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[175.159.121.134]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-309ef03bb7fsm9953249a91.9.2025.04.28.20.43.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 20:43:41 -0700 (PDT) From: Nick Chan Date: Tue, 29 Apr 2025 11:42:25 +0800 Subject: [PATCH RESEND v6 01/21] dt-bindings: arm: pmu: Add Apple A7-A11 SoC CPU PMU compatibles Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250429-apple-cpmu-v6-1-ed21815f0c3f@gmail.com> References: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> In-Reply-To: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1102; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=nvc6B3SNJrX+OFSnYkWwiXKVem6neRj112hzdXP5HLQ=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoEErjd3c1yTBwKCGhxeXkedW/lfSOfnH23+dzW l2135x2zHGJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaBBK4wAKCRABygi3psUI JLgGEACdUJeDNRMtqm3nhxyhEQAtsOix+3CT7D/67Vr7UWwXPJP2Oh+1DwSLzbn/zFkT9cugxIm GnSmZ4m2NYOn2WoAUS8F7cwsdDNGku8hnOj9A7YESw3yavZ6LVysiB63Iv4cSXfSxG3nB2YAq6K AgKxNOrluLF+fR+2zdUEkbhiV6pyZKtNCyQZPhUeRmDQXbEiBXgJ2UKA/N4pZc7c3YMbky2BSej +0eDrhVaQKHqmz5s+9Uh//vS8JStXzwFfiWjuD+mNFrdlf8ZKy9dZYvKJccDRO4/JIm6VLxIdtL t0CdhX8lL3BLVxOJ104+qC2OlUGI2K0XruyV67ivUtr915c4YfnTxYa1dY6DcpzGGGLQn3RZSxJ 1rL09HBeggJZWWKpANaz2AHyoLthHE86+KhruR1m3MMu5+EkEgh6+rSXO6dbMnGpPVvLbFqhAQO //uuyVAsRC2uHgRUzt8rS0tXfx61BZDj1yK3UF7AjiVBDYZIpsPbhdD8/xO+Dn6Jj5AYISVg1y6 yUz4EbfU4tjfQGuc40RCBXX91X8TLxf3h+pY7p9qU5NQjuNSX0IS9+JCAQPJgJdQpEkOhHFH7vg Kxcqt8aLrBEv1oph/C+FeG1tPYwGHeEkseunNKO83OpZRsuw6iO0sfFheenVmHndUjkp+juqRFG kSxUqdmoqhoaJkA== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Document the compatibles for Apple A7-A11 SoC CPU PMU. Acked-by: Krzysztof Kozlowski Signed-off-by: Nick Chan --- Documentation/devicetree/bindings/arm/pmu.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation= /devicetree/bindings/arm/pmu.yaml index 295963a3cae799a54560557137dd6b3cf4bd00f9..3726e1b78c42f150cf1dc68a6b3= aa3541517c311 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -22,8 +22,14 @@ properties: - apm,potenza-pmu - apple,avalanche-pmu - apple,blizzard-pmu + - apple,cyclone-pmu - apple,firestorm-pmu + - apple,fusion-pmu - apple,icestorm-pmu + - apple,monsoon-pmu + - apple,mistral-pmu + - apple,twister-pmu + - apple,typhoon-pmu - arm,armv8-pmuv3 # Only for s/w models - arm,arm1136-pmu - arm,arm1176-pmu --=20 2.49.0 From nobody Sun Feb 8 04:34:39 2026 Received: from mail-pj1-f52.google.com (mail-pj1-f52.google.com [209.85.216.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9352426FDAB; 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Initialization is harmless in EL1 but it is still a weird thing to do. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index df9a28ba69dcfad6f33a0d18b620276b910a36ca..b800da3f7f61ffa972fcab5f24b= 42127f2c55ac6 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -646,8 +646,10 @@ static int m1_pmu_init(struct arm_pmu *cpu_pmu, u32 fl= ags) cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->set_event_filter =3D m1_pmu_set_event_filter; =20 - cpu_pmu->map_pmuv3_event =3D m1_pmu_map_pmuv3_event; - m1_pmu_init_pmceid(cpu_pmu); + if (is_hyp_mode_available()) { + cpu_pmu->map_pmuv3_event =3D m1_pmu_map_pmuv3_event; + m1_pmu_init_pmceid(cpu_pmu); + } =20 bitmap_set(cpu_pmu->cntr_mask, 0, M1_PMU_NR_COUNTERS); cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; --=20 2.49.0 From nobody Sun Feb 8 04:34:39 2026 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11B972741CE; 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[175.159.121.134]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-309ef03bb7fsm9953249a91.9.2025.04.28.20.43.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 20:43:47 -0700 (PDT) From: Nick Chan Date: Tue, 29 Apr 2025 11:42:27 +0800 Subject: [PATCH RESEND v6 03/21] drivers/perf: apple_m1: Support per-implementation event tables Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250429-apple-cpmu-v6-3-ed21815f0c3f@gmail.com> References: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> In-Reply-To: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5785; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=EJFsNO1IGYgWw/sW/3l8ohSThIK8Gp7CsvED/Dkp2Hc=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoEErjTX35Fv0E0u7EqQ2vfEHXscywKJuACvG2/ SL3nVvFSSCJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaBBK4wAKCRABygi3psUI JDZnD/0RjQRenoIjFQor8g0BlsVEW7CRgD5aDQlBaqF65QKmTqkAgwKBAzziC7Ixrjm9/+MOMNX doPjI3XBJ4whqE6O6LZ2888SGla7RDLsm8xYdHZsm3MmiOnxZb28SILzJaXPQ3ebJUs4S9Kfn/9 T3y8lq6DBAtqOits0gDllR4v80bfZy4raL8nGN0rgF0dA09N0KWI478JlxRx6sndo1IdSQ8shJm iXXIePzVhYuzf5GJVPteq6CDxMD6lfvqtIunfSdZemIS2LOGz5+J/6MUP1hODEXGbt4qpEW8Ep7 O2JMcOh6oPdndD+fI1MOcgdQ7EkNJkUHbyDeRlhIuqYdSMyoheR7VdIln5IeaiJ5lO2JrpIR2z7 nW+Z1wzMv70BEEM2sYKqQMYa6gn+JpRrlICLrxhT9bpUt7JeR2thocEsHIvkxxd+pC9UDmdc8kS Xz6K5JnBKKIH4VwBrSSIQycAw+7jZFiq/z8aKTs3v4SZ5gZF0Mpxv06ASuUh41oYApUzm5wo7cG pU7CP29JGA2lb8zclJ6u7WGgsSYeE0KOnFrJSwo+Xt/iKODva4RAVAkkj2dLMAdSfDPc+UwbDyI lVYC0L3ok2AJr/FJqg61t2Rn6gcfXyk/78VRAK5uv6JTabxZX7e3F3R/qgG9QV3d5KWvdevelrF NaU4omtk+ZuCqGA== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Use per-implementation event tables to allow supporting implementations with a different list of events and event affinities. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 65 +++++++++++++++++++++++++------------= ---- 1 file changed, 40 insertions(+), 25 deletions(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index b800da3f7f61ffa972fcab5f24b42127f2c55ac6..d1bc850809993de044df8fd5d4d= fc61341482ee7 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -43,9 +43,6 @@ * moment, we don't really need to distinguish between the two because we * know next to nothing about the events themselves, and we already have * per cpu-type PMU abstractions. - * - * If we eventually find out that the events are different across - * implementations, we'll have to introduce per cpu-type tables. */ enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, @@ -494,11 +491,12 @@ static void m1_pmu_write_counter(struct perf_event *e= vent, u64 value) isb(); } =20 -static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, - struct perf_event *event) +static int apple_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event, + const u16 event_affinities[M1_PMU_CFG_EVENT]) { unsigned long evtype =3D event->hw.config_base & M1_PMU_CFG_EVENT; - unsigned long affinity =3D m1_pmu_event_affinity[evtype]; + unsigned long affinity =3D event_affinities[evtype]; int idx; =20 /* @@ -517,6 +515,12 @@ static int m1_pmu_get_event_idx(struct pmu_hw_events *= cpuc, return -EAGAIN; } =20 +static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, m1_pmu_event_affinity); +} + static void m1_pmu_clear_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -544,7 +548,8 @@ static void m1_pmu_stop(struct arm_pmu *cpu_pmu) __m1_pmu_set_mode(PMCR0_IMODE_OFF); } =20 -static int m1_pmu_map_event(struct perf_event *event) +static int apple_pmu_map_event_47(struct perf_event *event, + const unsigned int (*perf_map)[]) { /* * Although the counters are 48bit wide, bit 47 is what @@ -552,18 +557,29 @@ static int m1_pmu_map_event(struct perf_event *event) * being 47bit wide to mimick the behaviour of the ARM PMU. */ event->hw.flags |=3D ARMPMU_EVT_47BIT; - return armpmu_map_event(event, &m1_pmu_perf_map, NULL, M1_PMU_CFG_EVENT); + return armpmu_map_event(event, perf_map, NULL, M1_PMU_CFG_EVENT); } =20 -static int m2_pmu_map_event(struct perf_event *event) +static int apple_pmu_map_event_63(struct perf_event *event, + const unsigned int (*perf_map)[]) { /* - * Same deal as the above, except that M2 has 64bit counters. + * Same deal as the above, except with 64bit counters. * Which, as far as we're concerned, actually means 63 bits. * Yes, this is getting awkward. */ event->hw.flags |=3D ARMPMU_EVT_63BIT; - return armpmu_map_event(event, &m1_pmu_perf_map, NULL, M1_PMU_CFG_EVENT); + return armpmu_map_event(event, perf_map, NULL, M1_PMU_CFG_EVENT); +} + +static int m1_pmu_map_event(struct perf_event *event) +{ + return apple_pmu_map_event_47(event, &m1_pmu_perf_map); +} + +static int m2_pmu_map_event(struct perf_event *event) +{ + return apple_pmu_map_event_63(event, &m1_pmu_perf_map); } =20 static int m1_pmu_map_pmuv3_event(unsigned int eventsel) @@ -624,25 +640,16 @@ static int m1_pmu_set_event_filter(struct hw_perf_eve= nt *event, return 0; } =20 -static int m1_pmu_init(struct arm_pmu *cpu_pmu, u32 flags) +static int apple_pmu_init(struct arm_pmu *cpu_pmu) { cpu_pmu->handle_irq =3D m1_pmu_handle_irq; cpu_pmu->enable =3D m1_pmu_enable_event; cpu_pmu->disable =3D m1_pmu_disable_event; cpu_pmu->read_counter =3D m1_pmu_read_counter; cpu_pmu->write_counter =3D m1_pmu_write_counter; - cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->clear_event_idx =3D m1_pmu_clear_event_idx; cpu_pmu->start =3D m1_pmu_start; cpu_pmu->stop =3D m1_pmu_stop; - - if (flags & ARMPMU_EVT_47BIT) - cpu_pmu->map_event =3D m1_pmu_map_event; - else if (flags & ARMPMU_EVT_63BIT) - cpu_pmu->map_event =3D m2_pmu_map_event; - else - return WARN_ON(-EINVAL); - cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->set_event_filter =3D m1_pmu_set_event_filter; =20 @@ -661,25 +668,33 @@ static int m1_pmu_init(struct arm_pmu *cpu_pmu, u32 f= lags) static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_icestorm_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_47BIT); + cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + return apple_pmu_init(cpu_pmu); } =20 static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_firestorm_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_47BIT); + cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + return apple_pmu_init(cpu_pmu); } =20 static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_avalanche_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_63BIT); + cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; + cpu_pmu->map_event =3D m2_pmu_map_event; + return apple_pmu_init(cpu_pmu); } =20 static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_blizzard_pmu"; - return m1_pmu_init(cpu_pmu, ARMPMU_EVT_63BIT); + cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; + cpu_pmu->map_event =3D m2_pmu_map_event; + return apple_pmu_init(cpu_pmu); } =20 static const struct of_device_id m1_pmu_of_device_ids[] =3D { --=20 2.49.0 From nobody Sun Feb 8 04:34:39 2026 Received: from mail-pg1-f175.google.com (mail-pg1-f175.google.com [209.85.215.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 598FD274656; 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[175.159.121.134]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-309ef03bb7fsm9953249a91.9.2025.04.28.20.43.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 20:43:51 -0700 (PDT) From: Nick Chan Date: Tue, 29 Apr 2025 11:42:28 +0800 Subject: [PATCH RESEND v6 04/21] drivers/perf: apple_m1: Support a per-implementation number of counters Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250429-apple-cpmu-v6-4-ed21815f0c3f@gmail.com> References: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> In-Reply-To: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4845; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=BTD9OzZ4+bVdpzPnyX6mWog1RpRVl3h0ilCKcAXUUSU=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoEErjGxMUZXaCzNA+hDn0NL7rxEmDrzluCX9Ao OjQpnaIA+eJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaBBK4wAKCRABygi3psUI JKyfD/9QQMeNunFe+b3VOtj8xNDZd/QUQNnQSmNK3PYh94BR8kVUufLOaLtzMFbLeFAttpRWVRR mU9QI7EY9OIlac+LBWOUXqC34qW0Xorq0TtpeC61jGxyrdQWkMLdiWPN23tDWH0DJqm/TNZG+x/ 9wdOCg+zMn27lEMPEzMHs2N6AD3E4wbYgQpW3o6IiBvuJsDdLZMJ2CrXHuLcm2/r+1/h02QJoLj GoxTF2Ywb36NWSB4Oplg5gXGSHousJhC9VJvoKc4UQhOpjnLI3UbDfF1aDSyXiAkGtctY+oluVj Ei6cvbpSLoxb99ffFGq0OCQYJZLgEBEAFyhWx9QblsEQRoxiF0v+A2L4Jtk+JldMLFoypT6uiUo FoaGW8fM4SgAM/i08JjSCgaHCq+0y+fOiwgMNwG9QNxn3a93Wr9QF95WatZzV9PpnInhzCo0t02 Y0Wh6c+Ijob/QeWfr9xr4DLMzqxzSaNQsJRXbUGU1atSf8Q1vxkaR3wBaELeGNyCzm/I48saA0Z XidvWgpD5h/Yz8C6x3TbMlvVg7vxKSStg9CdRwSu3eBSl2ZubCs/WA+jTfSjNq1UzSlgcS5k5Po x5qo7EP0VkAy+cwbrCf0q1CJ9UZMLzA/HD1xAgv0hYA8yrhNQJTknJ1eLntmoNrupme7P5Bg5/h FqSx4bCjIhKmxkw== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Support a per-implementation number of counters to allow adding support for implementations with less counters. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index d1bc850809993de044df8fd5d4dfc61341482ee7..c03eb7acbb66790e17967d570c7= 1746f72e40867 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -20,6 +20,7 @@ #include =20 #define M1_PMU_NR_COUNTERS 10 +#define APPLE_PMU_MAX_NR_COUNTERS 10 =20 #define M1_PMU_CFG_EVENT GENMASK(7, 0) =20 @@ -459,7 +460,7 @@ static irqreturn_t m1_pmu_handle_irq(struct arm_pmu *cp= u_pmu) =20 regs =3D get_irq_regs(); =20 - for_each_set_bit(idx, cpu_pmu->cntr_mask, M1_PMU_NR_COUNTERS) { + for_each_set_bit(idx, cpu_pmu->cntr_mask, APPLE_PMU_MAX_NR_COUNTERS) { struct perf_event *event =3D cpuc->events[idx]; struct perf_sample_data data; =20 @@ -507,7 +508,7 @@ static int apple_pmu_get_event_idx(struct pmu_hw_events= *cpuc, * counting on the PMU at any given time, and by placing the * most constraining events first. */ - for_each_set_bit(idx, &affinity, M1_PMU_NR_COUNTERS) { + for_each_set_bit(idx, &affinity, APPLE_PMU_MAX_NR_COUNTERS) { if (!test_and_set_bit(idx, cpuc->used_mask)) return idx; } @@ -602,13 +603,13 @@ static void m1_pmu_init_pmceid(struct arm_pmu *pmu) } } =20 -static void m1_pmu_reset(void *info) +static void apple_pmu_reset(void *info, u32 counters) { int i; =20 __m1_pmu_set_mode(PMCR0_IMODE_OFF); =20 - for (i =3D 0; i < M1_PMU_NR_COUNTERS; i++) { + for (i =3D 0; i < counters; i++) { m1_pmu_disable_counter(i); m1_pmu_disable_counter_interrupt(i); m1_pmu_write_hw_counter(0, i); @@ -617,6 +618,11 @@ static void m1_pmu_reset(void *info) isb(); } =20 +static void m1_pmu_reset(void *info) +{ + apple_pmu_reset(info, M1_PMU_NR_COUNTERS); +} + static int m1_pmu_set_event_filter(struct hw_perf_event *event, struct perf_event_attr *attr) { @@ -640,7 +646,7 @@ static int m1_pmu_set_event_filter(struct hw_perf_event= *event, return 0; } =20 -static int apple_pmu_init(struct arm_pmu *cpu_pmu) +static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32 counters) { cpu_pmu->handle_irq =3D m1_pmu_handle_irq; cpu_pmu->enable =3D m1_pmu_enable_event; @@ -650,7 +656,6 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu) cpu_pmu->clear_event_idx =3D m1_pmu_clear_event_idx; cpu_pmu->start =3D m1_pmu_start; cpu_pmu->stop =3D m1_pmu_stop; - cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->set_event_filter =3D m1_pmu_set_event_filter; =20 if (is_hyp_mode_available()) { @@ -658,7 +663,7 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu) m1_pmu_init_pmceid(cpu_pmu); } =20 - bitmap_set(cpu_pmu->cntr_mask, 0, M1_PMU_NR_COUNTERS); + bitmap_set(cpu_pmu->cntr_mask, 0, counters); cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =3D &m1_pmu_format_attr_g= roup; return 0; @@ -670,7 +675,8 @@ static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) cpu_pmu->name =3D "apple_icestorm_pmu"; cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m1_pmu_map_event; - return apple_pmu_init(cpu_pmu); + cpu_pmu->reset =3D m1_pmu_reset; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) @@ -678,7 +684,8 @@ static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) cpu_pmu->name =3D "apple_firestorm_pmu"; cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m1_pmu_map_event; - return apple_pmu_init(cpu_pmu); + cpu_pmu->reset =3D m1_pmu_reset; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pmu) @@ -686,7 +693,8 @@ static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pm= u) cpu_pmu->name =3D "apple_avalanche_pmu"; cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m2_pmu_map_event; - return apple_pmu_init(cpu_pmu); + cpu_pmu->reset =3D m1_pmu_reset; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) @@ -694,7 +702,8 @@ static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) cpu_pmu->name =3D "apple_blizzard_pmu"; cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m2_pmu_map_event; - return apple_pmu_init(cpu_pmu); + cpu_pmu->reset =3D m1_pmu_reset; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); 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[175.159.121.134]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-309ef03bb7fsm9953249a91.9.2025.04.28.20.43.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 20:43:54 -0700 (PDT) From: Nick Chan Date: Tue, 29 Apr 2025 11:42:29 +0800 Subject: [PATCH RESEND v6 05/21] drivers/perf: apple_m1: Support configuring counters for 32-bit EL0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250429-apple-cpmu-v6-5-ed21815f0c3f@gmail.com> References: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> In-Reply-To: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2122; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=ow2nagzt8cdbi88jV06ZnLC5cMis8xMzKWgyHSgosSQ=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoEErjmkrzSmluSHWpPcLuLDWP98UII4msj5kA2 ggHtP3TV8uJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaBBK4wAKCRABygi3psUI JMfzD/wOvdaDI0puKAZ/mBBR/RM2CGIJHx1W73k4qAImQG2d7LjX6ZB1XJYDIH31FYuSz1EUOUR PsUNC9HgogHIa+HwSQXOm3gIsNqcdPFTf2wrmt/U0FlGJ/3Va2M2fZqO1cR6Rqa/U3FvgdWPioZ gz8QMUiIAcik5zNGkfAA2lC8Q9OxP9fLjQRib920ucOuxgyDUecskWWgNkTAED0ajkgBBSuUHvR Rw058GP5Kq/4SwcSGpybBCjuP/lvZ8kmLFWUORqtZQef8pQH/L8vFstLXUSumAlu4azAipJHbSw HgA4gIslgn+wsTMJIM8AYS3qgjyH8+3hGjaf2Dr6OiG3qHT9vyoezxjPidCA4OpR+iIqbO3TWyT As1nv47Ka4snM5MaX7s/6CHpWlXrMVFMIZ08EZjHJo3nU9f0RxYqMizdkR37xJkyswIrg2T5bvS ctfh68fdTC8I9pu0VhjjXmXI6lHmr13+X7DETjsC2BYJgh5+YHpWj+iEHUB9kWJXPzh7MCh/f2a tnoNTqsK1d8Z1dG7TyVOzW2leAENkYuxtuswY1k9xxBQu41GR+Pb2LxfI2lGp1WS4TrGoUQDMKM yPNaHFLi53Z7QlcrlQjrFOzz/k1tD+SmH0b6HSVEnpMB6SSHzpH4UE0Z4ZoIHG/p7o9d/wZPGFV i60irA/fg1MBlzA== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for configuring counters for 32-bit EL0 to allow adding support for implementations with 32-bit EL0. For documentation purposes, also add the bitmask for configuring counters for 64-bit EL3. Signed-off-by: Nick Chan --- arch/arm64/include/asm/apple_m1_pmu.h | 3 +++ drivers/perf/apple_m1_cpu_pmu.c | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/arch/arm64/include/asm/apple_m1_pmu.h b/arch/arm64/include/asm= /apple_m1_pmu.h index 02e05d05851f739b985bf416f1aa3baeafd691dc..6e238043e0dc2360c4fd507dc6a= 0eb7e055d2d6f 100644 --- a/arch/arm64/include/asm/apple_m1_pmu.h +++ b/arch/arm64/include/asm/apple_m1_pmu.h @@ -38,8 +38,11 @@ =20 #define SYS_IMP_APL_PMCR1_EL1 sys_reg(3, 1, 15, 1, 0) #define SYS_IMP_APL_PMCR1_EL12 sys_reg(3, 1, 15, 7, 2) +#define PMCR1_COUNT_A32_EL0_0_7 GENMASK(7, 0) #define PMCR1_COUNT_A64_EL0_0_7 GENMASK(15, 8) #define PMCR1_COUNT_A64_EL1_0_7 GENMASK(23, 16) +#define PMCR1_COUNT_A64_EL3_0_7 GENMASK(31, 24) +#define PMCR1_COUNT_A32_EL0_8_9 GENMASK(33, 32) #define PMCR1_COUNT_A64_EL0_8_9 GENMASK(41, 40) #define PMCR1_COUNT_A64_EL1_8_9 GENMASK(49, 48) =20 diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index c03eb7acbb66790e17967d570c71746f72e40867..f2566a0f8d330fdc0d71ae298f1= 6ee9700a13c23 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -348,10 +348,16 @@ static void __m1_pmu_configure_event_filter(unsigned = int index, bool user, case 0 ... 7: user_bit =3D BIT(get_bit_offset(index, PMCR1_COUNT_A64_EL0_0_7)); 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[175.159.121.134]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-309ef03bb7fsm9953249a91.9.2025.04.28.20.43.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 20:43:57 -0700 (PDT) From: Nick Chan Date: Tue, 29 Apr 2025 11:42:30 +0800 Subject: [PATCH RESEND v6 06/21] drivers/perf: apple_m1: Support per-implementation PMU startup Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250429-apple-cpmu-v6-6-ed21815f0c3f@gmail.com> References: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> In-Reply-To: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2178; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=XuN7zsZ7YOoemig6fmya2Ywu9aWxTuisbfQnSd0HHz8=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoEErkVcoNrjaCyRf0B+oVVlF/FnWvNI8GVPL/9 /6IEObFdLmJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaBBK5AAKCRABygi3psUI JHcRD/43EY45WDCCOHH/tCk4vG6bMpTVYoxMtOmM3AG6ssXxy+0LPTgCeIbIKhrKVlPPNNF15Kx 2zGMBcMedxpKxGE38naXV4W9pnSlKLwJsrRJfFtmn/wRrmqtgOh4HEGmrCAtd+1vgop0WVdjXSe WJxwrIfA3rtr1qDT3uvdrNqzAMQUuVIK5bxK3IZmaMccEwowCeS4K3m0ljdCQhFlx8yK0JaNOde G9Wv6SCT9BPpcXL2yBqDA+qPdnx4pwghspuCxamgW//wFGOnDmUBA5RlUaOG7DtLTqn95yig8Mv 5UfX3iDNRv+h6/E+cbv74gTyGf9Y4FIsg2T6h0lgXSr1/zE3PyZMZobiHLwvMY/nG9cRoS4sHZs WK7bUTPwDGDdM/gF7sybcIDaj5FxG92PRuwVGxUV5XMuDx7/JeOYaQc6jz5cixN+6oLsmCNDP4d r5dLJcUTVkVLbn64bkXAhGZ0fLqeuPQrNqXTL6I5m7PDPaMLg3Gre1oTHDBxa856QqxbTND1DM1 ezH6qet2/HJwAHenrwxnMfkwLEemNnvQTk4AWx2JjUjUw84hUbaX2khnnQrsEiJ5BqCzv5DwAzR jeDLZCiJrVFmi2aOB+LGw4dhCyMoe+AlsehCTNQ+3R0eu/4q5K0K29drrMCGgiC1XWEDjTpEXGZ jvbwtgkXUgZOdFA== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Support for implementations that deliver its interrupts in ways other than FIQ will be added, which requires a per-implementation startup function. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index f2566a0f8d330fdc0d71ae298f16ee9700a13c23..38fb9200369c11d0d7674bec4f3= 50915c67352b9 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -660,7 +660,6 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32 = counters) cpu_pmu->read_counter =3D m1_pmu_read_counter; cpu_pmu->write_counter =3D m1_pmu_write_counter; cpu_pmu->clear_event_idx =3D m1_pmu_clear_event_idx; - cpu_pmu->start =3D m1_pmu_start; cpu_pmu->stop =3D m1_pmu_stop; cpu_pmu->set_event_filter =3D m1_pmu_set_event_filter; =20 @@ -682,6 +681,7 @@ static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m1_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 @@ -691,6 +691,7 @@ static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m1_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 @@ -700,6 +701,7 @@ static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pm= u) cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m2_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 @@ -709,6 +711,7 @@ static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m2_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 --=20 2.49.0 From nobody Sun Feb 8 04:34:39 2026 Received: from mail-pj1-f53.google.com (mail-pj1-f53.google.com [209.85.216.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74D98274FEE; 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[175.159.121.134]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-309ef03bb7fsm9953249a91.9.2025.04.28.20.43.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 20:44:01 -0700 (PDT) From: Nick Chan Date: Tue, 29 Apr 2025 11:42:31 +0800 Subject: [PATCH RESEND v6 07/21] drivers/perf: apple_m1: Support per-implementation event attr group Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250429-apple-cpmu-v6-7-ed21815f0c3f@gmail.com> References: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> In-Reply-To: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2222; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=yx4ulzghzXPNnasdFXmt4DIvCjCuPnUboqBEbKM2bdE=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoEErkGoM2RWg0VDlbXiGWY/HfVc4yzBpXpB7XY woxK5/rLeOJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaBBK5AAKCRABygi3psUI JMDrEACtYSUEFb/komcO9xfM4+iYf4PfbQ9GJmuP6RrVfz23Yo2dm29bjUoeAwfvld16KTouLrg DBM5vBZTQOhc8nVNTh9NRNMsYbn1Zffep0SeMhQUDEBNb6NIXhiOHrTY8Nc8KTew4jtAm/h5VmN q2t5U+9QXA8+oV6FpBgIEfM66Rli70AIGdTkcyzZsOSx+cPOdM3B3YPLWGCywlRky0nxD2sD6uc Sch4WVH6GF/vpAodNYpe8t/BxxKyR2RAz3l1bvf2EmjmrOzLRt9L/GfT/YAE91wWePlgA/rdDP9 xpEWOJRDVCdXgBAGqVz8npNYMAxC4iCRNFS4g7zhHs8iswoYTYOA4teUDlsHmZKJ2fS4QfE5+d4 IQc63gns7yaojgY8npYL6c0aK9ZmVkpAzLrrBe0RrR/Q0eedgs5BBDjRudO7l2Rk/hX+RkPrOWp 5WaGpOv6mZQHQuAtb7+im0jH02X7gcRCZMOUxAFtMimUic5fFIl1yK43fT9sibB4yuh+QN2sAvk eEs5+Rxm/2Jl2VpRiTfLtYdwYvtHu8c+KywQyaVsSBaOHfIF4/TIoeijKvpiembgYXRyYm+nPlU 9SL5FMHxGt40EVGE0RfF7IlfYbfCsTjHw2fs9g7LqaTGstLqxFBud1C3kRfxhtYthe5IR++rsCu VV1MRAyn8hGlwpg== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 To support implementations with different event numbers for cycles or instruction events, event attr groups needs to be per-implementation. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index 38fb9200369c11d0d7674bec4f350915c67352b9..523ad37a07521692206cc438b8d= 777f505506c7e 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -669,7 +669,6 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32 = counters) } =20 bitmap_set(cpu_pmu->cntr_mask, 0, counters); - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =3D &m1_pmu_format_attr_g= roup; return 0; } @@ -682,6 +681,7 @@ static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) cpu_pmu->map_event =3D m1_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 @@ -692,6 +692,7 @@ static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) cpu_pmu->map_event =3D m1_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 @@ -702,6 +703,7 @@ static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pm= u) cpu_pmu->map_event =3D m2_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 @@ -712,6 +714,7 @@ static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) cpu_pmu->map_event =3D m2_pmu_map_event; cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 --=20 2.49.0 From nobody Sun Feb 8 04:34:39 2026 Received: from mail-pg1-f179.google.com (mail-pg1-f179.google.com [209.85.215.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F7EF2750E1; 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[175.159.121.134]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-309ef03bb7fsm9953249a91.9.2025.04.28.20.44.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 20:44:04 -0700 (PDT) From: Nick Chan Date: Tue, 29 Apr 2025 11:42:32 +0800 Subject: [PATCH RESEND v6 08/21] drivers/perf: apple_m1: Add Apple A7 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250429-apple-cpmu-v6-8-ed21815f0c3f@gmail.com> References: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> In-Reply-To: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11055; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=UJmXcVKIX5Xx7roTLsmv1+h5M1KahUJPMeW8SWgLQkE=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoEErk1LQxrrHpQ9XCqEfIl2j+6hyax8d7/96Z4 UlyvzC3nMuJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaBBK5AAKCRABygi3psUI JDRID/0cwOydVHHZgBSJMEdJnKSgrdrFoBHWwL8VyLaOf+xN+i9BpFxYVAwEIHqjdy0infxz3E4 TsZzUxzDQvjkRJ7fsfaoj7nTaNUOBzZUgjYWhN0yCrgM1Ip6ogHat8WGx5rtfftCWV6zTpIha3h EtdIFGzhPWM7xrivwmOnv0zwWbIQ1ThH9h9zP+NlmasUuxhU4dfNfZBI8Zs41K5oKw+01Wa7KSZ EVyJbCK92xr3PZZQhEcmPTNfCe6JlVucxxog+DfAEqFj7Fet1eQ74z76M4I5IAqw56T7w13OMvc NXbQbkoliy0LkH+DFcj9FBAhGHA+H1H68BpfdGzrS7TKU+VQjmw2m4CdHEgwc0mDS3QusuSfwKj yvGcxIPHvGikVSIrlzGFb4WZxP8d8hYS16pz5YmsocPb18y/6YMgT+KyPN5/IClq7FgZ8qRbYBe csvEztu5kGnCaxrki0SU4UT5JSu/WessZha2c4Kzg/XaOrq8OzmlBJau5D6BbfaPAjBjuHftHHc L76cs2M/5sloNhon8jwENCAOg5aQjfC83k2C3KUUriaZDPf25PgE5sE8A4O4QN12w8RLDPEXje9 OxxZMjcwRCfza3Lnt0RBfsb43ifTTV84lLnloIoEvqG9i+jCp7fj4P+0hK3qfkv+GUqYTmuQj4i s+9pwuc+7SrxH9A== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for the CPU PMU found in the Apple A7 SoC. The PMU has 8 counters and a very different event layout compared to the M1 PMU. Interrupts are delivered as IRQs instead of FIQs like on the M1. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 190 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 190 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index 523ad37a07521692206cc438b8d777f505506c7e..3c03d0e99ddaf90605cb8dafa68= ab8770d371a05 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -19,6 +19,7 @@ #include #include =20 +#define A7_PMU_NR_COUNTERS 8 #define M1_PMU_NR_COUNTERS 10 #define APPLE_PMU_MAX_NR_COUNTERS 10 =20 @@ -45,6 +46,143 @@ * know next to nothing about the events themselves, and we already have * per cpu-type PMU abstractions. */ + +enum a7_pmu_events { + A7_PMU_PERFCTR_INST_ALL =3D 0x0, + A7_PMU_PERFCTR_UNKNOWN_1 =3D 0x1, + A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A7_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0x10, + A7_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0x11, + A7_PMU_PERFCTR_BIU_UPSTREAM_CYCLE =3D 0x19, + A7_PMU_PERFCTR_BIU_DOWNSTREAM_CYCLE =3D 0x20, + A7_PMU_PERFCTR_L2C_AGENT_LD =3D 0x22, + A7_PMU_PERFCTR_L2C_AGENT_LD_MISS =3D 0x23, + A7_PMU_PERFCTR_L2C_AGENT_ST =3D 0x24, + A7_PMU_PERFCTR_L2C_AGENT_ST_MISS =3D 0x25, + A7_PMU_PERFCTR_SCHEDULE_UOP =3D 0x58, + A7_PMU_PERFCTR_MAP_REWIND =3D 0x61, + A7_PMU_PERFCTR_MAP_STALL =3D 0x62, + A7_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x6e, + A7_PMU_PERFCTR_INST_A32 =3D 0x78, + A7_PMU_PERFCTR_INST_T32 =3D 0x79, + A7_PMU_PERFCTR_INST_A64 =3D 0x7a, + A7_PMU_PERFCTR_INST_BRANCH =3D 0x7b, + A7_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x7c, + A7_PMU_PERFCTR_INST_BRANCH_RET =3D 0x7d, + A7_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x7e, + A7_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x81, + A7_PMU_PERFCTR_INST_BRANCH_COND =3D 0x82, + A7_PMU_PERFCTR_INST_INT_LD =3D 0x83, + A7_PMU_PERFCTR_INST_INT_ST =3D 0x84, + A7_PMU_PERFCTR_INST_INT_ALU =3D 0x85, + A7_PMU_PERFCTR_INST_SIMD_LD =3D 0x86, + A7_PMU_PERFCTR_INST_SIMD_ST =3D 0x87, + A7_PMU_PERFCTR_INST_SIMD_ALU =3D 0x88, + A7_PMU_PERFCTR_INST_LDST =3D 0x89, + A7_PMU_PERFCTR_UNKNOWN_8d =3D 0x8d, + A7_PMU_PERFCTR_UNKNOWN_8e =3D 0x8e, + A7_PMU_PERFCTR_UNKNOWN_8f =3D 0x8f, + A7_PMU_PERFCTR_UNKNOWN_90 =3D 0x90, + A7_PMU_PERFCTR_UNKNOWN_93 =3D 0x93, + A7_PMU_PERFCTR_UNKNOWN_94 =3D 0x94, + A7_PMU_PERFCTR_UNKNOWN_95 =3D 0x95, + A7_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0x96, + A7_PMU_PERFCTR_L1D_TLB_MISS =3D 0x97, + A7_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0x98, + A7_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0x99, + A7_PMU_PERFCTR_UNKNOWN_9b =3D 0x9b, + A7_PMU_PERFCTR_LD_UNIT_UOP =3D 0x9c, + A7_PMU_PERFCTR_ST_UNIT_UOP =3D 0x9d, + A7_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0x9e, + A7_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A7_PMU_PERFCTR_LDST_X64_UOP =3D 0xa7, + A7_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xb4, + A7_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xb5, + A7_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xb6, + A7_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xb9, + A7_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xba, + A7_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xbb, + A7_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xbd, + A7_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xbf, + A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xc0, + A7_PMU_PERFCTR_UNKNOWN_c1 =3D 0xc1, + A7_PMU_PERFCTR_UNKNOWN_c4 =3D 0xc4, + A7_PMU_PERFCTR_UNKNOWN_c5 =3D 0xc5, + A7_PMU_PERFCTR_UNKNOWN_c6 =3D 0xc6, + A7_PMU_PERFCTR_UNKNOWN_c8 =3D 0xc8, + A7_PMU_PERFCTR_UNKNOWN_ca =3D 0xca, + A7_PMU_PERFCTR_UNKNOWN_cb =3D 0xcb, + A7_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xce, + A7_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xcf, + A7_PMU_PERFCTR_UNKNOWN_f5 =3D 0xf5, + A7_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A7_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A7_PMU_PERFCTR_UNKNOWN_f8 =3D 0xf8, + A7_PMU_PERFCTR_UNKNOWN_fd =3D 0xfd, + A7_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A7_PMU_CFG_COUNT_USER =3D BIT(8), + A7_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a7_pmu_event_affinity[A7_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A7_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A7_PMU_PERFCTR_INST_ALL] =3D ANY_BUT_0_1 | BIT(1), + [A7_PMU_PERFCTR_UNKNOWN_1] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A7_PMU_PERFCTR_INST_A32] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_T32] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_A64] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_INT_ALU] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_SIMD_ALU] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_8d] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_8e] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_8f] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_90] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_93] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_94] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_95] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_ST] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_LD] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_9b] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_LD_UNIT_UOP] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_9f] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c1] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c4] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c5] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c6] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_c8] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_ca] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_cb] =3D ONLY_5_6_7, + [A7_PMU_PERFCTR_UNKNOWN_f5] =3D ONLY_2_4_6, + [A7_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_2_4_6, + [A7_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_2_4_6, + [A7_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -165,6 +303,14 @@ static const u16 m1_pmu_event_affinity[M1_PMU_PERFCTR_= LAST + 1] =3D { [M1_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, }; =20 +static const unsigned int a7_pmu_perf_map[PERF_COUNT_HW_MAX] =3D { + PERF_MAP_ALL_UNSUPPORTED, + [PERF_COUNT_HW_CPU_CYCLES] =3D A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE, + [PERF_COUNT_HW_INSTRUCTIONS] =3D A7_PMU_PERFCTR_INST_ALL, + [PERF_COUNT_HW_BRANCH_MISSES] =3D A7_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC, + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =3D A7_PMU_PERFCTR_INST_BRANCH +}; + static const unsigned m1_pmu_perf_map[PERF_COUNT_HW_MAX] =3D { PERF_MAP_ALL_UNSUPPORTED, [PERF_COUNT_HW_CPU_CYCLES] =3D M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE, @@ -199,6 +345,17 @@ static ssize_t m1_pmu_events_sysfs_show(struct device = *dev, #define M1_PMU_EVENT_ATTR(name, config) \ PMU_EVENT_ATTR_ID(name, m1_pmu_events_sysfs_show, config) =20 +static struct attribute *a7_pmu_event_attrs[] =3D { + M1_PMU_EVENT_ATTR(cycles, A7_PMU_PERFCTR_CORE_ACTIVE_CYCLE), + M1_PMU_EVENT_ATTR(instructions, A7_PMU_PERFCTR_INST_ALL), + NULL, +}; + +static const struct attribute_group a7_pmu_events_attr_group =3D { + .name =3D "events", + .attrs =3D a7_pmu_event_attrs, +}; + static struct attribute *m1_pmu_event_attrs[] =3D { M1_PMU_EVENT_ATTR(cycles, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE), M1_PMU_EVENT_ATTR(instructions, M1_PMU_PERFCTR_INST_ALL), @@ -522,6 +679,12 @@ static int apple_pmu_get_event_idx(struct pmu_hw_event= s *cpuc, return -EAGAIN; } =20 +static int a7_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a7_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -545,6 +708,11 @@ static void __m1_pmu_set_mode(u8 mode) isb(); } =20 +static void a7_pmu_start(struct arm_pmu *cpu_pmu) +{ + __m1_pmu_set_mode(PMCR0_IMODE_AIC); +} + static void m1_pmu_start(struct arm_pmu *cpu_pmu) { __m1_pmu_set_mode(PMCR0_IMODE_FIQ); @@ -579,6 +747,11 @@ static int apple_pmu_map_event_63(struct perf_event *e= vent, return armpmu_map_event(event, perf_map, NULL, M1_PMU_CFG_EVENT); } =20 +static int a7_pmu_map_event(struct perf_event *event) +{ + return apple_pmu_map_event_47(event, &a7_pmu_perf_map); +} + static int m1_pmu_map_event(struct perf_event *event) { return apple_pmu_map_event_47(event, &m1_pmu_perf_map); @@ -624,6 +797,11 @@ static void apple_pmu_reset(void *info, u32 counters) isb(); } =20 +static void a7_pmu_reset(void *info) +{ + apple_pmu_reset(info, A7_PMU_NR_COUNTERS); +} + static void m1_pmu_reset(void *info) { apple_pmu_reset(info, M1_PMU_NR_COUNTERS); @@ -674,6 +852,17 @@ static int apple_pmu_init(struct arm_pmu *cpu_pmu, u32= counters) } =20 /* Device driver gunk */ +static int a7_pmu_cyclone_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_cyclone_pmu"; + cpu_pmu->get_event_idx =3D a7_pmu_get_event_idx; + cpu_pmu->map_event =3D a7_pmu_map_event; + cpu_pmu->reset =3D a7_pmu_reset; + cpu_pmu->start =3D a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &a7_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); 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[175.159.121.134]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-309ef03bb7fsm9953249a91.9.2025.04.28.20.44.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 20:44:08 -0700 (PDT) From: Nick Chan Date: Tue, 29 Apr 2025 11:42:33 +0800 Subject: [PATCH RESEND v6 09/21] drivers/perf: apple_m1: Add Apple A8/A8X support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250429-apple-cpmu-v6-9-ed21815f0c3f@gmail.com> References: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> In-Reply-To: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7313; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=W4HZa+NpM2ESOXzUAr4zGaMv7Cw7ppma9xh4UBE8JRI=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoEErkrpWpQSCX/WqDqgyrcwt2S/fTgdh2zsLxq MPo+ysA+++JAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaBBK5AAKCRABygi3psUI JMb+EACEwp3lUqLLbKMkz+2c27n5snoNXQx3oIc7EDYlhgVmTQCvdB7tueEjMX0SyO5gHz7X95C THV1yvng0QqNbO1EVEnUHVz8M4f6TzUAZhm0gUHmljwLsGGTr7BuSl6FA9Gt/kq9mClVfXQpsaD +DOafVzm1xDr4g2RLFaocI8tw61jAN+U5xC6zIDwSLbZ19mIxzV2hyDnwGx4afa59GZeZe7UZpw PAyxFWp0hQGKHOPM7kTIaTcUosdZxQAamS5A+xFkFcRYn7VxJX8f+aSR2wcTDfKpn9I8btGyy7d 3KLqCUtCFosnwLHcHI3Cux+akEb3w+k4sJkkPyNK60rtKrISA3BHOcgrjbLYMs1NXC3B175QGJZ Xc9RAfJUTXHt1kCBWSR1ttM+omjeGxFvrw8Eo4eeOCkSW0zeQTmu1fTqi3pqpOCutONa9RZWzte VIVTlmUEVh3vVLFKLfgpaXrnCrMJHg0zZm8mftJ8iqZKEc3oJzjNhezgKlu4puSE35xgqjQwjBI jlJsdsValwI9E4HJiqBJ2EUGmHnyYsxv2yWGsJyI7RUMNcUogsofDPpy1NH5Zy12r3xpgkiu0ER NTvLmtCszdAsKF4Iun4WU20mJpLKr/dPH6wd88Nw5Ash1ZXGZtmXe7/WMXKYpwMZd67VHIS3dVm 78NXLvACEEq++Ug== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for the CPU PMU found on the Apple A8, A8X SoCs. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 124 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 124 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index 3c03d0e99ddaf90605cb8dafa68ab8770d371a05..5739a85f3ae07c52f4ce91c4eda= 3e4bcdf91015d 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -28,6 +28,7 @@ #define ANY_BUT_0_1 GENMASK(9, 2) #define ONLY_2_TO_7 GENMASK(7, 2) #define ONLY_2_4_6 (BIT(2) | BIT(4) | BIT(6)) +#define ONLY_3_5_7 (BIT(3) | BIT(5) | BIT(7)) #define ONLY_5_6_7 (BIT(5) | BIT(6) | BIT(7)) =20 /* @@ -183,6 +184,111 @@ static const u16 a7_pmu_event_affinity[A7_PMU_PERFCTR= _LAST + 1] =3D { [A7_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, }; =20 +enum a8_pmu_events { + A8_PMU_PERFCTR_UNKNOWN_1 =3D 0x1, + A8_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A8_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0xa, + A8_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0xb, + A8_PMU_PERFCTR_BIU_UPSTREAM_CYCLE =3D 0x13, + A8_PMU_PERFCTR_BIU_DOWNSTREAM_CYCLE =3D 0x14, + A8_PMU_PERFCTR_L2C_AGENT_LD =3D 0x1a, + A8_PMU_PERFCTR_L2C_AGENT_LD_MISS =3D 0x1b, + A8_PMU_PERFCTR_L2C_AGENT_ST =3D 0x1c, + A8_PMU_PERFCTR_L2C_AGENT_ST_MISS =3D 0x1d, + A8_PMU_PERFCTR_SCHEDULE_UOP =3D 0x52, + A8_PMU_PERFCTR_MAP_REWIND =3D 0x75, + A8_PMU_PERFCTR_MAP_STALL =3D 0x76, + A8_PMU_PERFCTR_MAP_INT_UOP =3D 0x7b, + A8_PMU_PERFCTR_MAP_LDST_UOP =3D 0x7c, + A8_PMU_PERFCTR_MAP_SIMD_UOP =3D 0x7d, + A8_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x84, + A8_PMU_PERFCTR_INST_A32 =3D 0x8a, + A8_PMU_PERFCTR_INST_T32 =3D 0x8b, + A8_PMU_PERFCTR_INST_ALL =3D 0x8c, + A8_PMU_PERFCTR_INST_BRANCH =3D 0x8d, + A8_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x8e, + A8_PMU_PERFCTR_INST_BRANCH_RET =3D 0x8f, + A8_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x90, + A8_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x93, + A8_PMU_PERFCTR_INST_BRANCH_COND =3D 0x94, + A8_PMU_PERFCTR_INST_INT_LD =3D 0x95, + A8_PMU_PERFCTR_INST_INT_ST =3D 0x96, + A8_PMU_PERFCTR_INST_INT_ALU =3D 0x97, + A8_PMU_PERFCTR_INST_SIMD_LD =3D 0x98, + A8_PMU_PERFCTR_INST_SIMD_ST =3D 0x99, + A8_PMU_PERFCTR_INST_SIMD_ALU =3D 0x9a, + A8_PMU_PERFCTR_INST_LDST =3D 0x9b, + A8_PMU_PERFCTR_UNKNOWN_9c =3D 0x9c, + A8_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A8_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0xa0, + A8_PMU_PERFCTR_L1D_TLB_MISS =3D 0xa1, + A8_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0xa2, + A8_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0xa3, + A8_PMU_PERFCTR_LD_UNIT_UOP =3D 0xa6, + A8_PMU_PERFCTR_ST_UNIT_UOP =3D 0xa7, + A8_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0xa8, + A8_PMU_PERFCTR_LDST_X64_UOP =3D 0xb1, + A8_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xbf, + A8_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xc0, + A8_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xc1, + A8_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xc4, + A8_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xc5, + A8_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xc6, + A8_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xc8, + A8_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xca, + A8_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xcb, + A8_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xd3, + A8_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xd4, + A8_PMU_PERFCTR_FETCH_RESTART =3D 0xde, + A8_PMU_PERFCTR_UNKNOWN_f5 =3D 0xf5, + A8_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A8_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A8_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A8_PMU_CFG_COUNT_USER =3D BIT(8), + A8_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a8_pmu_event_affinity[A8_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A8_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A8_PMU_PERFCTR_UNKNOWN_1] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A8_PMU_PERFCTR_INST_A32] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_T32] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_ALL] =3D BIT(7) | BIT(1), + [A8_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_INT_ALU] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_SIMD_ALU] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_UNKNOWN_9c] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_UNKNOWN_9f] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A8_PMU_PERFCTR_UNKNOWN_f5] =3D ANY_BUT_0_1, + [A8_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_3_5_7, + [A8_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_3_5_7, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -685,6 +791,12 @@ static int a7_pmu_get_event_idx(struct pmu_hw_events *= cpuc, return apple_pmu_get_event_idx(cpuc, event, a7_pmu_event_affinity); } =20 +static int a8_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a8_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -863,6 +975,17 @@ static int a7_pmu_cyclone_init(struct arm_pmu *cpu_pmu) return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); } =20 +static int a8_pmu_typhoon_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_typhoon_pmu"; + cpu_pmu->get_event_idx =3D a8_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D a7_pmu_reset; + cpu_pmu->start =3D a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_icestorm_pmu"; @@ -912,6 +1035,7 @@ static const struct of_device_id m1_pmu_of_device_ids[= ] =3D { { .compatible =3D "apple,blizzard-pmu", .data =3D m2_pmu_blizzard_init, }, { .compatible =3D "apple,icestorm-pmu", .data =3D m1_pmu_ice_init, }, { .compatible =3D "apple,firestorm-pmu", .data =3D m1_pmu_fire_init, }, + { .compatible =3D "apple,typhoon-pmu", .data =3D a8_pmu_typhoon_init, }, { .compatible =3D "apple,cyclone-pmu", .data =3D a7_pmu_cyclone_init, }, { }, }; --=20 2.49.0 From nobody Sun Feb 8 04:34:39 2026 Received: from mail-pj1-f45.google.com (mail-pj1-f45.google.com [209.85.216.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B7AAA27585A; Tue, 29 Apr 2025 03:44:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.45 ARC-Seal: i=1; a=rsa-sha256; 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Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 121 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 121 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index 5739a85f3ae07c52f4ce91c4eda3e4bcdf91015d..0f59a22812a424ecd442e731a5c= 6b5be828be77c 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -289,6 +289,109 @@ static const u16 a8_pmu_event_affinity[A8_PMU_PERFCTR= _LAST + 1] =3D { [A8_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_3_5_7, }; =20 + +enum a9_pmu_events { + A9_PMU_PERFCTR_UNKNOWN_1 =3D 0x1, + A9_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A9_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0xa, + A9_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0xb, + A9_PMU_PERFCTR_L2C_AGENT_LD =3D 0x1a, + A9_PMU_PERFCTR_L2C_AGENT_LD_MISS =3D 0x1b, + A9_PMU_PERFCTR_L2C_AGENT_ST =3D 0x1c, + A9_PMU_PERFCTR_L2C_AGENT_ST_MISS =3D 0x1d, + A9_PMU_PERFCTR_SCHEDULE_UOP =3D 0x52, + A9_PMU_PERFCTR_MAP_REWIND =3D 0x75, + A9_PMU_PERFCTR_MAP_STALL =3D 0x76, + A9_PMU_PERFCTR_MAP_INT_UOP =3D 0x7c, + A9_PMU_PERFCTR_MAP_LDST_UOP =3D 0x7d, + A9_PMU_PERFCTR_MAP_SIMD_UOP =3D 0x7e, + A9_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x84, + A9_PMU_PERFCTR_INST_ALL =3D 0x8c, + A9_PMU_PERFCTR_INST_BRANCH =3D 0x8d, + A9_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x8e, + A9_PMU_PERFCTR_INST_BRANCH_RET =3D 0x8f, + A9_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x90, + A9_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x93, + A9_PMU_PERFCTR_INST_BRANCH_COND =3D 0x94, + A9_PMU_PERFCTR_INST_INT_LD =3D 0x95, + A9_PMU_PERFCTR_INST_INT_ST =3D 0x96, + A9_PMU_PERFCTR_INST_INT_ALU =3D 0x97, + A9_PMU_PERFCTR_INST_SIMD_LD =3D 0x98, + A9_PMU_PERFCTR_INST_SIMD_ST =3D 0x99, + A9_PMU_PERFCTR_INST_SIMD_ALU =3D 0x9a, + A9_PMU_PERFCTR_INST_LDST =3D 0x9b, + A9_PMU_PERFCTR_INST_BARRIER =3D 0x9c, + A9_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A9_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0xa0, + A9_PMU_PERFCTR_L1D_TLB_MISS =3D 0xa1, + A9_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0xa2, + A9_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0xa3, + A9_PMU_PERFCTR_LD_UNIT_UOP =3D 0xa6, + A9_PMU_PERFCTR_ST_UNIT_UOP =3D 0xa7, + A9_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0xa8, + A9_PMU_PERFCTR_LDST_X64_UOP =3D 0xb1, + A9_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC =3D 0xb3, + A9_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL =3D 0xb4, + A9_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xbf, + A9_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xc0, + A9_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xc1, + A9_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xc4, + A9_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xc5, + A9_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xc6, + A9_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xc8, + A9_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xca, + A9_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xcb, + A9_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xd3, + A9_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xd4, + A9_PMU_PERFCTR_MAP_DISPATCH_BUBBLE =3D 0xd6, + A9_PMU_PERFCTR_FETCH_RESTART =3D 0xde, + A9_PMU_PERFCTR_ST_NT_UOP =3D 0xe5, + A9_PMU_PERFCTR_LD_NT_UOP =3D 0xe6, + A9_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A9_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A9_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A9_PMU_CFG_COUNT_USER =3D BIT(8), + A9_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a9_pmu_event_affinity[A9_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A9_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A9_PMU_PERFCTR_UNKNOWN_1] =3D BIT(7), + [A9_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A9_PMU_PERFCTR_INST_ALL] =3D BIT(7) | BIT(1), + [A9_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_INT_ALU] =3D BIT(7), + [A9_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_SIMD_ALU] =3D BIT(7), + [A9_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BARRIER] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_UNKNOWN_9f] =3D BIT(7), + [A9_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_3_5_7, + [A9_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_3_5_7, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -797,6 +900,12 @@ static int a8_pmu_get_event_idx(struct pmu_hw_events *= cpuc, return apple_pmu_get_event_idx(cpuc, event, a8_pmu_event_affinity); } =20 +static int a9_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a9_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -986,6 +1095,17 @@ static int a8_pmu_typhoon_init(struct arm_pmu *cpu_pm= u) return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); } =20 +static int a9_pmu_twister_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_twister_pmu"; + cpu_pmu->get_event_idx =3D a9_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D a7_pmu_reset; + cpu_pmu->start =3D a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_icestorm_pmu"; @@ -1035,6 +1155,7 @@ static const struct of_device_id m1_pmu_of_device_ids= [] =3D { { .compatible =3D "apple,blizzard-pmu", .data =3D m2_pmu_blizzard_init, }, { .compatible =3D "apple,icestorm-pmu", .data =3D m1_pmu_ice_init, }, { .compatible =3D "apple,firestorm-pmu", .data =3D m1_pmu_fire_init, }, + { .compatible =3D "apple,twister-pmu", .data =3D a9_pmu_twister_init, }, { .compatible =3D "apple,typhoon-pmu", .data =3D a8_pmu_typhoon_init, }, { .compatible =3D "apple,cyclone-pmu", .data =3D a7_pmu_cyclone_init, }, { }, --=20 2.49.0 From nobody Sun Feb 8 04:34:39 2026 Received: from mail-pj1-f46.google.com (mail-pj1-f46.google.com [209.85.216.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DAA3C3D561; Tue, 29 Apr 2025 03:44:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[175.159.121.134]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-309ef03bb7fsm9953249a91.9.2025.04.28.20.44.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 20:44:14 -0700 (PDT) From: Nick Chan Date: Tue, 29 Apr 2025 11:42:35 +0800 Subject: [PATCH RESEND v6 11/21] drivers/perf: apple_m1: Add Apple A10/A10X/T2 Support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250429-apple-cpmu-v6-11-ed21815f0c3f@gmail.com> References: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> In-Reply-To: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7477; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=vhfbuGedj/1gevD9XOwj27XPecCoXIxQmzuoGb/VE9I=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoEErkRE7I1lSc2hehQL5HKF2Y7eSmL/SRlrTBQ E97855QAIeJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaBBK5AAKCRABygi3psUI JFHTD/9PG+LrDQ2eE10r5N+LBNbzChgV5owiZavJoNMoKbPH90Nms0AwXakDA/17+a1qDoFvSEk EhJ0xRIUGnENrANCCNnkaovil43FHfb46y88i8lng7YAIcxtXohz+W1tQCHkhZjqFsgX0CSLjTB 0hKuIIm3LuDNxLwa4em5CtmnLcjqJVcCs6/d+1Fu+xRL9Zeb1JODZiMTT54f3cAx/YBQuE/WCbo 3a/0VXcSVCgbrKg40tgkxqzTSK5mgjGPLWmcX6Ui1V7pEUS7JrF54rZrD5NhQ0zv3MO83L+QSJD iY2+QAqjLTZ+Gxp5G6rphPDDSWDKqjl4axB8PwPJ7i9KicN3ndaP3Q1AbvGn+WEJDxHZ6y1eO/V IgY6LhuCJXo/M1na0LP0xG+FzElyKtgET8aIXj9DbBfkPyzxDFhqKsBAqU6aK1xXgpGT6SH/Fbt b3hiJ2c52DlzfN1jkhlMPsSflCLoLx3yGGgPOpdFQjsVUKGFnFcwE8gDvKXbR+Oz6jVCVky4Ajf EfYLrRc+Gp7sfMXP7zG0LXrWuAC4eCvGWHedaoiL0f2+7oVmASf0tqSjZQDQWtCwD+Ym98JcO/P ol7421Y0llLbXxYtPwjcbfvRDff7uIGn5jMwzn6EU0m737zIKABaLR9tylwVeumXOvt/2GfSNO9 bqL2lGQdgixukIw== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for the CPU PMU found in the Apple A10, A10X, T2 SoCs. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 127 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 127 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index 0f59a22812a424ecd442e731a5c6b5be828be77c..4f65ca4ea24157bced11d42a4cb= bad5f2dd23d4a 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -392,6 +392,115 @@ static const u16 a9_pmu_event_affinity[A9_PMU_PERFCTR= _LAST + 1] =3D { [A9_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_3_5_7, }; =20 +enum a10_pmu_events { + A10_PMU_PERFCTR_RETIRE_UOP =3D 0x1, + A10_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A10_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0xa, + A10_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0xb, + A10_PMU_PERFCTR_L2C_AGENT_LD =3D 0x1a, + A10_PMU_PERFCTR_L2C_AGENT_LD_MISS =3D 0x1b, + A10_PMU_PERFCTR_L2C_AGENT_ST =3D 0x1c, + A10_PMU_PERFCTR_L2C_AGENT_ST_MISS =3D 0x1d, + A10_PMU_PERFCTR_SCHEDULE_UOP =3D 0x52, + A10_PMU_PERFCTR_MAP_REWIND =3D 0x75, + A10_PMU_PERFCTR_MAP_STALL =3D 0x76, + A10_PMU_PERFCTR_MAP_INT_UOP =3D 0x7c, + A10_PMU_PERFCTR_MAP_LDST_UOP =3D 0x7d, + A10_PMU_PERFCTR_MAP_SIMD_UOP =3D 0x7e, + A10_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x84, + A10_PMU_PERFCTR_INST_ALL =3D 0x8c, + A10_PMU_PERFCTR_INST_BRANCH =3D 0x8d, + A10_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x8e, + A10_PMU_PERFCTR_INST_BRANCH_RET =3D 0x8f, + A10_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x90, + A10_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x93, + A10_PMU_PERFCTR_INST_BRANCH_COND =3D 0x94, + A10_PMU_PERFCTR_INST_INT_LD =3D 0x95, + A10_PMU_PERFCTR_INST_INT_ST =3D 0x96, + A10_PMU_PERFCTR_INST_INT_ALU =3D 0x97, + A10_PMU_PERFCTR_INST_SIMD_LD =3D 0x98, + A10_PMU_PERFCTR_INST_SIMD_ST =3D 0x99, + A10_PMU_PERFCTR_INST_SIMD_ALU =3D 0x9a, + A10_PMU_PERFCTR_INST_LDST =3D 0x9b, + A10_PMU_PERFCTR_INST_BARRIER =3D 0x9c, + A10_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A10_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0xa0, + A10_PMU_PERFCTR_L1D_TLB_MISS =3D 0xa1, + A10_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0xa2, + A10_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0xa3, + A10_PMU_PERFCTR_LD_UNIT_UOP =3D 0xa6, + A10_PMU_PERFCTR_ST_UNIT_UOP =3D 0xa7, + A10_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0xa8, + A10_PMU_PERFCTR_LDST_X64_UOP =3D 0xb1, + A10_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC =3D 0xb3, + A10_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL =3D 0xb4, + A10_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xbf, + A10_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xc0, + A10_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xc1, + A10_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xc4, + A10_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xc5, + A10_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xc6, + A10_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xc8, + A10_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xca, + A10_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xcb, + A10_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xd3, + A10_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xd4, + A10_PMU_PERFCTR_MAP_DISPATCH_BUBBLE =3D 0xd6, + A10_PMU_PERFCTR_L1I_CACHE_MISS_DEMAND =3D 0xdb, + A10_PMU_PERFCTR_FETCH_RESTART =3D 0xde, + A10_PMU_PERFCTR_ST_NT_UOP =3D 0xe5, + A10_PMU_PERFCTR_LD_NT_UOP =3D 0xe6, + A10_PMU_PERFCTR_UNKNOWN_f5 =3D 0xf5, + A10_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A10_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A10_PMU_PERFCTR_UNKNOWN_f8 =3D 0xf8, + A10_PMU_PERFCTR_UNKNOWN_fd =3D 0xfd, + A10_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A10_PMU_CFG_COUNT_USER =3D BIT(8), + A10_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a10_pmu_event_affinity[A10_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A10_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A10_PMU_PERFCTR_RETIRE_UOP] =3D BIT(7), + [A10_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A10_PMU_PERFCTR_INST_ALL] =3D BIT(7) | BIT(1), + [A10_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_INT_ALU] =3D BIT(7), + [A10_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_SIMD_ALU] =3D BIT(7), + [A10_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_INST_BARRIER] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_UNKNOWN_9f] =3D BIT(7), + [A10_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A10_PMU_PERFCTR_UNKNOWN_f5] =3D ONLY_2_4_6, + [A10_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_2_4_6, + [A10_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_2_4_6, + [A10_PMU_PERFCTR_UNKNOWN_f8] =3D ONLY_2_TO_7, + [A10_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -906,6 +1015,12 @@ static int a9_pmu_get_event_idx(struct pmu_hw_events = *cpuc, return apple_pmu_get_event_idx(cpuc, event, a9_pmu_event_affinity); } =20 +static int a10_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a10_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -1106,6 +1221,17 @@ static int a9_pmu_twister_init(struct arm_pmu *cpu_p= mu) return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); } =20 +static int a10_pmu_fusion_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_fusion_pmu"; + cpu_pmu->get_event_idx =3D a10_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_icestorm_pmu"; @@ -1155,6 +1281,7 @@ static const struct of_device_id m1_pmu_of_device_ids= [] =3D { { .compatible =3D "apple,blizzard-pmu", .data =3D m2_pmu_blizzard_init, }, { .compatible =3D "apple,icestorm-pmu", .data =3D m1_pmu_ice_init, }, { .compatible =3D "apple,firestorm-pmu", .data =3D m1_pmu_fire_init, }, + { .compatible =3D "apple,fusion-pmu", .data =3D a10_pmu_fusion_init, }, { .compatible =3D "apple,twister-pmu", .data =3D a9_pmu_twister_init, }, { .compatible =3D "apple,typhoon-pmu", .data =3D a8_pmu_typhoon_init, }, { .compatible =3D "apple,cyclone-pmu", .data =3D a7_pmu_cyclone_init, }, --=20 2.49.0 From nobody Sun Feb 8 04:34:39 2026 Received: from mail-pg1-f173.google.com (mail-pg1-f173.google.com [209.85.215.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 625B22741C4; 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[175.159.121.134]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-309ef03bb7fsm9953249a91.9.2025.04.28.20.44.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 20:44:18 -0700 (PDT) From: Nick Chan Date: Tue, 29 Apr 2025 11:42:36 +0800 Subject: [PATCH RESEND v6 12/21] drivers/perf: apple_m1: Add Apple A11 Support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250429-apple-cpmu-v6-12-ed21815f0c3f@gmail.com> References: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> In-Reply-To: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7991; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=bj5kb18dtPBEIPtFZihdYphvX8kAvgW+oUnbFOmqNLw=; b=kA0DAAoBAcoIt6bFCCQByyZiAGgQSuSjptSr8vaJ+L0ZEayreUbPiKQ2bRsFB4eOVeG5ApgCw 4kCMwQAAQoAHRYhBEtSeHhcl6z3nDxogwHKCLemxQgkBQJoEErkAAoJEAHKCLemxQgkMVkQALKJ lm02DrwIC5WShN8NCOaZbjyxivkvq7Cv8bd98UBgEaCS9w+MmAm8pNz5z8cwhl/9z/XBykpPtpg 9dqMxD2U9UatIEfgSKUQjZGtVEcpUdvvQBs6qTzAqFzmNkCDywngaUI4Kb9iQkmFS5WEgU+XLf3 LJRl4tYO7h2aE81J5d4y6EByUO0B3XOjyvKhTFoHm29QjqBwNjY+uaSFn/EcaEoUFkCyX3WeRlI 7SDDsLNwp/dUfJAABVksGesFcIywiTDw7k6YCH5sK5gpxp43Ev2ol6Vha76Pj5rSvcI3dh7fCbS iiRKJRbQ2XQ6sFTpSCQt1bC4Oc4neE8/qggGc+ILkaxi110zqSN4r1rtO5v02u5HBha+NVf/oCi 0EnifMJHjbjiwNf5e44XwJKKvJ+dhPE95iLv1oAN1g+e6d3evef9/uwDPdGLK6xpFYgxm7k5EMX QB/FqrgRIpbFq8cvqac4WFhoW+8imCsFuJoWfgz/6IZeAKuNYr0foabA8Yrnw0gZRorzNG0PGVo gYhu5Iex9Sl6rKU2Rrahwr3jWZYiaiIx0HtWaKZqSe0IOMVmxV3H7FNkE3zbEskVQreF2Ob56ky Kwed/cnAJgmICicySAquZnYNsZphSxXKqOpw2cE0l8AkIKDFQJqzrENdF4IfSbtfZvFR62OKkKo GnL4Z X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for the CPU PMU found attached to the performance and efficiency cores of the Apple A11 SoCs. This PMU can deliver its interrupt via IRQ or FIQ. Use FIQ as that is faster. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 137 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 137 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index 4f65ca4ea24157bced11d42a4cbbad5f2dd23d4a..365b4ecaedb180fe88f15c675c4= 4e2f5ac916c25 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -501,6 +501,113 @@ static const u16 a10_pmu_event_affinity[A10_PMU_PERFC= TR_LAST + 1] =3D { [A10_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, }; =20 +enum a11_pmu_events { + A11_PMU_PERFCTR_RETIRE_UOP =3D 0x1, + A11_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A11_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0xa, + A11_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0xb, + A11_PMU_PERFCTR_SCHEDULE_UOP =3D 0x52, + A11_PMU_PERFCTR_MAP_REWIND =3D 0x75, + A11_PMU_PERFCTR_MAP_STALL =3D 0x76, + A11_PMU_PERFCTR_MAP_INT_UOP =3D 0x7c, + A11_PMU_PERFCTR_MAP_LDST_UOP =3D 0x7d, + A11_PMU_PERFCTR_MAP_SIMD_UOP =3D 0x7e, + A11_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x84, + A11_PMU_PERFCTR_INST_A32 =3D 0x8a, + A11_PMU_PERFCTR_INST_T32 =3D 0x8b, + A11_PMU_PERFCTR_INST_ALL =3D 0x8c, + A11_PMU_PERFCTR_INST_BRANCH =3D 0x8d, + A11_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x8e, + A11_PMU_PERFCTR_INST_BRANCH_RET =3D 0x8f, + A11_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x90, + A11_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x93, + A11_PMU_PERFCTR_INST_BRANCH_COND =3D 0x94, + A11_PMU_PERFCTR_INST_INT_LD =3D 0x95, + A11_PMU_PERFCTR_INST_INT_ST =3D 0x96, + A11_PMU_PERFCTR_INST_INT_ALU =3D 0x97, + A11_PMU_PERFCTR_INST_SIMD_LD =3D 0x98, + A11_PMU_PERFCTR_INST_SIMD_ST =3D 0x99, + A11_PMU_PERFCTR_INST_SIMD_ALU =3D 0x9a, + A11_PMU_PERFCTR_INST_LDST =3D 0x9b, + A11_PMU_PERFCTR_INST_BARRIER =3D 0x9c, + A11_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A11_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0xa0, + A11_PMU_PERFCTR_L1D_TLB_MISS =3D 0xa1, + A11_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0xa2, + A11_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0xa3, + A11_PMU_PERFCTR_LD_UNIT_UOP =3D 0xa6, + A11_PMU_PERFCTR_ST_UNIT_UOP =3D 0xa7, + A11_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0xa8, + A11_PMU_PERFCTR_LDST_X64_UOP =3D 0xb1, + A11_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC =3D 0xb3, + A11_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL =3D 0xb4, + A11_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xbf, + A11_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xc0, + A11_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xc1, + A11_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xc4, + A11_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xc5, + A11_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xc6, + A11_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xc8, + A11_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xca, + A11_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xcb, + A11_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xd3, + A11_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xd4, + A11_PMU_PERFCTR_MAP_DISPATCH_BUBBLE =3D 0xd6, + A11_PMU_PERFCTR_L1I_CACHE_MISS_DEMAND =3D 0xdb, + A11_PMU_PERFCTR_FETCH_RESTART =3D 0xde, + A11_PMU_PERFCTR_ST_NT_UOP =3D 0xe5, + A11_PMU_PERFCTR_LD_NT_UOP =3D 0xe6, + A11_PMU_PERFCTR_UNKNOWN_f5 =3D 0xf5, + A11_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A11_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A11_PMU_PERFCTR_UNKNOWN_f8 =3D 0xf8, + A11_PMU_PERFCTR_UNKNOWN_fd =3D 0xfd, + A11_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A11_PMU_CFG_COUNT_USER =3D BIT(8), + A11_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a11_pmu_event_affinity[A11_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A11_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A11_PMU_PERFCTR_RETIRE_UOP] =3D BIT(7), + [A11_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A11_PMU_PERFCTR_INST_ALL] =3D BIT(7) | BIT(1), + [A11_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_INT_ALU] =3D BIT(7), + [A11_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_SIMD_ALU] =3D BIT(7), + [A11_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_INST_BARRIER] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_UNKNOWN_9f] =3D BIT(7), + [A11_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A11_PMU_PERFCTR_UNKNOWN_f5] =3D ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_2_4_6, + [A11_PMU_PERFCTR_UNKNOWN_f8] =3D ONLY_2_TO_7, + [A11_PMU_PERFCTR_UNKNOWN_fd] =3D ONLY_2_4_6, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -1021,6 +1128,12 @@ static int a10_pmu_get_event_idx(struct pmu_hw_event= s *cpuc, return apple_pmu_get_event_idx(cpuc, event, a10_pmu_event_affinity); } =20 +static int a11_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a11_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -1232,6 +1345,28 @@ static int a10_pmu_fusion_init(struct arm_pmu *cpu_p= mu) return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); } =20 +static int a11_pmu_monsoon_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_monsoon_pmu"; + cpu_pmu->get_event_idx =3D a11_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); +} + +static int a11_pmu_mistral_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_mistral_pmu"; + cpu_pmu->get_event_idx =3D a11_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D m1_pmu_reset; + cpu_pmu->start =3D m1_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, M1_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_icestorm_pmu"; @@ -1281,6 +1416,8 @@ static const struct of_device_id m1_pmu_of_device_ids= [] =3D { { .compatible =3D "apple,blizzard-pmu", .data =3D m2_pmu_blizzard_init, }, { .compatible =3D "apple,icestorm-pmu", .data =3D m1_pmu_ice_init, }, { .compatible =3D "apple,firestorm-pmu", .data =3D m1_pmu_fire_init, }, + { .compatible =3D "apple,monsoon-pmu", .data =3D a11_pmu_monsoon_init, }, + { .compatible =3D "apple,mistral-pmu", .data =3D a11_pmu_mistral_init, }, { .compatible =3D "apple,fusion-pmu", .data =3D a10_pmu_fusion_init, }, { .compatible =3D "apple,twister-pmu", .data =3D a9_pmu_twister_init, }, { .compatible =3D "apple,typhoon-pmu", .data =3D a8_pmu_typhoon_init, }, --=20 2.49.0 From nobody Sun Feb 8 04:34:39 2026 Received: from mail-pf1-f177.google.com (mail-pf1-f177.google.com [209.85.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C828B276032; 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[175.159.121.134]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-309ef03bb7fsm9953249a91.9.2025.04.28.20.44.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 20:44:21 -0700 (PDT) From: Nick Chan Date: Tue, 29 Apr 2025 11:42:37 +0800 Subject: [PATCH RESEND v6 13/21] arm64: dts: apple: s5l8960x: Add CPU PMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250429-apple-cpmu-v6-13-ed21815f0c3f@gmail.com> References: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> In-Reply-To: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=914; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=LZ5pN5iqWz3OCuzIiw27nZWBzYhm/oPtBhWwt5qbJRc=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoEErlfTyUVAy1ePsjHsSm1CJiFAxVuwctbhmdB xH4ukXVRrmJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaBBK5QAKCRABygi3psUI JEouEACzAD0sTgca0HLK6vqrrH2FMirQbIejbUzE91zU8/GE8ilbJPoJabc4+Yqgc20c44LHZ0A Ak/TsqoF6C9ppinHmYUuu7YiRF1vsG0DOgF+Ge0crlrxgwNyh5bk9tBPKkSjXMZ5glfwNI2i5tl h2ylYSy9PLj5CrKZJ+QQ1Lw8a+1qokfSHdzYMAxURp4fxyScyjNFCUN/ptIMaSbZAf7D/64EJOy BNH4hiqY4W9d94cr58UUxO7ZPxPQIDfKEJEhpPuHMix3Q+nBcAB5wUZEY1x6BGR1lYyzLrSqCW5 aV75k4SHDC4dfLA/2QH549hkVWy48rSYfcpuVhdsLl3Q7NjJobWlZ/GP7/6lt1e0fZ1elGXxKRj ET+Y6WzpGhTmloIPF/Eci/U77IVneCcuO/DzHCXFtWCjJwBSMvnsV2mbnUNf09Vsg/sVVNxbcsJ 0ngrGAEc0KcbN26+f71/VO6bMG0l96zXAm16BTklsWaFQ7kZ+M7wMg1L+vghuFFRnrFdM5kgOIQ FmsrgdzyVDo4B+buorhmXNlsICqKg5iHCYFhWPvHwXpqoTXVVvJSYa/K0R/y9+4xLXaw25929o2 WvZbnvYdNrSeyq2nXtwnvBzrNP3QpY7YFMZCrtDNf9xAYBheq0y1XIn0UKHKPvR4FGy24DH9KLR i3JkZ6ljQoCI1qg== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add CPU PMU nodes for Apple A7 SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/s5l8960x.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/s5l8960x.dtsi b/arch/arm64/boot/dts/= apple/s5l8960x.dtsi index d820b0e430507f681a5f2aa13a498be98080e1db..62d528d4b7204af28b66a90d68e= 27e1c78e2df26 100644 --- a/arch/arm64/boot/dts/apple/s5l8960x.dtsi +++ b/arch/arm64/boot/dts/apple/s5l8960x.dtsi @@ -138,6 +138,14 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,cyclone-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + ; + interrupt-affinity =3D <&cpu0 &cpu1>; + }; }; =20 #include "s5l8960x-pmgr.dtsi" --=20 2.49.0 From nobody Sun Feb 8 04:34:39 2026 Received: from mail-pg1-f179.google.com (mail-pg1-f179.google.com [209.85.215.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D46502777E1; Tue, 29 Apr 2025 03:44:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745898268; cv=none; b=g5ka6jK0jKsRLjB4/8yAB8hkt4Rv5Wh6wgehB0qv/q1KlHeE/LjVivJn+ik9rm+DGoPiyIoGqS6/cHJLlPVIJJHDKe7pTen1+XcMQEKQohMa1IuB6WNZaErQ7yyfU97112Ypg4EUX58YbXmXn8I25DRcA9n9BXELw6cgzJ8jras= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745898268; c=relaxed/simple; bh=gOE3a46CDNX3yVDAoVpyrWK4j8QsbYn+HXz/rfkRHIk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rTb86xL7pdYAVI+8SL5W05NECfJ65svCackUpwYA/IIrHrlbunjP3dkHU6VtUC3JNeCBvwnN0uJgfY37t8hL4Rcay6/AyEZamAmoIwyvpeKZkZelJT7UmvTJd3eF8rOhmwDOIbJEhdMIioN8kAwLAZLrZVHh2SDw+gOOyhtUmY0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=MESnflvk; arc=none smtp.client-ip=209.85.215.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="MESnflvk" Received: by mail-pg1-f179.google.com with SMTP id 41be03b00d2f7-af50f56b862so3776936a12.1; Mon, 28 Apr 2025 20:44:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1745898265; x=1746503065; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=7bV39ciPbYxAqyF9bw5GexYzHMHyeT7cFiiGjkDg4x0=; b=MESnflvkLptyHWFTBDvlv8Hu4lCk84nS1vLseLeHOd7sJR9QgVRDtxUqbxj4tIFgL6 82f2zSM//pHuhEPIF4XlxwBz5VgbJOkGW7Yw0b7SMz5wRwGU/IlsPU75WuBv65F/FilJ 9gWnJwMcvFH7x8ogBmvOwS8y8et2Ppfhqyjw+/x2E5hSH2/fpnn80ojzOeP8QCziEDeS 2rvoc+OZx/cKBo4D7rizBSy68Gv4HAKuRK3OmTovmyQ25A2CCRbkch4etUSEgqj90ifU xNKVCMKH/5uvCw4fDW5iuA5zzlyGaHWFRu+1RNWD67XyVOZomKc6QVIcPtBc4n92+S31 kXBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745898265; x=1746503065; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7bV39ciPbYxAqyF9bw5GexYzHMHyeT7cFiiGjkDg4x0=; b=GpyRtqgPWXfKQIOiQDaUreUIVX4QdDMs6XQKfGiP6HybbCT8zORp+fTg6R4y7vgDYa 55ckYX0Rod0TeaAS2tkMN66ez30yR2QNUTEY/C17omYHYamhvFynbPosEJDNyOdam2u3 N58+BTEHzEm72SGnBl/TTy8SqpuzirKGfSIBnpTEta8Bk/nVmLmcRBDp1KM4tjeN1YJI 8srZrTIaANNnq2C00fwsbjaDbkCL8t4otbEs0Kut4yPuF3h3GmhbhPtUwcLk01O8XxyZ UpTt53QJxqfMSNqJZs4dIxnuo7G66WCKlVHFTQRNAaE+QCELuVdD9RP9DmfxKtj7vTep OS9w== X-Forwarded-Encrypted: i=1; AJvYcCUxDL4PYWfMKqnUcWM0PxU4ZFiQPpH4B+WfqpJeBxM5wcF9hdc+CyeSLVUjS//+hKUsTLAdv1/wr8uZkNlSg/wZxA==@vger.kernel.org, AJvYcCX5qJQb8Gck2o3Exiv+MDFEz8EFZ9gQM+oA7cMJkNKz27ZPb8kQSiEltK2yILKjdTab61jREi8RSj3g2uKC@vger.kernel.org, AJvYcCXsLLrMgMAdKRIrIHFdhnzLvAZ6an1WgLf1g+y9luXTII/JDYF/5OxgQv75rKQOJnn14tvQ0Vg4tSRl@vger.kernel.org X-Gm-Message-State: AOJu0YzSmjN82ylfWwVBs1ZEslnMdVnWzEKRhcpn++FKmPox0puEuoe1 QqCQZm3+RGCqDw+5kvp7BTh8g4fqe+BYBeoQmBNx6xf+zuiGx2RMLRwNNg== X-Gm-Gg: ASbGncucoXdtOgcqdLhiMitEyh4ofG5PGNnwrHN6SCYcKVMC6CkbUwCBo9PRb3wDjB8 nL9atVS4zcojxYJLzpsRgoZr9zrW7yTsnkXfUoEt8P7gzicsrYPcT/s/0P1fR+oVXKfMK1K3Ghz ogq6ovZDFleaFM5hq4XwMStQwr+c/MjAIkE/rl33+G9KK+rs767eSD4p4stBYSt3+XGA0ZwhHhy SS3k7Zhh+YX9BhlIF+KizqLOndxDawv74g1n7mL53rgVC2KWbwAY5CvLB/7HhdNGDWpzAL6AL6y 0+Cg1xuUN0UqXtnrlwXtLu4FswX+pymZAmOkeL8zCsRLkyycg0mkmuIwt20MM+CKoZsS X-Google-Smtp-Source: AGHT+IFbQ5J8X9Uyjbt/tcsLIdvZTDaLR52CKOBn0GWmEL6qPYTK21ZRYjI9b02uRhJl5cb8jl39eg== X-Received: by 2002:a17:90b:274d:b0:2ff:7ad4:77b1 with SMTP id 98e67ed59e1d1-30a012fd061mr15573483a91.2.1745898265248; Mon, 28 Apr 2025 20:44:25 -0700 (PDT) Received: from [127.0.1.1] (wf121-134.ust.hk. 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Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t7000.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t7000.dtsi b/arch/arm64/boot/dts/app= le/t7000.dtsi index 85a34dc7bc01088167d33d7b7e1cdb78161c46d8..f1415f50cb150ce1d33999c8172= 43c3dc9184199 100644 --- a/arch/arm64/boot/dts/apple/t7000.dtsi +++ b/arch/arm64/boot/dts/apple/t7000.dtsi @@ -193,6 +193,14 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,typhoon-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + ; + interrupt-affinity =3D <&cpu0 &cpu1>; + }; }; =20 #include "t7000-pmgr.dtsi" --=20 2.49.0 From nobody Sun Feb 8 04:34:39 2026 Received: from mail-pj1-f54.google.com (mail-pj1-f54.google.com [209.85.216.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39ADC27817F; Tue, 29 Apr 2025 03:44:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745898270; cv=none; b=sVtYGwLMvrlQ9BObYwsVae3Un0aMICpcYN2P0r0MCMOBNF33ntQW33cFSAe6m+te37XhMtJ4uQyAl6z0ACJkkWYupzGXKAhPYNawE1e/mjgC8MzFRQwh+HEpAGWfheFMJ4BiKZXrin67Wrc7DD8MZcZgMUjRTpjxxWzxNNGfGms= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745898270; c=relaxed/simple; bh=/9xxkCL20iFcrQUCvIdlPD0ncxR9ZewCh+wmud58YcU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=e32fdJvaGP+6Qny0f6/L8YsDz5VGyjNNxOiUEEftbxJvk4i4G8dZ6eA/j5+YjLcPtl0JzagExqItjNtT8rU0vEjp4uw5c/n4TdqsIFIfO1hljmUPMObxERFgNkpiojcSiv0Vrw9+af2wwPPR/UPpM6o42SOoCMyeF3kQMLlK3as= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=D1hVT0BQ; arc=none smtp.client-ip=209.85.216.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="D1hVT0BQ" Received: by mail-pj1-f54.google.com with SMTP id 98e67ed59e1d1-309f3bf23b8so6005659a91.3; Mon, 28 Apr 2025 20:44:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1745898268; x=1746503068; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=t22CBONJmB65GQP7nsD4ofUIJ4+sf0vAxHh7+1UHNU4=; b=D1hVT0BQHmnGUu+inL7IENpm86xa43rkj2JfUjjOyBaJHtYDac4p749hy8UOjDRVmM ZgREGCS1ZKxNiM7wWBMRnIJIBsNZJJLXZ/koomDhc0pYgvmQZybv/s52oGxaJnSspWnY R7gVmH9eHCsaEUGU03Jc4PrJoBF9fNAqhzpSEjM+QFDARKemMhkSnEMRgpiisjBTOC4r 3w34g3I8gErxjZnsZbE3rtIm1gdP3xGUNIV6bGC+fsiEENE7GvgZKSDK2n2sSV958L3a ntgq3Tr7SQPrsC6RT8gVIK773GvgOGH7czLNV0GfmvM+VwBtI7qvpioiAT1p4SYnFWm8 ulHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745898268; x=1746503068; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=t22CBONJmB65GQP7nsD4ofUIJ4+sf0vAxHh7+1UHNU4=; b=LqQROxmpBeVaT/aYYhFzjBdRO3kldrYiM4qaU4s9FiZR2TQRyMzL3RZ4MaFn6mkJS2 WkuoHZ6p8OEVq1DQomhGqB1Z1VQUb9B+pXSVUfkulUijdWCT3r+WgAcwpTanbSNnidtd ZbpREMFJF9SAQW2jibQuX8ZmgCpJx6H12bdxyn9brSKKIhLqlwugNkrEMLVgIyWoPmTi IbKylFHQaP3gSxeeObLtIf/brPiDVO9nGgKNkTBrnDUBMi48Zd9+KGwNniHv+hz8uXEF 1oZ514BAtJ+9wnBocoMuoUBcG8HKCTOb+BEnN9SceAxO+UPReJmGqnNwybyRGUw1j5gB pMWw== X-Forwarded-Encrypted: i=1; AJvYcCU74HwqPD7rKRdqa7wFZwHzTRXiLrb04JK1XtM3881ovDQ7UHP1StenUu8kwq0yKPXdoxKpV5pL7ZPR@vger.kernel.org, AJvYcCURT7dy7kqXpWCh1soU95BhBE/8glFKQ9BzEFFFCQStzbmTYiKp1AbqOcweinPINxJAhN2uMQYxFBNYU0xo@vger.kernel.org, AJvYcCUvteqg66xe1dpYMKnPv28b7SRDibNcie9Wz1k8RrESk257EKAaDHBxwQvpj03YThmSXRL0fRIYDaQ/luwopreGKw==@vger.kernel.org X-Gm-Message-State: AOJu0Ywohc1v6kkfo9PZjuD0HoIAb7eSiRRwEBhxHpBt9cf8kG3CMK/p uTB8EOGv8GYaWTzTWEB37v7IP82CV3acdSBBGUhxjsESPB3u4ycb X-Gm-Gg: ASbGncuVchnM2lweAO0sPMifu5fkuHcyUkZTlCeBlCF7/WM5gB06kkp9Qw7Mox8iSxe 3zoqsNckrOaKZVJwazZNVYXpL+14Aoa+ZkBOU/RNZnaninPMl9droPhs2S8DBhV2eUS7lWBO3hP q383R9PvW+v+miEST0F5c8VlEt+acXs6LTbZOtrLeL1BeQoDekxaf5CmGHL9TXgL3DZb/cFCqbZ 8b/PHp++iHiK/P0ZuBln6f8Hsv+IWOt2zARmC8FmcIlvlzSOhaHFyyMmIkfXSaqN16ysv5D2zf+ g1gcB1SvY9s9DHyr/ODT0bxQs+CVpnGHrp648GAtbeNSb5fZyzJvxypRqA== X-Google-Smtp-Source: AGHT+IEWEAw4OwT6q/IeOWjxagm4FtQQx0OABKyoM16AT5iVGUbP68gxrwVyzhJZKq9oXmYDl3pltA== X-Received: by 2002:a17:90b:37c5:b0:2ee:f687:6acb with SMTP id 98e67ed59e1d1-30a01329347mr16385125a91.13.1745898268547; Mon, 28 Apr 2025 20:44:28 -0700 (PDT) Received: from [127.0.1.1] (wf121-134.ust.hk. [175.159.121.134]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-309ef03bb7fsm9953249a91.9.2025.04.28.20.44.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 20:44:28 -0700 (PDT) From: Nick Chan Date: Tue, 29 Apr 2025 11:42:39 +0800 Subject: [PATCH RESEND v6 15/21] arm64: dts: apple: t7001: Add CPU PMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250429-apple-cpmu-v6-15-ed21815f0c3f@gmail.com> References: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> In-Reply-To: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=946; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=/9xxkCL20iFcrQUCvIdlPD0ncxR9ZewCh+wmud58YcU=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoEErlTlWClVLzzj9JKvXwgD+WaQ6ahUE4T4P/+ RShtTYfN0mJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaBBK5QAKCRABygi3psUI JJG2D/9mYelzQkgmHZJ+Gk9hwJh+/0FCUyI/1EeTu5DrTgqAnxUbT0fLW+7ldfhF33cOLMANMhV YnPNRFc5GiumM1clRZY0p92fIuG7o5b55Dui15dcarrcBZb5NRLiet8WHiKuo2+W4qSldLIjnp1 dla6eCkdJajYiesIZg1MWs1gh9qqXvo1UMbMRtUtfb/mQdrBqap9y9DBKSCsS4qIMlhOO3zIhXM 6yUvEC8TiY1NN1m2FVH8DgSsObS5a+pGm+vbmVrIeXDlD48fmln60yS9NbD4CSCf4fF/Kh3MXjU CigdKHVnufn5Wp8QS71MWLWDyB8I+xhwWYFi6lDvkpi+q/eLEKq0WaZ+8+hrKd3py5v5dE3Tobv U+lH141KU6QlRdwUIHxERkksiG9XtoRk2QM/xA5ZOSzBSMc0l1tslqH5Ew8LJsJbjaAVUzcx660 Rpbg+7i/TBidpdCTv0jYsMyIUNvVz2YQeDEbp+rEdg5Dt5CsRaxl1VdA9qYKIaFq7pHff6GSyn/ UW17ny0wsRg2S/FvSheuQW1XYQjLZvHmpLlGchM6GnNAs3z8oXeuYAK6y4jOldrwy+Set48FEt3 gR8h85WlInSig38WV67JiaruYXYdHpxkK/0tnoggnqSi5IqExrL23Hx1A0GGUb6uuZ5JWlNzuMc ZiHX35qQt2rAeFg== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add CPU PMU nodes for Apple A8X SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t7001.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t7001.dtsi b/arch/arm64/boot/dts/app= le/t7001.dtsi index 8e2c67e19c4167fc6639458ce79588e153336603..fca0a100dfd7b29086735d36fec= 0db51144da456 100644 --- a/arch/arm64/boot/dts/apple/t7001.dtsi +++ b/arch/arm64/boot/dts/apple/t7001.dtsi @@ -183,6 +183,15 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,typhoon-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + ; + interrupt-affinity =3D <&cpu0 &cpu1 &cpu2>; + }; }; =20 #include "t7001-pmgr.dtsi" --=20 2.49.0 From nobody Sun Feb 8 04:34:39 2026 Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CA2E270550; Tue, 29 Apr 2025 03:44:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745898274; cv=none; b=XrXvDXj8t714pu606Gr+2fkCr7OTgQqs7sn7Q5qCKVZIU+H2yIqs1EHd4lvOcXbzmRrszRw0gbfQWqcMfao283vfzWn48WbhTnN1xYXPuUIud6R1eFEOSLHx2WigJ0651TSOaLIpbUaPJtFHm+P0X7YvB//+mQgBGsorvGaK4zM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745898274; c=relaxed/simple; bh=duxT7MNXJw4vPLeIH5239k3CmgZWAQGQK2kW07pl76w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CRHg381HfQEtCG7OHfRnfcSAlOJ7GThDCYCy2qbSb1fkE4WhA0IeXz/bjiPhwTE+IUUz+NdeTwNr6sPPWVCpeqISl8lXbvEp7/bS2oOXMwldSb5GnFf867o2m5Fc+IUcFRCRMnm3OE15d9Qf32te6SxWE2lp4BKvKEia6O5QYZw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=anR/F7ly; arc=none smtp.client-ip=209.85.214.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="anR/F7ly" Received: by mail-pl1-f181.google.com with SMTP id d9443c01a7336-2240b4de12bso82445875ad.2; Mon, 28 Apr 2025 20:44:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1745898272; x=1746503072; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=0QbHFcfneBNmb+XSCJr8gKBnaCoOSbgUaXguXGZhZ7I=; b=anR/F7lynR7JHGT5UTDSAWPRm/CsWUeBzXIAmjw8xVQxecgbXxsHfcLQXoYEtIwmuh HSfEh0cfRII01N0mMTb8+Ljm2lMiMh5uPkatI3P1NFcFlw2lpjVvcdwvnkREfQGVepJ2 /TONZ55cyLfEZ/0G+Dm/VE2yDxaX3j8sA+zZkzb4IGxxmBvfzk0Ph7XW1ouTdMdQc5Aa 7wmO1scOsicrQJMzfPGJ1muTsehSzm92ua9RRIpjUEGVs0EKk+bwYNzUbls7L3fo/hnG TsCvLF5vGeMVT6k4MkA1StV2FUXtbR7peU5DSBwXa2FFSc4nuUJCFONoRZlSzH8PT4s4 nJ8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745898272; x=1746503072; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0QbHFcfneBNmb+XSCJr8gKBnaCoOSbgUaXguXGZhZ7I=; b=BLS22Ev8YPBYh0lXRig4UPRmKhkgwgAmwUyD3hy3YIq9V04nHaQsQwcvISQoSo4eLl IKe0v4fRAsunShwnLwHG8SQYPbf2ErGdCCYm3/ucqqLiviYSzhP6G5Bc5yqk19kHr14M aZKn41s7urJP2PaiSElQWi/VuLsJGDjPpbfgoORwk83LC6qJc186a91Kk9oIXDEyNvW3 CfR/cX+VvwHRXZm0ZhtdeoHLBLGIZWIsVxtLtP2P/o3Nk6VzoBXL0p+yne6pTfKsbgvp 6p/0IlY2mHdxPC4OEP02i2dkTGbRrJsAzKnjz17huo16vQe/5hSmbLkPSoa30i9iXdEK +o3Q== X-Forwarded-Encrypted: i=1; AJvYcCU+a5ZlI6LOnNB6aWgYkkU9vsD923QjHkTy0NlY0+8KKvCRvWeUN5+KE337vq7pJxlPxSiw0bNGj2lws51IH1gpqw==@vger.kernel.org, AJvYcCURcoofYgvmD1GM4iLwlot3z2swU+8ElsAbWYWDSz4ORpJzy3VGOQ50y/VIjfkOo8n6LsGIlSEumrPc@vger.kernel.org, AJvYcCXjoi58JisPmlqVNIFn5/j270HcL/C9Cb3NOs3jzxB0FurHFdBe4UB3Xaws44dmCFQwDfIrK48/MiK2SXAP@vger.kernel.org X-Gm-Message-State: AOJu0YzyXCW3m5paUdHCzbKU1wX8jiRVJvlnOFFHr4zXlMUOxXs3ebzo wur0Cw3zbQJfl1/zhOAbCoOe3Udxl9Y/DFyAavSaEFXUpT5VoI+T X-Gm-Gg: ASbGncuNDkFGVLT6txsugpTVUoBlNdCiOiPMLnoPwX5pf9JydZJuAGjwOttk1o0Xr+y PNADbeI/Ma6CKC4e/7VyQTFuB6FvottWi85XVVMUdQn1+zM8bJD2NIStrOayLJ56WJg8p2Eu/VO ue25W5Ygr8bP6YtD752SWp+GapWA5Lg/YSRhw6gbj0bfASni6Qp+HsqCX2YhpOCveJxbvKOuMcr 4ivcfOA6wCHz+PwXGCvP0wbPvu3UIjKUqiRDI8xSrY7OdNQFxS65rEfHohJhX3Scdv56eh7oAiI 64kcsaqdH6pqpedfiMJt8mlKgNERhdeT984Vx6lQRVakRnk/wtYzS9D5gw== X-Google-Smtp-Source: AGHT+IGccqGZ3Xia9Ch8eVE4eB5PhOyKHbvEUCPfUez9ylO+fo9l2C2+BFOaam1hQjLiZd/TEJp4xw== X-Received: by 2002:a17:902:ec8e:b0:224:1001:677c with SMTP id d9443c01a7336-22dc69f8997mr153751925ad.9.1745898271905; Mon, 28 Apr 2025 20:44:31 -0700 (PDT) Received: from [127.0.1.1] (wf121-134.ust.hk. [175.159.121.134]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-309ef03bb7fsm9953249a91.9.2025.04.28.20.44.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 20:44:31 -0700 (PDT) From: Nick Chan Date: Tue, 29 Apr 2025 11:42:40 +0800 Subject: [PATCH RESEND v6 16/21] arm64: dts: apple: s800-0-3: Add CPU PMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250429-apple-cpmu-v6-16-ed21815f0c3f@gmail.com> References: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> In-Reply-To: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=912; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=duxT7MNXJw4vPLeIH5239k3CmgZWAQGQK2kW07pl76w=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoEErl5A1ECOtTNng0tLnKXDnvyb07KxJIcMC+5 SNjbIZmLoGJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaBBK5QAKCRABygi3psUI JHMXD/wJ6027IA1eE+iO9JomMzvUWoHwbUr0+PEnx4lRmEjmaW1Cy/p3GmMkYOUOt3Gcwwu644A iNFNEx5jt1OcJmtvU2r6dYE1oLH6JNXzNhVYQ/SJ1KMOakb9dQVKLWxIr/Syd1CuC73eekq6BRp VpfU5lr5PHujOxFpXOWHzW8jFShJ47f8Kg9ciBdXAJpI9wSpPDYHkpJwLn8W3TxL91+PKm0x+8p vx2C9ZstLrvj6vVpCvxgyCmReBs8Ka6OPrdjSWGiUqb9PJUUWcBKImifiIHMeCqJ3tOIj86nIna z26bosC1lp3M1qNqPWMlalzRh3AmVmukfJc0q9DEo5jClErJtsgAgqDn8oEB66/bFGh3XZLf13W XaI45hBeIziEk0fxxNCJ1zbNekMrbaM/FLxZx3IxEg1W1MKq26Ff6CwQZ5DXxz3Bghj4x+eCeaZ RYTzDjq2Xg4jJ1bTDu1gy4dBfBENStVrKQ9vkA3S3QxhcE3hg07lIz6l7HYyLweU0586d6h9btO kRNHxM+bxtOB6uDX6fUEppO2faEgybt87tVfjbOVB1Ioou5Ai707ssBB9+VFQLWFDI1sXzT3GUh 487zF6FZlcwJPioCb+vP/Ahj9r3VnIewLB0VEgRzvIBrUeDyJKQum4/tIiML9A46Fo2rUEiKzxu g1NClcHh8mdaObw== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add CPU PMU nodes for Apple A9 SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/s800-0-3.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/s800-0-3.dtsi b/arch/arm64/boot/dts/= apple/s800-0-3.dtsi index c0e9ae45627c8150bc0ddcdc1e6ab65d52fa7219..56ac6e7f3803a16beacc7476426= 2b02c75a96fce 100644 --- a/arch/arm64/boot/dts/apple/s800-0-3.dtsi +++ b/arch/arm64/boot/dts/apple/s800-0-3.dtsi @@ -167,6 +167,14 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,twister-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + ; + interrupt-affinity =3D <&cpu0 &cpu1>; + }; }; =20 #include "s800-0-3-pmgr.dtsi" --=20 2.49.0 From nobody Sun Feb 8 04:34:39 2026 Received: from mail-pg1-f170.google.com (mail-pg1-f170.google.com [209.85.215.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB8C029CB4A; Tue, 29 Apr 2025 03:44:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745898277; cv=none; b=pTHpHNBQ4cwS9AD29hdvwkK+a+StOBzko4t8T9LpD9jZYF0gR37LAd6BBVYi3r9Ya/hYx2GUebX3b4Z0A/Ji5LHvSBgE8H437e19zx65Jde33XqhBJUsnW/X8+X9RFw+3b0J5iIVEshKjcqUiIi50/brhmaE8lFhZOkjKx0md9c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745898277; c=relaxed/simple; bh=umS18Mpui1EoUACcGD+WdVdka5VgnqwULsO8fA+OvnQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=f5utI9ubCVAHVTtPFIfNKG+bUIcc1TWL8rHabv6zqrEVjh+mXiwkBbQ8gFIOreZAGkfZOVl3h6QqWpsuYCf289IkasUn66WoIdhD9idjqkbTOLHlxLnPuonAGICRs6TH4fHOBbFBe13agTmMc80F0zP/V0i9UdlfU9dS90oJVgQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=BnjeSOXe; arc=none smtp.client-ip=209.85.215.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="BnjeSOXe" Received: by mail-pg1-f170.google.com with SMTP id 41be03b00d2f7-b0b2ce7cc81so5486624a12.3; Mon, 28 Apr 2025 20:44:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1745898275; x=1746503075; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+utL2luHU/M8t1jzjSvkLs9Wawp5wUxO2TP0BW4NMfc=; b=BnjeSOXe+jwKUMGu9VeL9rAxdRdkha9WvUCcIi8FCXN9JKQ4oxJTNDvSwnQROzJsyf h/Ty39VDYHe1dXfYdlCd9KDlt1m68TobDBkjZiyax+wpn2h+H/nPxMO3BTR+FaTYg7Xw 2XutVMRC6mBmyF0IxfkkjTlU/WS0tBoQ45hLiSf7Zb2/crTNgaFje6rg0m29/VAzKoeV fdM/l9nL7MmznJ8Y1PIDTdw/VRysu6LDC37ddowdSIXRHJRuPUw7dWmJlzrxgVRWm+TZ N0tHJ0cmkUSinSu0cJ9MYi/BxBymTNGYFygeprTO62RUAZYpVsOXUdALopEi3n5dxJEA dvlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745898275; x=1746503075; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+utL2luHU/M8t1jzjSvkLs9Wawp5wUxO2TP0BW4NMfc=; b=ZEnGI67eDxfIBUVeBVr/tgHOlOzvBIaJGql3T7dni68C9xx32Et/rmhV7jgrgX3QU9 nBDC1K6wxdfn+XNnilRuWggn65uC5x1nJNS228O3/iY5C8WkmnDwNyn22Ic6BIFfYOLw QeVGdyFl/RFBHGSA/9wUBUm2tn7K9XosfO58xev7hmZsc1QwDNdnYzMRJJLsScQ0aSwb Ivy8guxn9+k19KOBhJ7wqow2lxrYBq3QV+wkGaQNi6hZLxZy1W8uOCI5IUMHzk0Xt3Qq uaC5jtBod1b7CTkIphCu4z+P2bvNqU0nNdp50LDKYgqQx9kCsT6qpz1sap+hOcdAvWX3 Pk4A== X-Forwarded-Encrypted: i=1; AJvYcCVm1WHqW/UFsv9vOQvWTGse0cXX/IiJ4FjmjSrA87yfP3LA+HsAXvym5sJ65oFtUCpE8/yeMR0SD7N0d6447Yof/g==@vger.kernel.org, AJvYcCVpJaXs0+biMXFvPTkfTf16AVgc8fcAdX0S7xhQZDd1/lHmdjQBSUAVLdjg4G6QiU1+RmaaDqARPDh+7N5K@vger.kernel.org, AJvYcCXtOGFdZutUdP5aOIcGrJMVxi3FpyQdHkStRHboRgBQDUtC+Uf3tNriAVhLoHtk46aqp3u4oliVIofb@vger.kernel.org X-Gm-Message-State: AOJu0YzfcK7o7t55EtOmcmpfkSWfcrAz32fwywHGer7TRDQR8RVEfSCL z6IkDMjGxZ0wod0jAIHgoNolHC80IfaCoIvjl4nVh3HMKscUzCC6 X-Gm-Gg: ASbGncuqroNgFYxbeRkdWORnWtcqjkd5BR67uXAHR2uzF+XadaJKMo1zewZt2q48Epy HYbl2kQ+W5kAReX5PLPlLvtxy6/LLqVH66NDOISmtffWS6jsYujbqnnp9QbMYTqkHdrFq3H7s8q IRszOY1tJZ1UXuP/IYn7e+va3b4zlggPd1PgAMKRk8jvUviwZwRQOdnWUsPke5O1wOYxKY/R5nZ Cb118/2bhYDbohfxN75iPkRCiYS9lVQLJCYcIyFysn7Zfxosk5lJXlUyCdMyDjLQOMyDKHS4TJs FTkFt7JVk38olgnD6rc48oeidTQKplqM+Y+bqHW+4cBZEZ/sUP6sKgYH7A== X-Google-Smtp-Source: AGHT+IHWfMjbVQ7CEMWplQp6hbDhEW0CnashZJmxKBOUPepAX15akTtG/oxgIuKanhYarcPeCqHQeQ== X-Received: by 2002:a17:90b:4c09:b0:2ef:2f49:7d7f with SMTP id 98e67ed59e1d1-30a2155ece6mr3699740a91.18.1745898275246; Mon, 28 Apr 2025 20:44:35 -0700 (PDT) Received: from [127.0.1.1] (wf121-134.ust.hk. [175.159.121.134]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-309ef03bb7fsm9953249a91.9.2025.04.28.20.44.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 20:44:34 -0700 (PDT) From: Nick Chan Date: Tue, 29 Apr 2025 11:42:41 +0800 Subject: [PATCH RESEND v6 17/21] arm64: dts: apple: s8001: Add CPU PMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250429-apple-cpmu-v6-17-ed21815f0c3f@gmail.com> References: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> In-Reply-To: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=895; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=umS18Mpui1EoUACcGD+WdVdka5VgnqwULsO8fA+OvnQ=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoEErl/IRyZyitmYveeenL0GQFh0I4cCrA6w6+0 9uwRuLZGQaJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaBBK5QAKCRABygi3psUI JKOPD/94+SO3FKA31NGVpaytKTjTzwMf8DGMAGqxJ3qNQv1fbU25mGiif6KB8zFmOIFvLYaKWGL 3lHVdyBFk3VRfYjagBokp7A32epeJOpRr3bJVzBAtyIVZqgpLmfpMToHKoHGY++WMKTkqCexJcY 1AIvtoXobSR0z7CFGe0K0VgakVOwp4KwFMJPtA3m6hveWhGKvUvslHaVSNUZfI8BvmyPZFRGF2B fkmqjzN8cyKVkPUbTvKRd7j6hIRFFUtzQ0F2bOvPjMh3k1hguUCEIraz0IrrJY89cYgQI6XzstX crkcRrNhOfbzhUx7Bf+JAI4RKtY1+2W6CSEXXwqfEr8gm+WxvaeeqyUHxORn7aXXXcjmZSW8esG FxKwhUjw33IrQrZtNqUD96Fh5DL4852ZvjvFJs25Ro5myt7hQOroQfZuIdpZ2chsNQ8pBwdwj5H b6eOaanSwrQX3ueBcLwJlIlfjw6zpHm5uxhCWQ1+qgKlTjF3GW9uX6zL6GjR8uWV13ApHCpN+Zm Pqf9CZC7srE0xwu7pfhnT9kbhIvEBjnD8rd3elEJ1HUD87JRVph6NcubeYCNYbPvF5XXl7utSGJ DICB8VUoC1e5100qCY2XDRjVWVrIOVJiLT8hLwRbmEzMLRjC5yX410cSKjuiRClh7xqZq1yZE3L +EU36l+T7kjRA4Q== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add CPU PMU nodes for Apple A9X SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/s8001.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/s8001.dtsi b/arch/arm64/boot/dts/app= le/s8001.dtsi index d56d49c048bbf55e5f2edf40f6fd1fcff6342a9f..33760c60a9189df5491256f81db= 7f413cada27a7 100644 --- a/arch/arm64/boot/dts/apple/s8001.dtsi +++ b/arch/arm64/boot/dts/apple/s8001.dtsi @@ -209,6 +209,14 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,twister-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + ; + interrupt-affinity =3D <&cpu0 &cpu1>; + }; }; =20 #include "s8001-pmgr.dtsi" --=20 2.49.0 From nobody Sun Feb 8 04:34:39 2026 Received: from mail-pj1-f45.google.com (mail-pj1-f45.google.com [209.85.216.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5802629DB82; Tue, 29 Apr 2025 03:44:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745898280; cv=none; b=svB1PUBma7rhSUlsuFkCSl1k09jC0KBNIe8woIOvJsBOrUsCrRLuyGHF4wWZYtL1LYF4WPRtZ8T4TVUxEf1Xs4+vpMEX95JwE+ttlTp0gpGQCy6jsZ5EzaXqjl1c6Irr7mHRDgXi1cBlXJLz9WlQXV3D9VNPr3WocssKjQ62tpM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745898280; c=relaxed/simple; bh=kZviMfYtRCR7gR5VoFkDRwcKeTgAqfWp35C3egDQLf8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rfyG9rRh3YqDIphnubTy4A8mzh0+cJAZKEczd4Dwm+8Dcsi/L0CwMNroyoydRoQFU0hR9CiFXo5nu0R84nMZ1w4bG6t/taet4nnmYdNfMz01misUNm2YbBPRyTnUIhVd2GACJ2DNUEJE4/pOEV+QAy/Xa755aykvn8ZUhuY9L4k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=csu2SAn0; arc=none smtp.client-ip=209.85.216.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="csu2SAn0" Received: by mail-pj1-f45.google.com with SMTP id 98e67ed59e1d1-301c4850194so4517168a91.2; Mon, 28 Apr 2025 20:44:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1745898278; x=1746503078; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=65yvptSdo6oSSwoGRF8EUfcgAwuQwDq5kFTQAdR/3Jo=; b=csu2SAn00P98l+MPhXlhdcTGNxyLaquyWRjYMyqK7PLHzufHf/6ngxpWWoOAHtc7yz ToZcpl1yjtbK2ea+gcr1ICxoC9vqVnQcYzuvFDajCdn7VjpIYI3m+5sh0M8T0HkwdBCa hiaMydZgI6LosMDjS+UQgBkKSTIbn+PHCT5ZwEIkTf0qataU2vFAEjAA08LYk3SM0Jle UcLPAIFMTSwl5kbsyiYpHZYD9jcogWKE9ff38HbJFTh0Q3u/RaDXZaNJMTeCZ4v5RUp9 RDnefoA38IGx86MRXAhiemA3yRIB8JtzO9vD1LJOgEWx5qt4O41yKmAYJ6QcCUJ4aie3 JRyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745898278; x=1746503078; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=65yvptSdo6oSSwoGRF8EUfcgAwuQwDq5kFTQAdR/3Jo=; b=mKeBzuYuhZeTnZMWQDjIdc4sW7FTJEcIq7RwGrJWbUY3vCiUf09CMy9QA+ZAa2nqLB bW1k4ZDf/SG7z9hVx1m6wmDk/SJuAo71eEV0r9Jhcp3qRgvgWjh9uAjyXolUDYFV8KxO AWK+DWbEqEmYcjcWNH+SGzC/EQco25TGMT32Lj3EBxTq19nIQvRZ5BptJ7IN8Kl6XrAD tBwi9bUJN1WltIBDi2yhwuU4t/tk/xMm/hbDeCZJhoAUGONPi2f5cEAHQU609qRE1qxU DipA1YIvGQm9rgZzwdawIStpTQzmQTY9dcD1Eet4PDleN2De4uEBfk+6+TzFKqp53k0i B6yQ== X-Forwarded-Encrypted: i=1; AJvYcCWCsNquGF29wmR7d9jOV57xflNlKioXy0POI2DenHGHITkv/s/3Fw3nl2rZQtzqY8toHCkwIyhkqc2x5VZXW+FCtw==@vger.kernel.org, AJvYcCWPtUcyRpetoD/ROtBNUlZA4EWIkTd/d4L/Yhy2VHOI89JfQY5u2imtYhaa0UVEHE08gzust1lYtiaT@vger.kernel.org, AJvYcCXZ0Gf9042uQcg/wzAoB5Mk9JPeCafl8EkSTO9kzozZck/DYCpKIZl+oK06rFNHQ9NVpO6ND7GewXom6GRI@vger.kernel.org X-Gm-Message-State: AOJu0Yzjj7DIqwRJGeoz2+Wm/HwUdIDXK+Pv+Q0AApVKvBlyog15Zxsb n+61eNfAaoAMA2I3IyKxQEvseOGZq72OR5GL9V6vN0F4kjg3HnnK X-Gm-Gg: ASbGncvWP4VhUFG9EKxZgPrOsXcaUjITnhpxzCvUHzzTRgS8wvtS0Iv9tWbAhURtvuQ Yp4W4sPl5u5mXg1ItknoWu81fG30CuJXT4lPn362bquBgvsYM8vNJBn9ak9HNGEQq6xJMgbK1hN Hl2dAQ/8GPyD4o8UhvMOfwTivraDsGPOBIXwdEgfbB0f5Di2xLBr0BkwpCWZv/UEe+wDqzGL2Ix PXGt1iZjy4oORkGY49y88Luq42HiSlCGpdyL/Vn1vHyczb3effw3UvHy99si1AUvwJFdPFaZUgK D/iA5BLuaBdkc4hyflwkAi9e0LS/wWMAIjQgWB75e6TBbwSuOuhrJ3qpxQ== X-Google-Smtp-Source: AGHT+IHxm8rT1uzIKYd3ADrbL4R5NMyjZOGRKMbNAB1/GXp9S82eG0nLY3UcJaZeQW35JAd4gGlOqA== X-Received: by 2002:a17:90b:554d:b0:2f4:4500:bb4d with SMTP id 98e67ed59e1d1-30a0132ba1emr16578615a91.20.1745898278562; Mon, 28 Apr 2025 20:44:38 -0700 (PDT) Received: from [127.0.1.1] (wf121-134.ust.hk. [175.159.121.134]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-309ef03bb7fsm9953249a91.9.2025.04.28.20.44.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 20:44:38 -0700 (PDT) From: Nick Chan Date: Tue, 29 Apr 2025 11:42:42 +0800 Subject: [PATCH RESEND v6 18/21] arm64: dts: apple: t8010: Add CPU PMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250429-apple-cpmu-v6-18-ed21815f0c3f@gmail.com> References: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> In-Reply-To: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=894; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=kZviMfYtRCR7gR5VoFkDRwcKeTgAqfWp35C3egDQLf8=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoEErlqBnZpfNvEc5aUCBu7KHe5SloQqmhqGvfE tbd8L938H6JAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaBBK5QAKCRABygi3psUI JN9jD/wIdllTQLa6ubvW3FYhSvEAW8tilwFBI+z1bwHry9E42ry4qJ46YOeEx/l5swDjNm/hIQD 0U9VCXRHRMVc/7OUpM2QjGef7+PJJfW8AH/tIk1UVsXshS2w4bjhX0nCsHFuGCcABnnPmpSnyhB 8Pt8e9wtlMBm067X899femotFvjQAXUdywixEZYnSPfwUDZXRmayFOcsXyRsAuXhoY9SAv37x/a M8fh39JtKEG9kJ+sUjbCMClMGpnbVpd0fs5wRuNahh50wGIxacXpfLnwchguFO1cwTOyq/3Rnnb avfDG1XNveZOTty65LDO3+bdErUSJhR10if94vy2kOxhMMHYApBl0Snl1IBXFZKiBKzjrLcmyc2 6ShcYQl6V8l/JLa6flHDYJKnosKVRTg8blKDjcInVRpKc+4DO7M9t6IZUaFSLIEI1MJWvdtEQAA TkmzFUN5oy/wtfZgY6fGqLg3NJ1QkhY92DYahM3Pcc+EagP0kklU8jQL9SNBspIfjWiPKwhb+xM bLAL8h/zgJZp8F5tC2DuHY2Zsy1bPsMR61wwsfBqIQMRomNKL2uc6EXCje7pCbcG0NFHzjA/XGE PlRM+kh+WShS9fcLMugbZQX9WOFN2mHNWRc+O3R/XfeHDsseT8U9PneTBJTTdJaax9yJ5PuG8Yx mxmYwJEk3r8LfjQ== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add CPU PMU nodes for Apple A10 SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t8010.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8010.dtsi b/arch/arm64/boot/dts/app= le/t8010.dtsi index 17e294bd7c44c7961cc3ba0ec5f4178840d5b9c6..cbffc84480379cb476d5caaecce= 91f746e862354 100644 --- a/arch/arm64/boot/dts/apple/t8010.dtsi +++ b/arch/arm64/boot/dts/apple/t8010.dtsi @@ -243,6 +243,14 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,fusion-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + ; + interrupt-affinity =3D <&cpu0 &cpu1>; + }; }; =20 #include "t8010-pmgr.dtsi" --=20 2.49.0 From nobody Sun Feb 8 04:34:39 2026 Received: from mail-pg1-f173.google.com (mail-pg1-f173.google.com [209.85.215.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0E2229E040; Tue, 29 Apr 2025 03:44:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745898284; cv=none; b=XTFcPOquGvm3zH0tMnKh8r6qNHKe1lXrDG7jTjyydrlAEgwSaa3duYCZiJrcdvfLaapZtDvxRCdZTR1bEii6Ilbh04Doz1qOWYXscymaZdsnIQfg8oGNeJA249ebmxsY41eJYgbk0DOYRTD1Um7Hw7vzuvPIEL+nY1Btv4NHEr8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745898284; c=relaxed/simple; bh=ZNIQgw4HnW0u/JgkpB+HMZ3DOfGGfZVMtPocokF3spo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Hys/rheVmz+hXMS5qoH2VrB87JNOGQunY6qzg/qUpBtasPGw5hmhD8g99bg6tAJqIo5noIqlvqIo2JC6eW0rCJ/dFPKYqjEXu5MT+CNXsS+Cgn9ZBnoRV9a/283T6xbhWkwFZARQ7+I9rKp8e3HpSFNsKQXo98RcfS94azy3U/M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ZjSpQg8t; arc=none smtp.client-ip=209.85.215.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ZjSpQg8t" Received: by mail-pg1-f173.google.com with SMTP id 41be03b00d2f7-b12b984e791so5332666a12.2; Mon, 28 Apr 2025 20:44:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1745898282; x=1746503082; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=DCporfr4EIL+gH/R4FLi79/b+qKEezH7ywKQB3RTf4A=; b=ZjSpQg8t9biSjlWZ5dQMwT3x/63QpN3z90wNy+GGaIPFoKDKRRPLj+rTwG90Fj1w8u fBIguwRLXc2nSZUN3YaY3RAp/VmBs+We4PAEN6Fc2V6f+M87YEdp012YLT8GSXXmBkYi FdvtjkWqw/pLvNaOOY0YG7TUNO0wASfn/MnxRaQRxXue1ROMVmmqQn89ThjswKQh4nFl zkOO/BpVE4BMFrahvQdxpYRzO2Uj2JdVMVahf/NuwQdtnhoeHb/SXlsDy5S9rriSEUFP jy7cX6szNmKP6QqKQDDwdEYuUMAdTHsgX+6+MmfXBbIgqGhfVZfd2Yi9XWP8SumEFtBz s2Yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745898282; x=1746503082; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DCporfr4EIL+gH/R4FLi79/b+qKEezH7ywKQB3RTf4A=; b=NY18cemtROnKmHjthTflyGjrmdxtXVEtOx/18ZkbSylkStUeU31Ll83Lu2T6sE8WY3 advSdyterPO3RR7RFyzCosFaLC5Ug7mEqSrCo/QgtNzX5P6KrU1t3rhnpqS/zeQq/MLs QW0tR7PKgp+oxVcEiLNoecFU8P5VjzTbpYRn33jj4/e40h6IMcvEiQuNb1BdepdVZ7cv WzwdW2IeZ8BrzSmkKlIiM3VKTy6/fRF1vZ2ayA7VChLncILmJC4bKNtssMLNyTWgn04S ClR6wFZVYAEfEksD+YHh5rEAe96gEU6mzku9e7VUuHFfvMV1bUkK/qERJJq7tsBUO83G tG9w== X-Forwarded-Encrypted: i=1; AJvYcCVJi2nLK1tuXPpGvndrZY424O0hU8TiYzToZqBTLZCco0VZXhp9sTNdY/TT6++4WBKJAkzo3Xz+4hhXp1TvUWX6OA==@vger.kernel.org, AJvYcCVyd/ESelm/5NZSC1mNjbMnCDlGnXtgoOz7tKhbwpRtBvpE+SiZ8wiVRtgrCnLTR0aRKWfyFyRnC+Nb@vger.kernel.org, AJvYcCWVIWXKGQkWyLhnmaLiot5qytTPg/hRpEP7FXmSaMd7gfjQI/6E261DmrQSo4mlJ8245qgWnaZDhbo7FPa+@vger.kernel.org X-Gm-Message-State: AOJu0Yyf9Hjw1TU58DD5jAQaXOR8C6dFMR4brGKBu4MYHp2Dbdckwq9v O6qp3gYhVyX67/oBpAW3AJZ8VlZnsgNokFtQ4YifJGlXU71Hao1f X-Gm-Gg: ASbGnct1LHEBQoq8uCHWulA/Bg+BFG1QTN4a8XiVHNg0ewCBp69e3jqh+rPyUNkwM7N US8hQQiEFo3KVk+kJYaKf2hyyxP3BRbExDGE4m10D+izwoukE0i+3N2yjVG9O89YQBKhoSDbJMp 1/KRNYhYioAgo+s9/JVPl9cZThNkvz41ACFHhPryU9sJyCAvipK6/jruxTtIJ9cQnCBj03Ww3tk 4XFilWDZWw7Oe58xDkGPFrC4E45vFeO/Sc8ebGhcKM6cdUKGYtjJ7XqblVwN1/IV+qqXOJNGHwb GUjKnxCXF/5GNQBLUtR39Z6uplB7eVJjq3MIOzajL/1PUuoe0J2jmbpfWg== X-Google-Smtp-Source: AGHT+IFzFXVneivf9OPokQY3zw9bSNPj8zkSDTlCOwbCoaI+2d7wrwaio94T7tzORQTF6aRrfbAhmg== X-Received: by 2002:a17:90b:4984:b0:2f2:a664:df1a with SMTP id 98e67ed59e1d1-30a21546c8amr3148992a91.2.1745898281922; Mon, 28 Apr 2025 20:44:41 -0700 (PDT) Received: from [127.0.1.1] (wf121-134.ust.hk. [175.159.121.134]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-309ef03bb7fsm9953249a91.9.2025.04.28.20.44.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 20:44:41 -0700 (PDT) From: Nick Chan Date: Tue, 29 Apr 2025 11:42:43 +0800 Subject: [PATCH RESEND v6 19/21] arm64: dts: apple: t8011: Add CPU PMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250429-apple-cpmu-v6-19-ed21815f0c3f@gmail.com> References: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> In-Reply-To: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=946; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=ZNIQgw4HnW0u/JgkpB+HMZ3DOfGGfZVMtPocokF3spo=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoEErmhAaAeRuhpFbi6gLnsvgpq48CyERFohMo0 o05klQB3lKJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaBBK5gAKCRABygi3psUI JJ2oD/9vTAubABP6miBhIXITGpYPldj+/FlKBXzefi6FCtClttM1Vh58xbYEO36GkrWeGDOZ7jZ VhKAap3FjIz6Umg6gO3TTPtaEgE8lxoACUUkB7d8EjXlm4BGIhELKMdlVu9hNqNREMpA0X5HoY4 5IijZygjLtt1g6wP8oa08TSi7CApM9FILAkaYRuKNzXh/1BfWsslseDmpJ7VINmMzmmZEUtS6sC fVZiehj8FMwcwjFLNdf6/NlPaOmes9aIl5quoIC2XH30LBCY4L0Nt95xXyDMldkLtkCI51Zdpgs 9fyzSeVjf0YH42rkH0G5tdytxLMUuyNigaoJLaVD/nQWswN7QJGhZBWcpOt6XC9xglliCFjvZAS mF3lU+nMuhA/u3qscGRrck8aTS46io12eWrAmhUEHp3hQC3jn/9S1Nu1Ww4ivON7v/EhxLxSaie 12QNz5nlzAYQQcCOz4blxc2AuNxVJjYi0W1JvIHfNuOwPR5Jhy1bEcF+kbBLvqp7q7B7Ux3cS85 gaCa62HWVailnmqVgkzLbav/DevA8Swc6kQ1k2gq2vqhsiorBqsOTWIyl93SHM2Ub/usGbdQCn9 8e5HIvILx1jjsNBP2LRBxpgORNuFYqgu7hrHnh/qA0/muSE/IHnIHY+io2RhQBnLuQc4V31Hzsn cKZ6gFO450NZrxg== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add CPU PMU nodse for Apple A10X SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t8011.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8011.dtsi b/arch/arm64/boot/dts/app= le/t8011.dtsi index 5b280c896b760dc8b759bf38dae79060e34dfc19..7fb3ab738f67583d9a19a542bf3= 6ab2806268d55 100644 --- a/arch/arm64/boot/dts/apple/t8011.dtsi +++ b/arch/arm64/boot/dts/apple/t8011.dtsi @@ -237,6 +237,15 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,fusion-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + , + ; + interrupt-affinity =3D <&cpu0 &cpu1 &cpu2>; + }; }; =20 #include "t8011-pmgr.dtsi" --=20 2.49.0 From nobody Sun Feb 8 04:34:39 2026 Received: from mail-pg1-f169.google.com (mail-pg1-f169.google.com [209.85.215.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1A4F29E061; Tue, 29 Apr 2025 03:44:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745898287; cv=none; b=fiq8+xH9lkbD56xKG2h/E5SnZUqK2mctVl3YjGX80PIhv5vV0udAb2FllhHHXStFG4+WB7leXjxQkn9/ZUElOPQQPK7JaeuGrbWbIBkFjiehzscwuNgeLxTir1J4q7TGPiGbyFr1m0bpkdiq+8wdNpZt67rHp4258p66ZmscbnM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745898287; c=relaxed/simple; bh=iSgQuvf9kmSTE4D2ckw53TzjQOR5RrwNb5r5c6wUTAU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VMNz7ePCCerwohNJpu7iPbSLElKSOShX1o+X3W6Vu3rzNMzucFiUGLpXBreMrS6qBZl6Vj5m+xvpgqe4jHeQPUbY6y9cK5NQISga3FWz34cMIsdqrmdL6ZTVYWbjQn9CxMpvRSJBkzujijmNFf6rHm0JtWPurFOT0iDlC8Yz8Qg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=J6E+TVTc; arc=none smtp.client-ip=209.85.215.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="J6E+TVTc" Received: by mail-pg1-f169.google.com with SMTP id 41be03b00d2f7-b03bc416962so3909657a12.0; Mon, 28 Apr 2025 20:44:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1745898285; x=1746503085; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=wbV9nsv1jvdE6TIAVwMdOO2R8WMK9uKpowquURgrnXA=; b=J6E+TVTcHqoic2FWSsiS5LN/14fa2uPfGX3dELQBYfXQmp4H7Y8u19Ui1/rCVL2Qk4 cFAIBuZQxFeB4MDIedWDkRFopHgbvHfrCrc83bzfLBO522CYwhPT7WE9OoAw1SA2QB/R 5Mf3Q4mA7jsVRWcQ0ykfc1s0B64jVPB+MwvS7QxZkOpNQoQ5WS8Q7UCDx2hr0TsWdGss 9QunY3DRHxgz409gXlSv1D2HJB73E5/iiTC2snZMo+j6Bp8QONaw5t7YzFTsB8Zl7/oT G6aZutM8y4JRoEj+M27tM4IPw5gYSXRJU0zDK8T+j1JmylFi+tJduSvQLeLrvXmD9X3g ug6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745898285; x=1746503085; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wbV9nsv1jvdE6TIAVwMdOO2R8WMK9uKpowquURgrnXA=; b=uQok+ATcNRAlGR6IoX9aejf4QP0Q6g2VIqmauC19PvZbxP3wygkKnw8lcPEjWCYBi4 NcRT+iU8cqnMAGwUp/1TDrzffYsgZRolohYj28NUfXrJrekIFRXeHCfDbRGv9QJo05jY K8DQqMjKjb0P8+bOmBtyky0EuuNs7IDXIURO6ijEq+IDNX4zl4n26BIM5M3fG7kWAgcU o2nWaW20Ha9c5JP1wfyXrzpFsk1qNVJozS814Esp4ezWtoYjIJG58YiQ4wH4Mft/Pluw dWyApkSf7/qoZgqdPvwOYgzeqUSJ3FzSxtI0gzixBl2E5qbL0abhAbAMbQwR5FM0fovd 3/Gw== X-Forwarded-Encrypted: i=1; AJvYcCUAeqzqdRmn70AbfbfCE5Fzrb29ZvQWv4grgth2poCkWtNVyO0/cIy14aOXh/ezsu9sNT2SMl/l/qdmqLxA38CiFQ==@vger.kernel.org, AJvYcCW8GM27il2mRkSyvz1vq+NxqKHpuH7Kbo7w2J/tJUeb6PznmRMGSt3fNnVou+qzyrNJHu59o15WT1YW@vger.kernel.org, AJvYcCWh2oj77cDhRsAfAPm7EtgCMVSb5/4tABW09A0ZykCFUDMfK28ee7XxcdsD3HdVTfEsALTpNdkkabWQVpnZ@vger.kernel.org X-Gm-Message-State: AOJu0YxWPgHdThsJBZbqGbH9ZpxOpIV7kOVVfHnRgnqyo9M4kpdAwjxG //j+hiIWXH7+RIG031UNsktvzEtocY3bd9Y/tFlJMcqkHrIY0O61 X-Gm-Gg: ASbGncs/DiINV3uZzeYo2Z/Ngyc56kl/f0TQr3M4swHxt9AR+lqaDcGPzSNbmECs60S 3CkG06WnZd5IG/QFmCDEerpJlPgGAwtiDAfurnmRBXkbcolJHj37NRbw97jF5oi0YWE5m+sJNfw WmUQw1eyiIbiSslpFIO78tW6X0npOuJZjrN/T+84UnvdvJguQPkz34gq2+2hp7I9jKFOGyqSiMl ghsqZs8nlDZmZh2JGc4vc5/D3vSVeyv8Qd1RGWwS/pcyws1mhto/J2N5iZl6uBD4ivyoQv4ebn1 k6Jnq1gGcDsagtqsg3iPY7XDrK6uYJtbAr+zMz6xKm7+cS+kw2TgAYckzA== X-Google-Smtp-Source: AGHT+IFEbVkPWYNQnY1Eec1Z/JJdXhHAO0h1WUxh3tHn6ObSEJqONbzchnPFoKFOa85JTrCDNEdlqg== X-Received: by 2002:a17:90b:2dd2:b0:2fe:9581:fbea with SMTP id 98e67ed59e1d1-30a013bcc03mr14963519a91.29.1745898285220; Mon, 28 Apr 2025 20:44:45 -0700 (PDT) Received: from [127.0.1.1] (wf121-134.ust.hk. [175.159.121.134]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-309ef03bb7fsm9953249a91.9.2025.04.28.20.44.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 20:44:44 -0700 (PDT) From: Nick Chan Date: Tue, 29 Apr 2025 11:42:44 +0800 Subject: [PATCH RESEND v6 20/21] arm64: dts: apple: t8012: Add CPU PMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250429-apple-cpmu-v6-20-ed21815f0c3f@gmail.com> References: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> In-Reply-To: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=893; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=iSgQuvf9kmSTE4D2ckw53TzjQOR5RrwNb5r5c6wUTAU=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoEErmBO4nJnK5mFPF40lad4p+BSKJJgrH+MZn7 sq2/grmPHyJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaBBK5gAKCRABygi3psUI JOtkD/9p5R5bmRzF8RZxw0kgeMs0uNsPHoqfnYjW+vmoqBbxtxeoO6ad3tbGJ9wfuvHxK5mpxMO wIxI0CXw5vmijcdumpsQcOkB7JVaZqrID7+Zr2ye58YFLpFWKRi77q8ffHFHrZ8Gggm7Og8Xvol UNbMssQR1fLxePqjUnfSST7/n0t+HiJWcDRdW9XFizJH9wyZ/NrTeRki6N78F3yUwO0cH/z6F7g /TORZXoKldoHsSHanyvFdJGj+lsrBcabdzp4zokYekXiYccfG6pqPXMgdBhmfhwrog/v5reAbIx Kvb3p8CQbxgnD8rLuo7rq//4nOouJoC6oHHuRWNs8aZHw7fNea65Qhy6+yodo6haAjiZASQrhnp jISf+cvhVA98LZeijP2N8717K/qZj+ArhpITbGmD2GKh8m3bfrqvvIF2OvejSuqODpIGuSHKah4 CsPh8tcbFe3oPcUo3P2gyvVUCpEvTzo+g8ZG6WOWFdNK9nTQkfWRMgUs9qIbDERPFJL6B4X8Fw8 fxb4Hc2Ua4zgvnDMgO8kkTA/sIHAKOQh7D8g/GSapyx5+cynYVtm7CAPPs1JdiXnfcScaCm0W6N +VAlmG7IVsFIgUXnJy1avWP9WKc+tPHEWi8FuYEaAmqrzEfg4cojYwrn6aedQDgUxNR9/9KbXbY cZYlEABjiv6VR7A== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add CPU PMU nodes for Apple T2 SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t8012.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8012.dtsi b/arch/arm64/boot/dts/app= le/t8012.dtsi index 42df2f51ad7be4c4533e76d18e49a9a747b6b7a8..d79ed754c68dd89fc8c52887e6d= cbbce04fe126b 100644 --- a/arch/arm64/boot/dts/apple/t8012.dtsi +++ b/arch/arm64/boot/dts/apple/t8012.dtsi @@ -276,6 +276,14 @@ timer { interrupts =3D , ; }; + + pmu { + compatible =3D "apple,fusion-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D , + ; + interrupt-affinity =3D <&cpu0 &cpu1>; + }; }; =20 #include "t8012-pmgr.dtsi" --=20 2.49.0 From nobody Sun Feb 8 04:34:39 2026 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3945429E07F; Tue, 29 Apr 2025 03:44:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.169 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745898290; cv=none; b=PnMyM1dLcKkAw71p5DQ1i1vAeNU9LEl6FQvvmFyIB0SSChZXgOuepy4xfix7nvECByH/7s6iYQvPOMcn5k5hnirOllMSYjORHMt4R37Vogr/KUvojfAxuTHLJExXWcSwf/sozthwwi8SFEY0ueEryMUuxLkKlJdE0IOkQUqhC3Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745898290; c=relaxed/simple; bh=ZHoXysjC3tKjwBhupXya9t0tvevKJFeLclU2Q2P4acg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AC8Jw1nqG2/07/wGkeMk/2AhMOhpXydZbJkUde3rIOizZDY3N0Ia/BUZPHP7nMg7Rh4Y9l1I/b2cIHu+Vb/TJQXYOWDTZi7gdElP6+r16P16qQ3sbNTvnwy2bj3zfs1pGEfngSHRGpKzJz162nfghWp9Qj51xeIQ32E7R2R6LrY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Dv7V7AJE; arc=none smtp.client-ip=209.85.214.169 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Dv7V7AJE" Received: by mail-pl1-f169.google.com with SMTP id d9443c01a7336-2241053582dso83035375ad.1; Mon, 28 Apr 2025 20:44:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1745898288; x=1746503088; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=YgYxG+vTxBAlApfr9OfPBfVTpSGem7njEO/S/STMqlg=; b=Dv7V7AJE89JWOJ9BwDOFhfhCQxspaPNCxU2oDqs7/IYQ71psWWm4Gcoop9xnqzOMHy mUzP7Va2b9cdN5uVU54K0n1gurtMtOUZXdJOtvTiRXskE8bcfL+LxUhaDD9CCfAs3vFy jk9CpnMR18ovIsRVuCCOe9RIciafLbUJHpA0jnnRuU000M/gq31gfW12Oo31zEHZpgpR LIyYeBa7vminjOeeLAtJ9Ll4/UYPYp6cftQnysPVsqfLnUug5aZxO3kP/xxOdEjeoiBr CYSP7MbvdJRQrwwFh2cZcY+cmy4r/b972VPYhbRdRVqsu8pmF6lMAv2FIM+YqbAuHh+y nANg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745898288; x=1746503088; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YgYxG+vTxBAlApfr9OfPBfVTpSGem7njEO/S/STMqlg=; b=dWSGLPmM22FWZmgGJ4XgImndAmTMyIFIvssDkZtNFnSpKgUJG+LlMIguGTo1xtYFi5 BlZW7oJHe8A326FGYruOi+SFQC9mShpg4Zq6xN5wUWvgeqz/lMKzWyrx4wbSpXZUfU2X d7Mk5+RdCC8j6Le3H9zkF1w1/MPJXVu5gCbhVUXUD+SpJ0VdN22CLdJlafzrJZDRhETD dYh3nIZCecfcgc9hGud7YjfyIxU+n716xouhkVevzEjyX210WQ5pHCozFbBCzlr53DN7 l1vc/i2aa5qHsl2zL2esb4WjuaI2rdV0t/jDAGvkiGI5u1MM3AzVXENi2TSXNP8/NisN cyaw== X-Forwarded-Encrypted: i=1; AJvYcCUdwfE5vp+z0fs+KN1BM3QSbOOyo0PJFpJ76+Nix4S+snSYyUSB7EmNr6RPezg46ClYuL5bcUhLks5iQZBo@vger.kernel.org, AJvYcCWGA/FYgtH5Kr9ndiSmve9l7grwDP2ciK6GtFATeK6asFW7qDWQRtYJEwy4zsFC212PgMXLs8R7/iKG@vger.kernel.org, AJvYcCXs+dvvWk9nMW/tvkuqYVxXlRNrcdn3LfmtVnfM43Idt3Bys2ghNERExVgQDxOVmgKKYC5vNPHk/KZ4kxD7bpSF+w==@vger.kernel.org X-Gm-Message-State: AOJu0Yzyyolbj/nTmENzEWqg81U08MTrm6SXvl+4MA45UtXVBwUC22iT VOnAmUEFiu6lzLbg/BkLYTU9VtA7Gsl8YBK6c+lBuXRloGXRdhfq X-Gm-Gg: ASbGnctCxOM8MhJ7cuVCUwMXQwkaTlDDU7JAxhTNcdlZZ/AEVB8W1czUaEzp2ywBnlk 8VgXaqyFdtjeEXzTgiA8ycZuwsExB4JkTOg8L/m15AIVvrTUcxOqGcfVYnzYFCty3O/MMWWhLSZ KcfRanbL+JAL4bEyzpdLMYhxhex8iE1bwwgnPkI4RrTTmfQzC/UH1j5V+VdkF7Q7wRjTPy/2GY+ Tf6G2HSaCpEBoXQ4t4erNrSn5JI3TYyeDvPphW4i/yjt624AuAPIHOEQjbauPNZyqyEBvbh4hn0 ogdghccZSVggvM670WdTnMVEePmK1aTfwgxMtNlJQVl+P2XoxgDODvPqz0ioBtaw4HYx X-Google-Smtp-Source: AGHT+IG+mbGfHby4oN4mif/0xWyzRBGUvzT/O7NjVxUxLjebSyALlk4r0nPv9AAtoDtPEV0kMXU5LA== X-Received: by 2002:a17:903:24e:b0:220:e023:8fa6 with SMTP id d9443c01a7336-22dc6a87a3bmr149376745ad.50.1745898288540; Mon, 28 Apr 2025 20:44:48 -0700 (PDT) Received: from [127.0.1.1] (wf121-134.ust.hk. [175.159.121.134]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-309ef03bb7fsm9953249a91.9.2025.04.28.20.44.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 20:44:48 -0700 (PDT) From: Nick Chan Date: Tue, 29 Apr 2025 11:42:45 +0800 Subject: [PATCH RESEND v6 21/21] arm64: dts: apple: t8015: Add CPU PMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250429-apple-cpmu-v6-21-ed21815f0c3f@gmail.com> References: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> In-Reply-To: <20250429-apple-cpmu-v6-0-ed21815f0c3f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1462; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=ZHoXysjC3tKjwBhupXya9t0tvevKJFeLclU2Q2P4acg=; b=owEBbQKS/ZANAwAKAQHKCLemxQgkAcsmYgBoEErmS1j7IbxLQZFLwnkOWnyGSToxunf+XJVbp 2Po03ztjQmJAjMEAAEKAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCaBBK5gAKCRABygi3psUI JEnzD/4oHcDES/A3PK30mbJojwRLni5u89YxyaUUXYibt356GrRUeaB9TaCO01jQtOCbCyLwdng YYLhyzjLX5WGz+LVCOpox/FejgYqaGmOs48zTsdrza7jrrcapf4Gm3y4u9LGy1oivwzW4eSvHqe BclP4UmTlBVeLCZgD5Lpdx1Y7gGcA/kE0oKbae+SCi23mdmVMa6uVCUd0YrwMGRwglDR/DNE33E v8Pk7JisxFreQLuncLRqBJXpYzB5lDbB3XxsnmuZqNuT1SDyjwK+EHMGuNIsXLBLF+FjFwQJ4dC NKmL4l+qJPyZJ2badP5lsPMumOQ4E882OtRIGWLojoc2W7DzjrPbPSrZ8FzILxZtDwxyLqHALf5 rOlZ/n4kepyshmCA1terQLnhNH66s4MEPKSTRqIdbOmpaOJAmQr0q7xehYOTcQtkOxik80Dizob 5UAtpDS+m2hl3rgIk/L4thrBIfq5YVY+5kPuZ77KP9UEJoxKoopvnY8AedI6CZ8Kj4Vk496/r7k bIw0zf4Dv76CCEY/S9EJdSOe1UG0VMQEbYtoarAGR3tYr8skigSk++wEkiMdMIAddQ+ryWvepQS dNNrxD1hBKlDuXAs4WdEvD7FLxKx9p3JaA56Abb1PxNiE8S85h95aE0WQHyuIURre8/c7Wb3kcv wjboZ0P2NAD9FNg== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add CPU PMU nodes for Apple A11 SoC. Signed-off-by: Nick Chan --- arch/arm64/boot/dts/apple/t8015.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8015.dtsi b/arch/arm64/boot/dts/app= le/t8015.dtsi index 4d54afcecd50b50ed1fd386ccfc46c373e190e6b..e838b65ea63eef9c198032ee87e= 63dae282141dc 100644 --- a/arch/arm64/boot/dts/apple/t8015.dtsi +++ b/arch/arm64/boot/dts/apple/t8015.dtsi @@ -252,6 +252,18 @@ aic: interrupt-controller@232100000 { #interrupt-cells =3D <3>; interrupt-controller; power-domains =3D <&ps_aic>; + + affinities { + e-core-pmu-affinity { + apple,fiq-index =3D ; + cpus =3D <&cpu_e0 &cpu_e1 &cpu_e2 &cpu_e3>; + }; + + p-core-pmu-affinity { + apple,fiq-index =3D ; + cpus =3D <&cpu_p0 &cpu_p1>; + }; + }; }; =20 pmgr: power-management@232000000 { @@ -380,6 +392,18 @@ timer { interrupts =3D , ; }; + + pmu-e { + compatible =3D "apple,mistral-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D ; + }; + + pmu-p { + compatible =3D "apple,monsoon-pmu"; + interrupt-parent =3D <&aic>; + interrupts =3D ; + }; }; =20 #include "t8015-pmgr.dtsi" --=20 2.49.0