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Mon, 28 Apr 2025 11:42:03 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Richard Cochran Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 1/2] clk: renesas: rzv2h-cpg: Skip monitor checks for external clocks Date: Mon, 28 Apr 2025 19:41:51 +0100 Message-ID: <20250428184152.428908-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428184152.428908-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250428184152.428908-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Introduce support for module clocks that may be sourced from an external clock rather than the on-chip PLL. Add two new fields `external_clk` and `external_clk_mux_index` to `struct rzv2h_mod_clk` and `struct mod_clock` to mark such clocks and record the mux index corresponding to the external input. Provide a new helper macro `DEF_MOD_MUX_EXTERNAL()` for concise declaration of external-source module clocks. In `rzv2h_mod_clock_is_enabled()`, detect when the parent mux selects the external source (by comparing the current mux index against `external_clk_mux_index`) and skip the normal CLK_MON register check in that case. Update `rzv2h_cpg_register_mod_clk()` to populate the new fields from the SoC info. Signed-off-by: Lad Prabhakar --- v2->v3: - Renamed helper macro to `DEF_MOD_MUX_EXTERNAL()`. - Added a new field `external_clk_mux_index` to `struct mod_clock` to store the mux index corresponding to the external input. - Updated the `rzv2h_mod_clock_is_enabled()` function to check if the parent mux selects the external source by comparing the current mux index against `external_clk_mux_index`. - Updated the `rzv2h_cpg_register_mod_clk()` function to populate the new fields from the SoC info. - Updated commit description v1->v2: - None --- drivers/clk/renesas/rzv2h-cpg.c | 31 ++++++++++++++++++++++++++++++- drivers/clk/renesas/rzv2h-cpg.h | 23 +++++++++++++++++++---- 2 files changed, 49 insertions(+), 5 deletions(-) diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cp= g.c index bcc496e8cbcd..e03c9801d2e9 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -119,6 +119,8 @@ struct pll_clk { * @on_bit: ON/MON bit * @mon_index: monitor register offset * @mon_bit: monitor bit + * @external_clk: Boolean flag indicating whether the parent clock can be = an external clock + * @external_clk_mux_index: Index of the clock mux selection when the sour= ce is an external clock */ struct mod_clock { struct rzv2h_cpg_priv *priv; @@ -129,6 +131,8 @@ struct mod_clock { u8 on_bit; s8 mon_index; u8 mon_bit; + bool external_clk; + u8 external_clk_mux_index; }; =20 #define to_mod_clock(_hw) container_of(_hw, struct mod_clock, hw) @@ -567,10 +571,33 @@ static int rzv2h_mod_clock_is_enabled(struct clk_hw *= hw) { struct mod_clock *clock =3D to_mod_clock(hw); struct rzv2h_cpg_priv *priv =3D clock->priv; + bool skip_mon =3D false; u32 bitmask; u32 offset; =20 - if (clock->mon_index >=3D 0) { + if (clock->mon_index >=3D 0 && clock->external_clk) { + struct clk_hw *parent_hw; + struct clk *parent_clk; + struct clk_mux *mux; + int index; + u32 val; + + parent_clk =3D clk_get_parent(hw->clk); + if (IS_ERR(parent_clk)) + goto check_mon; + + parent_hw =3D __clk_get_hw(parent_clk); + mux =3D to_clk_mux(parent_hw); + + val =3D readl(mux->reg) >> mux->shift; + val &=3D mux->mask; + index =3D clk_mux_val_to_index(parent_hw, mux->table, 0, val); + if (index =3D=3D clock->external_clk_mux_index) + skip_mon =3D true; + } + +check_mon: + if (clock->mon_index >=3D 0 && !skip_mon) { offset =3D GET_CLK_MON_OFFSET(clock->mon_index); bitmask =3D BIT(clock->mon_bit); =20 @@ -687,6 +714,8 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *= mod, clock->mon_index =3D mod->mon_index; clock->mon_bit =3D mod->mon_bit; clock->no_pm =3D mod->no_pm; + clock->external_clk =3D mod->external_clk; + clock->external_clk_mux_index =3D mod->external_clk_mux_index; clock->priv =3D priv; clock->hw.init =3D &init; clock->mstop_data =3D mod->mstop_data; diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cp= g.h index 449f8c82e8fb..687587033688 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -192,6 +192,8 @@ enum clk_types { * @on_bit: ON bit * @mon_index: monitor register index * @mon_bit: monitor bit + * @external_clk: Boolean flag indicating whether the parent clock can be = an external clock + * @external_clk_mux_index: Index of the clock mux selection when the sour= ce is an external clock */ struct rzv2h_mod_clk { const char *name; @@ -203,9 +205,12 @@ struct rzv2h_mod_clk { u8 on_bit; s8 mon_index; u8 mon_bit; + bool external_clk; + u8 external_clk_mux_index; }; =20 -#define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, = _onbit, _monindex, _monbit) \ +#define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, \ + _onbit, _monindex, _monbit, _external_clk, _external_clk_mux_index)= \ { \ .name =3D (_name), \ .mstop_data =3D (_mstop), \ @@ -216,16 +221,26 @@ struct rzv2h_mod_clk { .on_bit =3D (_onbit), \ .mon_index =3D (_monindex), \ .mon_bit =3D (_monbit), \ + .external_clk =3D (_external_clk), \ + .external_clk_mux_index =3D (_external_clk_mux_index), \ } =20 #define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mst= op) \ - DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _mon= index, _monbit) + DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _mon= index, _monbit, \ + false, 0) =20 #define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _mon= bit, _mstop) \ - DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _moni= ndex, _monbit) + DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _moni= ndex, _monbit, \ + false, 0) =20 #define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit= , _mstop) \ - DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _moni= ndex, _monbit) + DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _moni= ndex, _monbit, \ + false, 0) + +#define DEF_MOD_MUX_EXTERNAL(_name, _parent, _onindex, _onbit, _monindex, = _monbit, _mstop, \ + _external_clk_mux_index) \ + DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _mon= index, _monbit, \ + true, _external_clk_mux_index) =20 /** * struct rzv2h_reset - Reset definitions --=20 2.49.0 From nobody Mon Feb 9 13:10:36 2026 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40E612951BF; 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Mon, 28 Apr 2025 11:42:05 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:593b:8313:b361:2f0]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-440a52f89b2sm137745995e9.8.2025.04.28.11.42.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Apr 2025 11:42:04 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Richard Cochran Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 2/2] clk: renesas: r9a09g057: Add clock and reset entries for GBETH0/1 Date: Mon, 28 Apr 2025 19:41:52 +0100 Message-ID: <20250428184152.428908-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250428184152.428908-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250428184152.428908-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add clock and reset entries for GBETH instances. Include core clocks for PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks used as clock sources for the GBETH IP. Signed-off-by: Lad Prabhakar --- v2->v3: - Used DEF_MOD_MUX_EXTERNAL() macro for external MUX clocks. - Renamed gbe0/1 external mux clock names v1->v2: - None --- drivers/clk/renesas/r9a09g057-cpg.c | 64 +++++++++++++++++++++++++++++ drivers/clk/renesas/rzv2h-cpg.h | 11 +++++ 2 files changed, 75 insertions(+) diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a0= 9g057-cpg.c index 3c40e36259fe..da908e820950 100644 --- a/drivers/clk/renesas/r9a09g057-cpg.c +++ b/drivers/clk/renesas/r9a09g057-cpg.c @@ -29,6 +29,7 @@ enum clk_ids { CLK_PLLDTY, CLK_PLLCA55, CLK_PLLVDO, + CLK_PLLETH, CLK_PLLGPU, =20 /* Internal Core Clocks */ @@ -49,6 +50,14 @@ enum clk_ids { CLK_PLLVDO_CRU1, CLK_PLLVDO_CRU2, CLK_PLLVDO_CRU3, + CLK_PLLETH_DIV_250_FIX, + CLK_PLLETH_DIV_125_FIX, + CLK_CSDIV_PLLETH_GBE0, + CLK_CSDIV_PLLETH_GBE1, + CLK_SMUX2_GBE0_TXCLK, + CLK_SMUX2_GBE0_RXCLK, + CLK_SMUX2_GBE1_TXCLK, + CLK_SMUX2_GBE1_RXCLK, CLK_PLLGPU_GEAR, =20 /* Module Clocks */ @@ -78,6 +87,19 @@ static const struct clk_div_table dtable_2_64[] =3D { {0, 0}, }; =20 +static const struct clk_div_table dtable_2_100[] =3D { + {0, 2}, + {1, 10}, + {2, 100}, + {0, 0}, +}; + +/* Mux clock tables */ +static const char * const smux2_gbe0_rxclk[] =3D { ".plleth_gbe0", "et0_rx= clk" }; +static const char * const smux2_gbe0_txclk[] =3D { ".plleth_gbe0", "et0_tx= clk" }; +static const char * const smux2_gbe1_rxclk[] =3D { ".plleth_gbe1", "et1_rx= clk" }; +static const char * const smux2_gbe1_txclk[] =3D { ".plleth_gbe1", "et1_tx= clk" }; + static const struct cpg_core_clk r9a09g057_core_clks[] __initconst =3D { /* External Clock Inputs */ DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), @@ -90,6 +112,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] _= _initconst =3D { DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55), DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2), + DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3), DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU), =20 /* Internal Core Clocks */ @@ -115,6 +138,17 @@ static const struct cpg_core_clk r9a09g057_core_clks[]= __initconst =3D { DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dta= ble_2_4), DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dta= ble_2_4), =20 + DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4), + DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_F= IX, 1, 2), + DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0, + CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL0, dtable_2_100), + DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1, + CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL1, dtable_2_100), + DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_= gbe0_txclk), + DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_= gbe0_rxclk), + DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_= gbe1_txclk), + DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_= gbe1_rxclk), + DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dta= ble_2_64), =20 /* Core Clocks */ @@ -130,6 +164,10 @@ static const struct cpg_core_clk r9a09g057_core_clks[]= __initconst =3D { DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1,= 1), DEF_FIXED("usb2_0_clk_core0", R9A09G057_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, = 1), DEF_FIXED("usb2_0_clk_core1", R9A09G057_USB2_0_CLK_CORE1, CLK_QEXTAL, 1, = 1), + DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G057_GBETH_0_CLK_PTP_REF_I, + CLK_PLLETH_DIV_125_FIX, 1, 1), + DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G057_GBETH_1_CLK_PTP_REF_I, + CLK_PLLETH_DIV_125_FIX, 1, 1), }; =20 static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst =3D { @@ -233,6 +271,30 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[]= __initconst =3D { BUS_MSTOP(7, BIT(10))), DEF_MOD("usb2_0_pclk_usbtst1", CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23, BUS_MSTOP(7, BIT(11))), + DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, = 24, + BUS_MSTOP(8, BIT(5)), 1), + DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, = 25, + BUS_MSTOP(8, BIT(5)), 1), + DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10= , 5, 26, + BUS_MSTOP(8, BIT(5)), 1), + DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11= , 5, 27, + BUS_MSTOP(8, BIT(5)), 1), + DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28, + BUS_MSTOP(8, BIT(5))), + DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29, + BUS_MSTOP(8, BIT(5))), + DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5,= 30, + BUS_MSTOP(8, BIT(6)), 1), + DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5,= 31, + BUS_MSTOP(8, BIT(6)), 1), + DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0,= 6, 0, + BUS_MSTOP(8, BIT(6)), 1), + DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1,= 6, 1, + BUS_MSTOP(8, BIT(6)), 1), + DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2, + BUS_MSTOP(8, BIT(6))), + DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3, + BUS_MSTOP(8, BIT(6))), DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18, BUS_MSTOP(9, BIT(4))), DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19, @@ -304,6 +366,8 @@ static const struct rzv2h_reset r9a09g057_resets[] __in= itconst =3D { DEF_RST(10, 13, 4, 30), /* USB2_0_U2H1_HRESETN */ DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */ DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */ + DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */ + DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */ DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */ DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */ DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */ diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cp= g.h index 687587033688..a05fb5e7f707 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -93,10 +93,13 @@ struct smuxed { .width =3D (_width), \ }) =20 +#define CPG_SSEL0 (0x300) +#define CPG_SSEL1 (0x304) #define CPG_CDDIV0 (0x400) #define CPG_CDDIV1 (0x404) #define CPG_CDDIV3 (0x40C) #define CPG_CDDIV4 (0x410) +#define CPG_CSDIV0 (0x500) =20 #define CDDIV0_DIVCTL1 DDIV_PACK(CPG_CDDIV0, 4, 3, 1) #define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2) @@ -111,6 +114,14 @@ struct smuxed { #define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17) #define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18) =20 +#define CSDIV0_DIVCTL0 DDIV_PACK(CPG_CSDIV0, 0, 2, CSDIV_NO_MON) +#define CSDIV0_DIVCTL1 DDIV_PACK(CPG_CSDIV0, 4, 2, CSDIV_NO_MON) + +#define SSEL0_SELCTL2 SMUX_PACK(CPG_SSEL0, 8, 1) +#define SSEL0_SELCTL3 SMUX_PACK(CPG_SSEL0, 12, 1) +#define SSEL1_SELCTL0 SMUX_PACK(CPG_SSEL1, 0, 1) +#define SSEL1_SELCTL1 SMUX_PACK(CPG_SSEL1, 4, 1) + #define BUS_MSTOP_IDX_MASK GENMASK(31, 16) #define BUS_MSTOP_BITS_MASK GENMASK(15, 0) #define BUS_MSTOP(idx, mask) (FIELD_PREP_CONST(BUS_MSTOP_IDX_MASK, (idx)) = | \ --=20 2.49.0