From nobody Mon Feb 9 19:53:06 2026 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB6D41DF99C; Mon, 28 Apr 2025 07:21:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745824894; cv=none; b=HXrzTNuHWoR73McfdS1a37AClOmcIzDPxEHX8fPXzBGwOwZaLM6e0Ah4CvN/AdKv1zyPxkXkdaEvKqeLMAr5b0ufbpN5DGyr3Vjj+7VAdCjTYfGs2CmIGen1EeF0XWYwm2Cfs2fXb7jYd63USKefxKi7UaHhli3G6+jgspBijxs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745824894; c=relaxed/simple; bh=3te5LPmJkpHjXH2Vc5I9HPtlBqUQBVrsokKzIQqVe3g=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HxFDU1zb/vwcbd5WnVg95wUTNa5rsY5e2HOIPvGBC1ypbCUAG1boNAmpBi7vHgZY9M3z/NnBv5e2WmWvErZnTFs5VyO6yay7YNgyhiN97Z0rauK9k4bMIuJ8dLvIm6UI6Y0MxUZhxDa8gtMN5b+srXKJry+fSBG1mYavCFSnC/E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=fzAUs6Rd; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="fzAUs6Rd" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 53S7LK8q2714007 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 28 Apr 2025 02:21:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1745824881; bh=JsyrQTZY+NVH5nil6RuG7SvmccuQbuMeBRKoaahJSPk=; h=From:To:Subject:Date:In-Reply-To:References; b=fzAUs6RdtB25icZdW+8rVWmiNJGsRC+dzNX27ABqyRKjmiF5iQ8dcSkPp4lO9Aio2 XpxqMD4RhiuNs1FlcJipWzrP7u9beTzlIT0CFtQ630OCEDLGp5bneY1diVgJwfmN0o 1DyT2ClM9WpaE3CThV6np5EXpA3RcnV5zCO+eJew= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 53S7LKEF016562 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 28 Apr 2025 02:21:20 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 28 Apr 2025 02:21:20 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 28 Apr 2025 02:21:20 -0500 Received: from uda0498651.dhcp.ti.com (uda0498651.dhcp.ti.com [172.24.227.7]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53S7KdMe068873; Mon, 28 Apr 2025 02:21:16 -0500 From: Sai Sree Kartheek Adivi To: , , , , , , , , , , , , , , , Subject: [PATCH 5/8] drivers: soc: ti: k3-ringacc: handle absence of tisci Date: Mon, 28 Apr 2025 12:50:29 +0530 Message-ID: <20250428072032.946008-6-s-adivi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250428072032.946008-1-s-adivi@ti.com> References: <20250428072032.946008-1-s-adivi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Handle absence of tisci with direct register writes. This will support platforms that do not have tisci firmware like AM62L. Signed-off-by: Sai Sree Kartheek Adivi --- drivers/soc/ti/k3-ringacc.c | 162 +++++++++++++++++++++++++----- include/linux/soc/ti/k3-ringacc.h | 4 + 2 files changed, 142 insertions(+), 24 deletions(-) diff --git a/drivers/soc/ti/k3-ringacc.c b/drivers/soc/ti/k3-ringacc.c index 82a15cad1c6c4..49e0483676a14 100644 --- a/drivers/soc/ti/k3-ringacc.c +++ b/drivers/soc/ti/k3-ringacc.c @@ -45,6 +45,38 @@ struct k3_ring_rt_regs { u32 hwindx; }; =20 +#define K3_RINGACC_RT_CFG_REGS_OFS 0x40 +#define K3_DMARING_CFG_ADDR_HI_MASK GENMASK(3, 0) +#define K3_DMARING_CFG_ASEL_SHIFT 16 +#define K3_DMARING_CFG_SIZE_MASK GENMASK(15, 0) + +/** + * struct k3_ring_cfg_regs - The RA Configuration Registers region + * + * @ba_lo: Ring Base Address Low Register + * @ba_hi: Ring Base Address High Register + * @size: Ring Size Register + */ +struct k3_ring_cfg_regs { + u32 ba_lo; + u32 ba_hi; + u32 size; +}; + +#define K3_RINGACC_RT_INT_REGS_OFS 0x140 +#define K3_RINGACC_RT_INT_ENABLE_SET_COMPLETE BIT(0) +#define K3_RINGACC_RT_INT_ENABLE_SET_TR BIT(2) + +struct k3_ring_intr_regs { + u32 enable_set; + u32 resv_4; + u32 clr; + u32 resv_16; + u32 status_set; + u32 resv_8; + u32 status; +}; + #define K3_RINGACC_RT_REGS_STEP 0x1000 #define K3_DMARING_RT_REGS_STEP 0x2000 #define K3_DMARING_RT_REGS_REVERSE_OFS 0x1000 @@ -157,6 +189,8 @@ struct k3_ring_state { */ struct k3_ring { struct k3_ring_rt_regs __iomem *rt; + struct k3_ring_cfg_regs __iomem *cfg; + struct k3_ring_intr_regs __iomem *intr; struct k3_ring_fifo_regs __iomem *fifos; struct k3_ringacc_proxy_target_regs __iomem *proxy; dma_addr_t ring_mem_dma; @@ -465,16 +499,30 @@ static void k3_ringacc_ring_reset_sci(struct k3_ring = *ring) struct ti_sci_msg_rm_ring_cfg ring_cfg =3D { 0 }; struct k3_ringacc *ringacc =3D ring->parent; int ret; + u32 reg; =20 - ring_cfg.nav_id =3D ringacc->tisci_dev_id; - ring_cfg.index =3D ring->ring_id; - ring_cfg.valid_params =3D TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID; - ring_cfg.count =3D ring->size; + if (!ringacc->tisci) { + if (ring->cfg =3D=3D NULL) + return; + reg =3D readl(&ring->cfg->size); + reg &=3D ~K3_DMARING_CFG_SIZE_MASK; =20 - ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); - if (ret) - dev_err(ringacc->dev, "TISCI reset ring fail (%d) ring_idx %d\n", - ret, ring->ring_id); + writel(reg, &ring->cfg->size); + wmb(); + reg |=3D ring->size; + + writel(reg, &ring->cfg->size); + } else { + ring_cfg.nav_id =3D ringacc->tisci_dev_id; + ring_cfg.index =3D ring->ring_id; + ring_cfg.valid_params =3D TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID; + ring_cfg.count =3D ring->size; + + ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); + if (ret) + dev_err(ringacc->dev, "TISCI reset ring fail (%d) ring_idx %d\n", + ret, ring->ring_id); + } } =20 void k3_ringacc_ring_reset(struct k3_ring *ring) @@ -494,16 +542,30 @@ static void k3_ringacc_ring_reconfig_qmode_sci(struct= k3_ring *ring, struct ti_sci_msg_rm_ring_cfg ring_cfg =3D { 0 }; struct k3_ringacc *ringacc =3D ring->parent; int ret; + u32 reg; =20 ring_cfg.nav_id =3D ringacc->tisci_dev_id; ring_cfg.index =3D ring->ring_id; ring_cfg.valid_params =3D TI_SCI_MSG_VALUE_RM_RING_MODE_VALID; ring_cfg.mode =3D mode; =20 - ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); - if (ret) - dev_err(ringacc->dev, "TISCI reconf qmode fail (%d) ring_idx %d\n", - ret, ring->ring_id); + if (!ringacc->tisci) { + writel(ring_cfg.addr_lo, &ring->cfg->ba_lo); + writel((ring_cfg.addr_hi & K3_DMARING_CFG_ADDR_HI_MASK) + + (ring_cfg.asel << K3_DMARING_CFG_ASEL_SHIFT), + &ring->cfg->ba_hi); + + reg =3D readl(&ring->cfg->size); + reg &=3D ~K3_DMARING_CFG_SIZE_MASK; + reg |=3D ring_cfg.count & K3_DMARING_CFG_SIZE_MASK; + + writel(reg, &ring->cfg->size); + } else { + ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); + if (ret) + dev_err(ringacc->dev, "TISCI reconf qmode fail (%d) ring_idx %d\n", + ret, ring->ring_id); + } } =20 void k3_ringacc_ring_reset_dma(struct k3_ring *ring, u32 occ) @@ -570,15 +632,29 @@ static void k3_ringacc_ring_free_sci(struct k3_ring *= ring) struct ti_sci_msg_rm_ring_cfg ring_cfg =3D { 0 }; struct k3_ringacc *ringacc =3D ring->parent; int ret; + u32 reg; =20 ring_cfg.nav_id =3D ringacc->tisci_dev_id; ring_cfg.index =3D ring->ring_id; ring_cfg.valid_params =3D TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER; =20 - ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); - if (ret) - dev_err(ringacc->dev, "TISCI ring free fail (%d) ring_idx %d\n", - ret, ring->ring_id); + if (!ringacc->tisci) { + writel(ring_cfg.addr_lo, &ring->cfg->ba_lo); + writel((ring_cfg.addr_hi & K3_DMARING_CFG_ADDR_HI_MASK) + + (ring_cfg.asel << K3_DMARING_CFG_ASEL_SHIFT), + &ring->cfg->ba_hi); + + reg =3D readl(&ring->cfg->size); + reg &=3D ~K3_DMARING_CFG_SIZE_MASK; + reg |=3D ring_cfg.count & K3_DMARING_CFG_SIZE_MASK; + + writel(reg, &ring->cfg->size); + } else { + ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); + if (ret) + dev_err(ringacc->dev, "TISCI ring free fail (%d) ring_idx %d\n", + ret, ring->ring_id); + } } =20 int k3_ringacc_ring_free(struct k3_ring *ring) @@ -669,15 +745,31 @@ int k3_ringacc_get_ring_irq_num(struct k3_ring *ring) } EXPORT_SYMBOL_GPL(k3_ringacc_get_ring_irq_num); =20 +u32 k3_ringacc_ring_get_irq_status(struct k3_ring *ring) +{ + struct k3_ringacc *ringacc =3D ring->parent; + struct k3_ring *ring2 =3D &ringacc->rings[ring->ring_id]; + + return readl(&ring2->intr->status); +} +EXPORT_SYMBOL_GPL(k3_ringacc_ring_get_irq_status); + +void k3_ringacc_ring_clear_irq(struct k3_ring *ring) +{ + struct k3_ringacc *ringacc =3D ring->parent; + struct k3_ring *ring2 =3D &ringacc->rings[ring->ring_id]; + + writel(0xFF, &ring2->intr->status); +} +EXPORT_SYMBOL_GPL(k3_ringacc_ring_clear_irq); + static int k3_ringacc_ring_cfg_sci(struct k3_ring *ring) { struct ti_sci_msg_rm_ring_cfg ring_cfg =3D { 0 }; struct k3_ringacc *ringacc =3D ring->parent; + u32 reg; int ret; =20 - if (!ringacc->tisci) - return -EINVAL; - ring_cfg.nav_id =3D ringacc->tisci_dev_id; ring_cfg.index =3D ring->ring_id; ring_cfg.valid_params =3D TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER; @@ -688,11 +780,26 @@ static int k3_ringacc_ring_cfg_sci(struct k3_ring *ri= ng) ring_cfg.size =3D ring->elm_size; ring_cfg.asel =3D ring->asel; =20 + if (!ringacc->tisci) { + writel(ring_cfg.addr_lo, &ring->cfg->ba_lo); + writel((ring_cfg.addr_hi & K3_DMARING_CFG_ADDR_HI_MASK) + + (ring_cfg.asel << K3_DMARING_CFG_ASEL_SHIFT), + &ring->cfg->ba_hi); + + reg =3D readl(&ring->cfg->size); + reg &=3D ~K3_DMARING_CFG_SIZE_MASK; + reg |=3D ring_cfg.count & K3_DMARING_CFG_SIZE_MASK; + + writel(reg, &ring->cfg->size); + writel(K3_RINGACC_RT_INT_ENABLE_SET_COMPLETE | K3_RINGACC_RT_INT_ENABLE_= SET_TR, + &ring->intr->enable_set); + return 0; + } + ret =3D ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); if (ret) dev_err(ringacc->dev, "TISCI config ring fail (%d) ring_idx %d\n", - ret, ring->ring_id); - + ret, ring->ring_id); return ret; } =20 @@ -1480,9 +1587,12 @@ struct k3_ringacc *k3_ringacc_dmarings_init(struct p= latform_device *pdev, =20 mutex_init(&ringacc->req_lock); =20 - base_rt =3D devm_platform_ioremap_resource_byname(pdev, "ringrt"); - if (IS_ERR(base_rt)) - return ERR_CAST(base_rt); + base_rt =3D data->base_rt; + if (!base_rt) { + base_rt =3D devm_platform_ioremap_resource_byname(pdev, "ringrt"); + if (IS_ERR(base_rt)) + return ERR_CAST(base_rt); + } =20 ringacc->rings =3D devm_kzalloc(dev, sizeof(*ringacc->rings) * @@ -1498,6 +1608,10 @@ struct k3_ringacc *k3_ringacc_dmarings_init(struct p= latform_device *pdev, struct k3_ring *ring =3D &ringacc->rings[i]; =20 ring->rt =3D base_rt + K3_DMARING_RT_REGS_STEP * i; + ring->cfg =3D base_rt + K3_RINGACC_RT_CFG_REGS_OFS + + K3_DMARING_RT_REGS_STEP * i; + ring->intr =3D base_rt + K3_RINGACC_RT_INT_REGS_OFS + + K3_DMARING_RT_REGS_STEP * i; ring->parent =3D ringacc; ring->ring_id =3D i; ring->proxy_id =3D K3_RINGACC_PROXY_NOT_USED; diff --git a/include/linux/soc/ti/k3-ringacc.h b/include/linux/soc/ti/k3-ri= ngacc.h index 39b022b925986..fcf6fbd4a8594 100644 --- a/include/linux/soc/ti/k3-ringacc.h +++ b/include/linux/soc/ti/k3-ringacc.h @@ -158,6 +158,9 @@ u32 k3_ringacc_get_ring_id(struct k3_ring *ring); */ int k3_ringacc_get_ring_irq_num(struct k3_ring *ring); =20 +u32 k3_ringacc_ring_get_irq_status(struct k3_ring *ring); +void k3_ringacc_ring_clear_irq(struct k3_ring *ring); + /** * k3_ringacc_ring_cfg - ring configure * @ring: pointer on ring @@ -262,6 +265,7 @@ struct k3_ringacc_init_data { const struct ti_sci_handle *tisci; u32 tisci_dev_id; u32 num_rings; + void __iomem *base_rt; }; =20 struct k3_ringacc *k3_ringacc_dmarings_init(struct platform_device *pdev, --=20 2.34.1