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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2025 06:26:34.0233 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7188e9cb-0112-48be-e588-08dd861d9f4a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017090.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8266 Content-Type: text/plain; charset="utf-8" Rename and use the existing amd_pstate_epp callbacks for amd_pstate driver as well. Remove the debug print in online callback while at it. These callbacks will be needed to support the "Requested CPU Min Frequency" BIOS option. Reviewed-by: Mario Limonciello Signed-off-by: Dhananjay Ugwekar --- drivers/cpufreq/amd-pstate.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index c29840ba3b30..02de51001eba 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1568,19 +1568,17 @@ static int amd_pstate_epp_set_policy(struct cpufreq= _policy *policy) return 0; } =20 -static int amd_pstate_epp_cpu_online(struct cpufreq_policy *policy) +static int amd_pstate_cpu_online(struct cpufreq_policy *policy) { - pr_debug("AMD CPU Core %d going online\n", policy->cpu); - return amd_pstate_cppc_enable(policy); } =20 -static int amd_pstate_epp_cpu_offline(struct cpufreq_policy *policy) +static int amd_pstate_cpu_offline(struct cpufreq_policy *policy) { return 0; } =20 -static int amd_pstate_epp_suspend(struct cpufreq_policy *policy) +static int amd_pstate_suspend(struct cpufreq_policy *policy) { struct amd_cpudata *cpudata =3D policy->driver_data; =20 @@ -1618,6 +1616,9 @@ static struct cpufreq_driver amd_pstate_driver =3D { .fast_switch =3D amd_pstate_fast_switch, .init =3D amd_pstate_cpu_init, .exit =3D amd_pstate_cpu_exit, + .online =3D amd_pstate_cpu_online, + .offline =3D amd_pstate_cpu_offline, + .suspend =3D amd_pstate_suspend, .set_boost =3D amd_pstate_set_boost, .update_limits =3D amd_pstate_update_limits, .name =3D "amd-pstate", @@ -1630,9 +1631,9 @@ static struct cpufreq_driver amd_pstate_epp_driver = =3D { .setpolicy =3D amd_pstate_epp_set_policy, .init =3D amd_pstate_epp_cpu_init, .exit =3D amd_pstate_epp_cpu_exit, - .offline =3D amd_pstate_epp_cpu_offline, - .online =3D amd_pstate_epp_cpu_online, - .suspend =3D amd_pstate_epp_suspend, + .offline =3D amd_pstate_cpu_offline, + .online =3D amd_pstate_cpu_online, + .suspend =3D amd_pstate_suspend, .resume =3D amd_pstate_epp_resume, .update_limits =3D amd_pstate_update_limits, .set_boost =3D amd_pstate_set_boost, --=20 2.34.1 From nobody Sun Dec 14 19:35:45 2025 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2073.outbound.protection.outlook.com [40.107.237.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9518D28399; 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Mon, 28 Apr 2025 02:16:50 -0500 From: Dhananjay Ugwekar To: , CC: , , "Dhananjay Ugwekar" Subject: [PATCH v3 2/2] cpufreq/amd-pstate: Add support for the "Requested CPU Min frequency" BIOS option Date: Mon, 28 Apr 2025 07:16:24 +0000 Message-ID: <20250428071623.4309-1-dhananjay.ugwekar@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250428062520.4997-1-dhananjay.ugwekar@amd.com> References: <20250428062520.4997-1-dhananjay.ugwekar@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000A672F:EE_|BL3PR12MB6449:EE_ X-MS-Office365-Filtering-Correlation-Id: a08ff8d3-209a-4b84-fd32-08dd8624a802 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|1800799024|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2025 07:16:55.0601 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a08ff8d3-209a-4b84-fd32-08dd8624a802 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A672F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6449 Content-Type: text/plain; charset="utf-8" Initialize lower frequency limit to the "Requested CPU Min frequency" BIOS option (if it is set) value as part of the driver->init() callback. The BIOS specified value is passed by the PMFW as min_perf in CPPC_REQ MSR. To ensure that we don't mistake a stale min_perf value in CPPC_REQ value as the "Requested CPU Min frequency" during a kexec wakeup, reset the CPPC_REQ.min_perf value back to the BIOS specified one in the offline, exit and suspend callbacks. amd_pstate_target() and amd_pstate_epp_update_limit() which are invoked as part of the resume() and online() callbacks will take care of restoring the CPPC_REQ back to the correct values. Signed-off-by: Dhananjay Ugwekar Reviewed-by: Mario Limonciello --- Changes since v2: * Add resume callback to reset the CPPC_REQ to last sane value for amd-pstate driver * Check update_perf's return value in amd_pstate_suspend --- drivers/cpufreq/amd-pstate.c | 82 ++++++++++++++++++++++++++++++------ drivers/cpufreq/amd-pstate.h | 2 + 2 files changed, 71 insertions(+), 13 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 02de51001eba..4da03c7c7fe3 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -389,7 +389,8 @@ static inline int amd_pstate_cppc_enable(struct cpufreq= _policy *policy) static int msr_init_perf(struct amd_cpudata *cpudata) { union perf_cached perf =3D READ_ONCE(cpudata->perf); - u64 cap1, numerator; + u64 cap1, numerator, cppc_req; + u8 min_perf; =20 int ret =3D rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, &cap1); @@ -400,6 +401,22 @@ static int msr_init_perf(struct amd_cpudata *cpudata) if (ret) return ret; =20 + ret =3D rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &cppc_req); + if (ret) + return ret; + + WRITE_ONCE(cpudata->cppc_req_cached, cppc_req); + min_perf =3D FIELD_GET(AMD_CPPC_MIN_PERF_MASK, cppc_req); + + /* + * Clear out the min_perf part to check if the rest of the MSR is 0, if y= es, this is an + * indication that the min_perf value is the one specified through the BI= OS option + */ + cppc_req &=3D ~(AMD_CPPC_MIN_PERF_MASK); + + if (!cppc_req) + perf.bios_min_perf =3D min_perf; + perf.highest_perf =3D numerator; perf.max_limit_perf =3D numerator; perf.min_limit_perf =3D FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1); @@ -580,20 +597,26 @@ static int amd_pstate_verify(struct cpufreq_policy_da= ta *policy_data) { /* * Initialize lower frequency limit (i.e.policy->min) with - * lowest_nonlinear_frequency which is the most energy efficient - * frequency. Override the initial value set by cpufreq core and - * amd-pstate qos_requests. + * lowest_nonlinear_frequency or the min frequency (if) specified in BIOS, + * Override the initial value set by cpufreq core and amd-pstate qos_requ= ests. */ if (policy_data->min =3D=3D FREQ_QOS_MIN_DEFAULT_VALUE) { struct cpufreq_policy *policy __free(put_cpufreq_policy) =3D cpufreq_cpu_get(policy_data->cpu); struct amd_cpudata *cpudata; + union perf_cached perf; =20 if (!policy) return -EINVAL; =20 cpudata =3D policy->driver_data; - policy_data->min =3D cpudata->lowest_nonlinear_freq; + perf =3D READ_ONCE(cpudata->perf); + + if (perf.bios_min_perf) + policy_data->min =3D perf_to_freq(perf, cpudata->nominal_freq, + perf.bios_min_perf); + else + policy_data->min =3D cpudata->lowest_nonlinear_freq; } =20 cpufreq_verify_within_cpu_limits(policy_data); @@ -1040,6 +1063,10 @@ static int amd_pstate_cpu_init(struct cpufreq_policy= *policy) static void amd_pstate_cpu_exit(struct cpufreq_policy *policy) { struct amd_cpudata *cpudata =3D policy->driver_data; + union perf_cached perf =3D READ_ONCE(cpudata->perf); + + /* Reset CPPC_REQ MSR to the BIOS value */ + amd_pstate_update_perf(policy, perf.bios_min_perf, 0U, 0U, 0U, false); =20 freq_qos_remove_request(&cpudata->req[1]); freq_qos_remove_request(&cpudata->req[0]); @@ -1428,7 +1455,6 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_pol= icy *policy) struct amd_cpudata *cpudata; union perf_cached perf; struct device *dev; - u64 value; int ret; =20 /* @@ -1493,12 +1519,6 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_po= licy *policy) cpudata->epp_default =3D AMD_CPPC_EPP_BALANCE_PERFORMANCE; } =20 - if (cpu_feature_enabled(X86_FEATURE_CPPC)) { - ret =3D rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value); - if (ret) - return ret; - WRITE_ONCE(cpudata->cppc_req_cached, value); - } ret =3D amd_pstate_set_epp(policy, cpudata->epp_default); if (ret) return ret; @@ -1518,6 +1538,11 @@ static void amd_pstate_epp_cpu_exit(struct cpufreq_p= olicy *policy) struct amd_cpudata *cpudata =3D policy->driver_data; =20 if (cpudata) { + union perf_cached perf =3D READ_ONCE(cpudata->perf); + + /* Reset CPPC_REQ MSR to the BIOS value */ + amd_pstate_update_perf(policy, perf.bios_min_perf, 0U, 0U, 0U, false); + kfree(cpudata); policy->driver_data =3D NULL; } @@ -1575,12 +1600,31 @@ static int amd_pstate_cpu_online(struct cpufreq_pol= icy *policy) =20 static int amd_pstate_cpu_offline(struct cpufreq_policy *policy) { - return 0; + struct amd_cpudata *cpudata =3D policy->driver_data; + union perf_cached perf =3D READ_ONCE(cpudata->perf); + + /* + * Reset CPPC_REQ MSR to the BIOS value, this will allow us to retain the= BIOS specified + * min_perf value across kexec reboots. If this CPU is just onlined norma= lly after this, the + * limits, epp and desired perf will get reset to the cached values in cp= udata struct + */ + return amd_pstate_update_perf(policy, perf.bios_min_perf, 0U, 0U, 0U, fal= se); } =20 static int amd_pstate_suspend(struct cpufreq_policy *policy) { struct amd_cpudata *cpudata =3D policy->driver_data; + union perf_cached perf =3D READ_ONCE(cpudata->perf); + int ret; + + /* + * Reset CPPC_REQ MSR to the BIOS value, this will allow us to retain the= BIOS specified + * min_perf value across kexec reboots. If this CPU is just resumed back = without kexec, + * the limits, epp and desired perf will get reset to the cached values i= n cpudata struct + */ + ret =3D amd_pstate_update_perf(policy, perf.bios_min_perf, 0U, 0U, 0U, fa= lse); + if (ret) + return ret; =20 /* invalidate to ensure it's rewritten during resume */ cpudata->cppc_req_cached =3D 0; @@ -1591,6 +1635,17 @@ static int amd_pstate_suspend(struct cpufreq_policy = *policy) return 0; } =20 +static int amd_pstate_resume(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata =3D policy->driver_data; + union perf_cached perf =3D READ_ONCE(cpudata->perf); + int cur_perf =3D freq_to_perf(perf, cpudata->nominal_freq, policy->cur); + + /* Set CPPC_REQ to last sane value until the governor updates it */ + return amd_pstate_update_perf(policy, perf.min_limit_perf, cur_perf, perf= .max_limit_perf, + 0U, false); +} + static int amd_pstate_epp_resume(struct cpufreq_policy *policy) { struct amd_cpudata *cpudata =3D policy->driver_data; @@ -1619,6 +1674,7 @@ static struct cpufreq_driver amd_pstate_driver =3D { .online =3D amd_pstate_cpu_online, .offline =3D amd_pstate_cpu_offline, .suspend =3D amd_pstate_suspend, + .resume =3D amd_pstate_resume, .set_boost =3D amd_pstate_set_boost, .update_limits =3D amd_pstate_update_limits, .name =3D "amd-pstate", diff --git a/drivers/cpufreq/amd-pstate.h b/drivers/cpufreq/amd-pstate.h index fbe1c08d3f06..2f7ae364d331 100644 --- a/drivers/cpufreq/amd-pstate.h +++ b/drivers/cpufreq/amd-pstate.h @@ -30,6 +30,7 @@ * @lowest_perf: the absolute lowest performance level of the processor * @min_limit_perf: Cached value of the performance corresponding to polic= y->min * @max_limit_perf: Cached value of the performance corresponding to polic= y->max + * @bios_min_perf: Cached perf value corresponding to the "Requested CPU M= in Frequency" BIOS option */ union perf_cached { struct { @@ -39,6 +40,7 @@ union perf_cached { u8 lowest_perf; u8 min_limit_perf; u8 max_limit_perf; + u8 bios_min_perf; }; u64 val; }; --=20 2.34.1