From nobody Sun Feb 8 05:43:19 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8AF1C1C2324; Mon, 28 Apr 2025 06:03:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745820208; cv=none; b=B0z0qCpEXXEoEd/q67eVSPsrbnzaFYDgdYy226I0DCCNBP6hfkP6x4DaiPs3H6tLbtcLgI0iyWpfe9pdDvdflaKIbmdGMjbBXdaQ7xP5iEMR/CfL4jKE129cyOIIZcHHpZCXaeH51FN9OorzcVkuPIQ3H9dogGCUwEUcg3gICSg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745820208; c=relaxed/simple; bh=4bGpCp15hXzvEQMTcZCDeMmmBPhJF0lOvOCtQUjv3Qc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ofRDaVxjecpWVXMiw5W0Vxzwkk2VlLoYdiNSKjavgUjHIdTkS234SgSuCN0p4TU2y6LLszTgfjD7/mQzhKyEgYCuNzvxSwW9a+LS6xPPH88H33fs1cBAStc/0feW+WSZCdCZuxPgw+JcZCka5QHlKnlMIWcS15UnfV66gwA44yE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=T47E7lZu; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="T47E7lZu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1745820207; x=1777356207; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4bGpCp15hXzvEQMTcZCDeMmmBPhJF0lOvOCtQUjv3Qc=; b=T47E7lZu2DCJr1Xa0H5KFyTuGOwGb06GNlhWdCBUhMetZkHzrVjqs9UZ qfkvvkZyGjyPs5D9WpJiY/NRTcWYIKRkHfToXGPhGw/N7EY478h/XtDCh +uGK5HEl3Nw+l498XyjD57C3NBxENWfRgEldMsVBO0C/S/aMNEze8P/3N bEo3vP8jJW14tQRZmxqbbcEJr9hjBJbQRsLCdMKOoLwMeGSOFb5iFgDV5 aUYKKVbFpTHvHsBKIJtxJIWivGTkobciF2S9cryfaTpvrjTIma1yPBXpI 9Gmt7KkAb0FBMH2etdCMwb2sFNxZipWf+DnrBW0YQsAMKc8wP4vWwvx0W A==; X-CSE-ConnectionGUID: jejlNfO4SQOcXq260kSGeQ== X-CSE-MsgGUID: ET9OfV65RYin44E3NSSSog== X-IronPort-AV: E=McAfee;i="6700,10204,11416"; a="51064585" X-IronPort-AV: E=Sophos;i="6.15,245,1739865600"; d="scan'208";a="51064585" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2025 23:03:27 -0700 X-CSE-ConnectionGUID: OhCeRr4pS+OBkQloShu9cg== X-CSE-MsgGUID: ndYlet1VSveyRIJujU6BCw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,245,1739865600"; d="scan'208";a="133340732" Received: from mohdfai2-ilbpg12-1.png.intel.com ([10.88.227.73]) by orviesa006.jf.intel.com with ESMTP; 27 Apr 2025 23:03:24 -0700 From: Faizal Rahim To: Tony Nguyen , Przemek Kitszel , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vladimir Oltean Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Faizal Rahim , Chwee-Lin Choong Subject: [PATCH iwl-next v1 1/8] igc: move IGC_TXDCTL_QUEUE_ENABLE and IGC_TXDCTL_SWFLUSH Date: Mon, 28 Apr 2025 02:02:18 -0400 Message-Id: <20250428060225.1306986-2-faizal.abdul.rahim@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250428060225.1306986-1-faizal.abdul.rahim@linux.intel.com> References: <20250428060225.1306986-1-faizal.abdul.rahim@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Consolidate TXDCTL-related macros for better organization and readability. Signed-off-by: Faizal Rahim --- drivers/net/ethernet/intel/igc/igc.h | 6 ++++++ drivers/net/ethernet/intel/igc/igc_base.h | 4 ---- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/in= tel/igc/igc.h index 859a15e4ccba..e9d180eac015 100644 --- a/drivers/net/ethernet/intel/igc/igc.h +++ b/drivers/net/ethernet/intel/igc/igc.h @@ -492,6 +492,12 @@ static inline u32 igc_rss_type(const union igc_adv_rx_= desc *rx_desc) #define IGC_RX_WTHRESH 4 #define IGC_TX_WTHRESH 16 =20 +/* Additional Transmit Descriptor Control definitions */ +/* Ena specific Tx Queue */ +#define IGC_TXDCTL_QUEUE_ENABLE 0x02000000 +/* Transmit Software Flush */ +#define IGC_TXDCTL_SWFLUSH 0x04000000 + #define IGC_RX_DMA_ATTR \ (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) =20 diff --git a/drivers/net/ethernet/intel/igc/igc_base.h b/drivers/net/ethern= et/intel/igc/igc_base.h index 6320eabb72fe..4a56c634977b 100644 --- a/drivers/net/ethernet/intel/igc/igc_base.h +++ b/drivers/net/ethernet/intel/igc/igc_base.h @@ -86,10 +86,6 @@ union igc_adv_rx_desc { } wb; /* writeback */ }; =20 -/* Additional Transmit Descriptor Control definitions */ -#define IGC_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */ -#define IGC_TXDCTL_SWFLUSH 0x04000000 /* Transmit Software Flush */ - /* Additional Receive Descriptor Control definitions */ #define IGC_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */ #define IGC_RXDCTL_SWFLUSH 0x04000000 /* Receive Software Flush */ --=20 2.34.1 From nobody Sun Feb 8 05:43:19 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B7AD1CAA6E; Mon, 28 Apr 2025 06:03:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745820211; cv=none; b=MywTI6Tu4VZW2S7Nr7N6RATu4CeIVBYKg6IWQ1/wTjyz5WiaLP+OiCShrdov7ThapOzxt+3zFZlk6IvSVSVIVF6LBvonFxv/T7G0VndrJLzJFEqYf5H05BA6Z7jnVlBvsjHVLKPjqm5e18XUvkhITZL8PhPNtUzZZu/S7GCiPqo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745820211; c=relaxed/simple; bh=utJgU/4E0lRF86nAOgNjxmBrTEjRQTmBI49DKxLnVb0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=CihJbBZWoLtdnyz0oeSiTnOSglfeDnWH1bjt0pdmejSiizxY9QZcf+y9j+SzTUcXagBuysiAVtfmPNGwH7ofxZtNEDHSVBjCMTt9d0dNgVMOhz4nLcKrPsw/+xMBSXLEmv1Nrhxjiv20NWEqzaYjAANkaXG+zdL7yP2fnbeo8VE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=GP/w9fnr; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="GP/w9fnr" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1745820211; x=1777356211; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=utJgU/4E0lRF86nAOgNjxmBrTEjRQTmBI49DKxLnVb0=; b=GP/w9fnrOFpOFEAvgxy0yEvGMNp+qiQqvHnBzQvcPgR8onBxniv0V7So 8FsROgG4p8NfQoO1mCulj2n5fdrMrYGGsmIakxg2yag+bho3YTrhSjpWz M0GwhYsC+HLUCB5zC1EGtWeA4acFpLTjYw1r4vHOH9ciGchtj562yq+2i cJYUTGhJSwZCsP02ollY5qDrm9AHAzfngR2pY33nDAPPfATQULERu+1Ud 809B9Hg2GYgMyEc1asAcF4zb5d7WIJQ/0o/s+PVvrXBE46aZXxumY6Bsl zyEqpxxoy0ojoVbSuJqE7ciaD0cze+39CvZovxKfRu53SUDNU0BX3rMG1 w==; X-CSE-ConnectionGUID: IKcu9tqHSM6kSzH3An6kjQ== X-CSE-MsgGUID: jrMXmdgNR5WANJb1BxxuUg== X-IronPort-AV: E=McAfee;i="6700,10204,11416"; a="51064601" X-IronPort-AV: E=Sophos;i="6.15,245,1739865600"; d="scan'208";a="51064601" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2025 23:03:30 -0700 X-CSE-ConnectionGUID: r8L480b1Qx+M0KGADanF6A== X-CSE-MsgGUID: jQ1pQTfzS6mZjH6ajiiPyw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,245,1739865600"; d="scan'208";a="133340742" Received: from mohdfai2-ilbpg12-1.png.intel.com ([10.88.227.73]) by orviesa006.jf.intel.com with ESMTP; 27 Apr 2025 23:03:27 -0700 From: Faizal Rahim To: Tony Nguyen , Przemek Kitszel , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vladimir Oltean Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Faizal Rahim , Chwee-Lin Choong Subject: [PATCH iwl-next v1 2/8] igc: add TXDCTL prefix to related macros Date: Mon, 28 Apr 2025 02:02:19 -0400 Message-Id: <20250428060225.1306986-3-faizal.abdul.rahim@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250428060225.1306986-1-faizal.abdul.rahim@linux.intel.com> References: <20250428060225.1306986-1-faizal.abdul.rahim@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rename macros to include the TXDCTL_ prefix for consistency and clarity. This aligns naming with the register they configure and improves code readability. Signed-off-by: Faizal Rahim --- drivers/net/ethernet/intel/igc/igc.h | 6 +++--- drivers/net/ethernet/intel/igc/igc_main.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/in= tel/igc/igc.h index e9d180eac015..bc37cc8deefb 100644 --- a/drivers/net/ethernet/intel/igc/igc.h +++ b/drivers/net/ethernet/intel/igc/igc.h @@ -487,10 +487,10 @@ static inline u32 igc_rss_type(const union igc_adv_rx= _desc *rx_desc) */ #define IGC_RX_PTHRESH 8 #define IGC_RX_HTHRESH 8 -#define IGC_TX_PTHRESH 8 -#define IGC_TX_HTHRESH 1 +#define IGC_TXDCTL_PTHRESH 8 +#define IGC_TXDCTL_HTHRESH 1 #define IGC_RX_WTHRESH 4 -#define IGC_TX_WTHRESH 16 +#define IGC_TXDCTL_WTHRESH 16 =20 /* Additional Transmit Descriptor Control definitions */ /* Ena specific Tx Queue */ diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethern= et/intel/igc/igc_main.c index 27575a1e1777..725c8f0b9f3d 100644 --- a/drivers/net/ethernet/intel/igc/igc_main.c +++ b/drivers/net/ethernet/intel/igc/igc_main.c @@ -749,9 +749,9 @@ static void igc_configure_tx_ring(struct igc_adapter *a= dapter, wr32(IGC_TDH(reg_idx), 0); writel(0, ring->tail); =20 - txdctl |=3D IGC_TX_PTHRESH; - txdctl |=3D IGC_TX_HTHRESH << 8; - txdctl |=3D IGC_TX_WTHRESH << 16; + txdctl |=3D IGC_TXDCTL_PTHRESH; + txdctl |=3D IGC_TXDCTL_HTHRESH << 8; + txdctl |=3D IGC_TXDCTL_WTHRESH << 16; =20 txdctl |=3D IGC_TXDCTL_QUEUE_ENABLE; wr32(IGC_TXDCTL(reg_idx), txdctl); --=20 2.34.1 From nobody Sun Feb 8 05:43:19 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5143D1D54FE; Mon, 28 Apr 2025 06:03:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745820214; cv=none; b=CmiXY6gOeq+vGTAtXQxzM5DyLegmN4iUa45cf4W1mCtHnl4pZkf8yqJDAaZR5IDGXWIJRma7mXeK/INkWnN7LZq6z3lSRmyZoQyr/P2PNXnf2Vyb0p2oeJ452IV+t/DTtl4477PUYQYdUAxZAxL7L70fEEoKyomhfOOyM85grao= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745820214; c=relaxed/simple; bh=pS4q/Yjxbmtc0fCQ3ldogllC9oASKz4SUbDlI70Yroo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QPuFzs+D98kR/r422bebTdtFDDaCMUT/SMjHmZn/XSR6OM3na+NxMvjVftxO+66jqYWJizAKsLhVMSxdTJ+AsRHLvW5Wo01fbVGRsAqNuFpjWnc3pe3TpoTMos4ZFOuHczy9aYpKD2EGHaxiO/d4bt2XnUVtjBh5H2GQhZxeC2Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=cHxiehA+; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="cHxiehA+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1745820214; x=1777356214; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pS4q/Yjxbmtc0fCQ3ldogllC9oASKz4SUbDlI70Yroo=; b=cHxiehA+NYkhg0le5XKv1mlbs6jWeCUVuuigvTUf414bHgmddecU6CAi dDI5VqGRbOQyD1SHnBdeTKa0kJ1/EgkH9yv8Kfk8GXfQmSA7aoG7M7tHb l7aQuGeDQuj0/P3V7CYIyUSwdjs2cR3hbhL01R5aljiyru1zoo3zQXF/l edfS2F9b0pHQ1XifaDfs+kZcQnQgn5tbVsCWYksJjZUojy+RBiE+TN9Vu 2focc2rp3MYsCdVHkMNxUNrjSPzk9EvL1FuXlQppm8nizOS3XBbHHetdU n0ZIH24hcvIjAZt1hCEm0wMgtzK8eiTEEBzmayxxvntrDGMIy8ErE6r9x w==; X-CSE-ConnectionGUID: sR3zcGrnR++mCDBoQtM4Ew== X-CSE-MsgGUID: STHZL5aQTg2eY/a3AcectA== X-IronPort-AV: E=McAfee;i="6700,10204,11416"; a="51064613" X-IronPort-AV: E=Sophos;i="6.15,245,1739865600"; d="scan'208";a="51064613" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2025 23:03:34 -0700 X-CSE-ConnectionGUID: MNq7LqucQVCwYbZseCh3PQ== X-CSE-MsgGUID: kKBHL5XaQna9TZ6tL/LZEQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,245,1739865600"; d="scan'208";a="133340764" Received: from mohdfai2-ilbpg12-1.png.intel.com ([10.88.227.73]) by orviesa006.jf.intel.com with ESMTP; 27 Apr 2025 23:03:31 -0700 From: Faizal Rahim To: Tony Nguyen , Przemek Kitszel , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vladimir Oltean Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Faizal Rahim , Chwee-Lin Choong Subject: [PATCH iwl-next v1 3/8] igc: refactor TXDCTL macros to use FIELD_PREP and GEN_MASK Date: Mon, 28 Apr 2025 02:02:20 -0400 Message-Id: <20250428060225.1306986-4-faizal.abdul.rahim@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250428060225.1306986-1-faizal.abdul.rahim@linux.intel.com> References: <20250428060225.1306986-1-faizal.abdul.rahim@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refactor TXDCTL macro handling to use FIELD_PREP and GENMASK macros. This prepares the code for adding a new TXDCTL priority field in an upcoming patch. Signed-off-by: Faizal Rahim --- drivers/net/ethernet/intel/igc/igc.h | 16 +++++++++++----- drivers/net/ethernet/intel/igc/igc_main.c | 6 ++---- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/in= tel/igc/igc.h index bc37cc8deefb..4e44304b0608 100644 --- a/drivers/net/ethernet/intel/igc/igc.h +++ b/drivers/net/ethernet/intel/igc/igc.h @@ -487,16 +487,22 @@ static inline u32 igc_rss_type(const union igc_adv_rx= _desc *rx_desc) */ #define IGC_RX_PTHRESH 8 #define IGC_RX_HTHRESH 8 -#define IGC_TXDCTL_PTHRESH 8 -#define IGC_TXDCTL_HTHRESH 1 #define IGC_RX_WTHRESH 4 -#define IGC_TXDCTL_WTHRESH 16 =20 +#define IGC_TXDCTL_PTHRESH_MASK GENMASK(4, 0) +#define IGC_TXDCTL_HTHRESH_MASK GENMASK(12, 8) +#define IGC_TXDCTL_WTHRESH_MASK GENMASK(20, 16) +#define IGC_TXDCTL_QUEUE_ENABLE_MASK GENMASK(25, 25) +#define IGC_TXDCTL_SWFLUSH_MASK GENMASK(26, 26) + +#define IGC_TXDCTL_PTHRESH(x) FIELD_PREP(IGC_TXDCTL_PTHRESH_MASK, (x)) +#define IGC_TXDCTL_HTHRESH(x) FIELD_PREP(IGC_TXDCTL_HTHRESH_MASK, (x)) +#define IGC_TXDCTL_WTHRESH(x) FIELD_PREP(IGC_TXDCTL_WTHRESH_MASK, (x)) /* Additional Transmit Descriptor Control definitions */ /* Ena specific Tx Queue */ -#define IGC_TXDCTL_QUEUE_ENABLE 0x02000000 +#define IGC_TXDCTL_QUEUE_ENABLE FIELD_PREP(IGC_TXDCTL_QUEUE_ENABLE_MASK, = 1) /* Transmit Software Flush */ -#define IGC_TXDCTL_SWFLUSH 0x04000000 +#define IGC_TXDCTL_SWFLUSH FIELD_PREP(IGC_TXDCTL_SWFLUSH_MASK, 1) =20 #define IGC_RX_DMA_ATTR \ (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethern= et/intel/igc/igc_main.c index 725c8f0b9f3d..86716fabf6a9 100644 --- a/drivers/net/ethernet/intel/igc/igc_main.c +++ b/drivers/net/ethernet/intel/igc/igc_main.c @@ -749,11 +749,9 @@ static void igc_configure_tx_ring(struct igc_adapter *= adapter, wr32(IGC_TDH(reg_idx), 0); writel(0, ring->tail); =20 - txdctl |=3D IGC_TXDCTL_PTHRESH; - txdctl |=3D IGC_TXDCTL_HTHRESH << 8; - txdctl |=3D IGC_TXDCTL_WTHRESH << 16; + txdctl |=3D IGC_TXDCTL_PTHRESH(8) | IGC_TXDCTL_HTHRESH(1) | + IGC_TXDCTL_WTHRESH(16) | IGC_TXDCTL_QUEUE_ENABLE; =20 - txdctl |=3D IGC_TXDCTL_QUEUE_ENABLE; wr32(IGC_TXDCTL(reg_idx), txdctl); } =20 --=20 2.34.1 From nobody Sun Feb 8 05:43:19 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C0E329CEB; Mon, 28 Apr 2025 06:03:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745820218; cv=none; b=JJBDLiCT/9Oy6UwWtYrag4s314DPpUI1GInm1+frySnoMPRVD0jzwd+1JeZxMlxrEEqWvehXfY9x9hpXZ5OFgMv2zJqBIGLCBUHC/4cYozyL6XDBfi9V58eU13bXusqTnGquuMhIuzDWm0VKMEdyTYewx/tmB1NvRKYXiYEakoA= ARC-Message-Signature: i=1; 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d="scan'208";a="133340787" Received: from mohdfai2-ilbpg12-1.png.intel.com ([10.88.227.73]) by orviesa006.jf.intel.com with ESMTP; 27 Apr 2025 23:03:34 -0700 From: Faizal Rahim To: Tony Nguyen , Przemek Kitszel , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vladimir Oltean Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Faizal Rahim , Chwee-Lin Choong Subject: [PATCH iwl-next v1 4/8] igc: assign highest TX queue number as highest priority in mqprio Date: Mon, 28 Apr 2025 02:02:21 -0400 Message-Id: <20250428060225.1306986-5-faizal.abdul.rahim@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250428060225.1306986-1-faizal.abdul.rahim@linux.intel.com> References: <20250428060225.1306986-1-faizal.abdul.rahim@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Previously, TX arbitration prioritized queues based on the TC they were mapped to. A queue mapped to TC 3 had higher priority than one mapped to TC 0. To improve code reuse for upcoming patches and align with typical NIC behavior, this patch updates the logic to prioritize higher queue numbers when mqprio is used. As a result, queue 0 becomes the lowest priority and queue 3 becomes the highest. This patch also introduces igc_tsn_is_tc_to_queue_priority_ordered() to preserve the original TC-based priority rule and reject configurations where a higher TC maps to a lower queue offset. Signed-off-by: Faizal Rahim --- drivers/net/ethernet/intel/igc/igc_main.c | 19 ++++++++++++ drivers/net/ethernet/intel/igc/igc_tsn.c | 35 ++++++++++++++--------- 2 files changed, 41 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethern= et/intel/igc/igc_main.c index 86716fabf6a9..1b58811f8cfa 100644 --- a/drivers/net/ethernet/intel/igc/igc_main.c +++ b/drivers/net/ethernet/intel/igc/igc_main.c @@ -6724,6 +6724,19 @@ static void igc_save_mqprio_params(struct igc_adapte= r *adapter, u8 num_tc, adapter->queue_per_tc[i] =3D offset[i]; } =20 +static bool igc_tsn_is_tc_to_queue_priority_ordered(struct tc_mqprio_qopt_= offload *mqprio) +{ + int i; + int num_tc =3D mqprio->qopt.num_tc; + + for (i =3D 1; i < num_tc; i++) { + if (mqprio->qopt.offset[i - 1] > mqprio->qopt.offset[i]) + return false; + } + + return true; +} + static int igc_tsn_enable_mqprio(struct igc_adapter *adapter, struct tc_mqprio_qopt_offload *mqprio) { @@ -6756,6 +6769,12 @@ static int igc_tsn_enable_mqprio(struct igc_adapter = *adapter, } } =20 + if (!igc_tsn_is_tc_to_queue_priority_ordered(mqprio)) { + NL_SET_ERR_MSG_MOD(mqprio->extack, + "tc to queue mapping must preserve increasing priority (higher tc = =E2=86=92 higher queue)"); + return -EOPNOTSUPP; + } + /* Preemption is not supported yet. */ if (mqprio->preemptible_tcs) { NL_SET_ERR_MSG_MOD(mqprio->extack, diff --git a/drivers/net/ethernet/intel/igc/igc_tsn.c b/drivers/net/etherne= t/intel/igc/igc_tsn.c index e964b11feab1..e1e1c5c89989 100644 --- a/drivers/net/ethernet/intel/igc/igc_tsn.c +++ b/drivers/net/ethernet/intel/igc/igc_tsn.c @@ -12,6 +12,13 @@ #define TX_MIN_FRAG_SIZE 64 #define TX_MAX_FRAG_SIZE (TX_MIN_FRAG_SIZE * (MAX_MULTPLIER_TX_MIN_FRAG + = 1)) =20 +enum tx_queue { + TX_QUEUE_0 =3D 0, + TX_QUEUE_1, + TX_QUEUE_2, + TX_QUEUE_3, +}; + DEFINE_STATIC_KEY_FALSE(igc_fpe_enabled); =20 static int igc_fpe_init_smd_frame(struct igc_ring *ring, @@ -236,7 +243,7 @@ bool igc_tsn_is_taprio_activated_by_user(struct igc_ada= pter *adapter) adapter->taprio_offload_enable; } =20 -static void igc_tsn_tx_arb(struct igc_adapter *adapter, u16 *queue_per_tc) +static void igc_tsn_tx_arb(struct igc_adapter *adapter, bool reverse_prio) { struct igc_hw *hw =3D &adapter->hw; u32 txarb; @@ -248,10 +255,17 @@ static void igc_tsn_tx_arb(struct igc_adapter *adapte= r, u16 *queue_per_tc) IGC_TXARB_TXQ_PRIO_2_MASK | IGC_TXARB_TXQ_PRIO_3_MASK); =20 - txarb |=3D IGC_TXARB_TXQ_PRIO_0(queue_per_tc[3]); - txarb |=3D IGC_TXARB_TXQ_PRIO_1(queue_per_tc[2]); - txarb |=3D IGC_TXARB_TXQ_PRIO_2(queue_per_tc[1]); - txarb |=3D IGC_TXARB_TXQ_PRIO_3(queue_per_tc[0]); + if (reverse_prio) { + txarb |=3D IGC_TXARB_TXQ_PRIO_0(TX_QUEUE_3); + txarb |=3D IGC_TXARB_TXQ_PRIO_1(TX_QUEUE_2); + txarb |=3D IGC_TXARB_TXQ_PRIO_2(TX_QUEUE_1); + txarb |=3D IGC_TXARB_TXQ_PRIO_3(TX_QUEUE_0); + } else { + txarb |=3D IGC_TXARB_TXQ_PRIO_0(TX_QUEUE_0); + txarb |=3D IGC_TXARB_TXQ_PRIO_1(TX_QUEUE_1); + txarb |=3D IGC_TXARB_TXQ_PRIO_2(TX_QUEUE_2); + txarb |=3D IGC_TXARB_TXQ_PRIO_3(TX_QUEUE_3); + } =20 wr32(IGC_TXARB, txarb); } @@ -282,7 +296,6 @@ static void igc_tsn_set_rxpbsize(struct igc_adapter *ad= apter, u32 rxpbs_exp_bmc_ */ static int igc_tsn_disable_offload(struct igc_adapter *adapter) { - u16 queue_per_tc[4] =3D { 3, 2, 1, 0 }; struct igc_hw *hw =3D &adapter->hw; u32 tqavctrl; int i; @@ -315,7 +328,7 @@ static int igc_tsn_disable_offload(struct igc_adapter *= adapter) /* Restore the default Tx arbitration: Priority 0 has the highest * priority and is assigned to queue 0 and so on and so forth. */ - igc_tsn_tx_arb(adapter, queue_per_tc); + igc_tsn_tx_arb(adapter, false); =20 adapter->flags &=3D ~IGC_FLAG_TSN_QBV_ENABLED; =20 @@ -381,12 +394,8 @@ static int igc_tsn_enable_offload(struct igc_adapter *= adapter) if (igc_is_device_id_i226(hw)) igc_tsn_set_retx_qbvfullthreshold(adapter); =20 - if (adapter->strict_priority_enable) { - /* Configure queue priorities according to the user provided - * mapping. - */ - igc_tsn_tx_arb(adapter, adapter->queue_per_tc); - } + if (adapter->strict_priority_enable) + igc_tsn_tx_arb(adapter, true); =20 for (i =3D 0; i < adapter->num_tx_queues; i++) { struct igc_ring *ring =3D adapter->tx_ring[i]; --=20 2.34.1 From nobody Sun Feb 8 05:43:19 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 814691C1F13; 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X-CSE-ConnectionGUID: c8V/5TnJTkGr7GLz44zXsw== X-CSE-MsgGUID: YLytroW7RfOEskEsEb+OgA== X-IronPort-AV: E=McAfee;i="6700,10204,11416"; a="51064641" X-IronPort-AV: E=Sophos;i="6.15,245,1739865600"; d="scan'208";a="51064641" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2025 23:03:41 -0700 X-CSE-ConnectionGUID: r/xWXEzaRI+hB3417ii/DQ== X-CSE-MsgGUID: k9htWCBhTZ247V5aEhM4aA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,245,1739865600"; d="scan'208";a="133340810" Received: from mohdfai2-ilbpg12-1.png.intel.com ([10.88.227.73]) by orviesa006.jf.intel.com with ESMTP; 27 Apr 2025 23:03:37 -0700 From: Faizal Rahim To: Tony Nguyen , Przemek Kitszel , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vladimir Oltean Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Faizal Rahim , Chwee-Lin Choong Subject: [PATCH iwl-next v1 5/8] igc: add private flag to reverse TX queue priority in TSN mode Date: Mon, 28 Apr 2025 02:02:22 -0400 Message-Id: <20250428060225.1306986-6-faizal.abdul.rahim@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250428060225.1306986-1-faizal.abdul.rahim@linux.intel.com> References: <20250428060225.1306986-1-faizal.abdul.rahim@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable By default, igc assigns TX hw queue 0 the highest priority and queue 3 the lowest. This is opposite of most NICs, where TX hw queue 3 has the highest priority and queue 0 the lowest. mqprio in igc already uses TX arbitration unconditionally to reverse TX queue priority when mqprio is enabled. The TX arbitration logic does not require a private flag, because mqprio was added recently and no known users depend on the default queue ordering, which differs from the typical convention. taprio does not use TX arbitration, so it inherits the default igc TX queue priority order. This causes tc command inconsistencies when configuring frame preemption with taprio compared to mqprio in igc. Other tc command inconsistencies and configuration issues already exist when using taprio on igc compared to other network controllers. These issues are described in a later section. To harmonize TX queue priority behavior between taprio and mqprio, and to fix these issues without breaking long-standing taprio use cases, this patch adds a new private flag, called reverse-tsn-txq-prio, to reverse the TX queue priority. It makes queue 3 the highest and queue 0 the lowest, reusing the TX arbitration logic already used by mqprio. Users must set the private flag when enabling frame preemption with taprio to follow the standard convention. Doing so promotes adoption of the correct priority model for new features while preserving compatibility with legacy configurations. This new private flag addresses: 1. Non-standard socket =E2=86=92 tc =E2=86=92 TX hw queue mapping for tapr= io in igc Without the private flag: - taprio maps (socket =E2=86=92 tc =E2=86=92 TX hardware queue) differently= on igc compared to other network controllers - On igc, mqprio maps tc differently from taprio, since mqprio already uses TX arbitration The following examples compare taprio configuration on igc and other network controllers: a) On other NICs (TX hw queue 3 is highest priority): taprio num_tc 4 map 0 1 2 3 .... \ queues 1@0 1@1 1@2 1@3 Mapping translates to: socket 0 =E2=86=92 tc 0 =E2=86=92 queue 0 socket 3 =E2=86=92 tc 3 =E2=86=92 queue 3 This is the normal mapping that respects the standard convention: higher socket number =E2=86=92 higher tc -> higher priority TX hw queue b) On igc (TX hw queue 0 is highest priority by default): taprio num_tc 4 map 3 2 1 0 .... \ queues 1@0 1@1 1@2 1@3 Mapping translates to: socket 0 =E2=86=92 tc 3 =E2=86=92 queue 3 socket 3 =E2=86=92 tc 0 =E2=86=92 queue 0 This igc tc mapping example is based on Intel's TSN validation test case, where a higher socket priority maps to a higher priority queue. It respects the mapping: higher socket number -> higher priority TX hw queue but breaks the expected ordering: higher tc -> higher priority TX hw queue as defined in [Ref1]. This custom mapping complicates common taprio setup across NICs. 2. Non-standard frame preemption mapping for taprio in igc Without the private flag: - Compared to other network controllers, taprio on igc must flip the expected fp sequence, since express traffic is expected to map to the highest priority queue and preemptible traffic to lower ones - On igc, frame preemption configuration for mqprio differs from taprio, since mqprio already uses TX arbitration The following examples compare taprio frame preemption configuration on igc and other network controllers: a) On other NICs (TX hw queue 3 is highest priority): taprio num_tc 4 map ..... \ queues 1@0 1@1 1@2 1@3 \ fp P P P E Mapping translates to: tc0, tc1, tc2 =E2=86=92 preemptible =E2=86=92 queue 0, 1, 2 tc3 =E2=86=92 express =E2=86=92 queue 3 This is the normal mapping that respects the standard convention: higher tc -> express traffic -> higher priority TX hw queue lower tc -> preemptible traffic -> lower priority TX hw queue b) On igc (TX hw queue 0 is highest priority by default): taprio num_tc 4 map ...... \ queues 1@0 1@1 1@2 1@3 \ fp E P P P Mapping translates to: tc0 =E2=86=92 express =E2=86=92 queue 0 tc1, tc2, tc3 =E2=86=92 preemptible =E2=86=92 queue 1, 2, 3 This inversion respects the mapping of: express traffic -> higher priority TX hw queue but breaks the expected ordering: higher tc -> express traffic as defined in [Ref1] where higher tc indicates higher priority. In this case, the lower tc0 is assigned to express traffic. This custom mapping further complicates common preemption setup across NICs. 3. LaunchTime + XDP queue priority issue on igc (reported by Siemens) XDP requires RX and TX to share the same queue. When XDP uses queue 0, which has the highest TX priority, best-effort packets that do not match any RX filter also end up on RX queue 0. This is because queue 0 is the default for packets that do not match any RX filter. This leads to unexpected interference with real-time applications that process traffic on queue 0. Reversing the TX queue priority allows assigning XDP to queue 3 instead, which isolates real-time traffic from best-effort packets. Tests were performed on taprio with the following combinations, where two apps send traffic simultaneously on different queues: Private Flag Traffic Sent By Traffic Sent By ---------------------------------------------------------------- enabled iperf3 (queue 3) iperf3 (queue 0) disabled iperf3 (queue 0) iperf3 (queue 3) enabled iperf3 (queue 3) real-time app (queue 0) disabled iperf3 (queue 0) real-time app (queue 3) enabled real-time app (queue 3) iperf3 (queue 0) disabled real-time app (queue 0) iperf3 (queue 3) enabled real-time app (queue 3) real-time app (queue 0) disabled real-time app (queue 0) real-time app (queue 3) Private flag is controlled with: ethtool --set-priv-flags enp1s0 reverse-tsn-txq-prio [Ref1] IEEE 802.1Q clause 8.6.8 Transmission selection: "For a given Port and traffic class, frames are selected from the corresponding queue for transmission if and only if: ... b) For each queue corresponding to a numerically higher value of traffic class supported by the Port, the operation of the transmission selection algorithm supported by that queue determines that there is no frame available for transmission." Signed-off-by: Faizal Rahim --- drivers/net/ethernet/intel/igc/igc.h | 1 + drivers/net/ethernet/intel/igc/igc_ethtool.c | 12 ++++++++++-- drivers/net/ethernet/intel/igc/igc_main.c | 3 ++- drivers/net/ethernet/intel/igc/igc_tsn.c | 3 ++- 4 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/in= tel/igc/igc.h index 4e44304b0608..684a11df445c 100644 --- a/drivers/net/ethernet/intel/igc/igc.h +++ b/drivers/net/ethernet/intel/igc/igc.h @@ -395,6 +395,7 @@ extern char igc_driver_name[]; #define IGC_FLAG_TSN_QBV_ENABLED BIT(17) #define IGC_FLAG_TSN_QAV_ENABLED BIT(18) #define IGC_FLAG_TSN_PREEMPT_ENABLED BIT(19) +#define IGC_FLAG_TSN_REVERSE_TXQ_PRIO BIT(20) =20 #define IGC_FLAG_TSN_ANY_ENABLED \ (IGC_FLAG_TSN_QBV_ENABLED | IGC_FLAG_TSN_QAV_ENABLED | \ diff --git a/drivers/net/ethernet/intel/igc/igc_ethtool.c b/drivers/net/eth= ernet/intel/igc/igc_ethtool.c index 324a27a5bef9..8e9827e62a86 100644 --- a/drivers/net/ethernet/intel/igc/igc_ethtool.c +++ b/drivers/net/ethernet/intel/igc/igc_ethtool.c @@ -122,9 +122,11 @@ static const char igc_gstrings_test[][ETH_GSTRING_LEN]= =3D { #define IGC_STATS_LEN \ (IGC_GLOBAL_STATS_LEN + IGC_NETDEV_STATS_LEN + IGC_QUEUE_STATS_LEN) =20 +#define IGC_PRIV_FLAGS_LEGACY_RX BIT(0) +#define IGC_PRIV_FLAGS_REVERSE_TSN_TXQ_PRIO BIT(1) static const char igc_priv_flags_strings[][ETH_GSTRING_LEN] =3D { -#define IGC_PRIV_FLAGS_LEGACY_RX BIT(0) "legacy-rx", + "reverse-tsn-txq-prio", }; =20 #define IGC_PRIV_FLAGS_STR_LEN ARRAY_SIZE(igc_priv_flags_strings) @@ -1600,6 +1602,9 @@ static u32 igc_ethtool_get_priv_flags(struct net_devi= ce *netdev) if (adapter->flags & IGC_FLAG_RX_LEGACY) priv_flags |=3D IGC_PRIV_FLAGS_LEGACY_RX; =20 + if (adapter->flags & IGC_FLAG_TSN_REVERSE_TXQ_PRIO) + priv_flags |=3D IGC_PRIV_FLAGS_REVERSE_TSN_TXQ_PRIO; + return priv_flags; } =20 @@ -1608,10 +1613,13 @@ static int igc_ethtool_set_priv_flags(struct net_de= vice *netdev, u32 priv_flags) struct igc_adapter *adapter =3D netdev_priv(netdev); unsigned int flags =3D adapter->flags; =20 - flags &=3D ~IGC_FLAG_RX_LEGACY; + flags &=3D ~(IGC_FLAG_RX_LEGACY | IGC_FLAG_TSN_REVERSE_TXQ_PRIO); if (priv_flags & IGC_PRIV_FLAGS_LEGACY_RX) flags |=3D IGC_FLAG_RX_LEGACY; =20 + if (priv_flags & IGC_PRIV_FLAGS_REVERSE_TSN_TXQ_PRIO) + flags |=3D IGC_FLAG_TSN_REVERSE_TXQ_PRIO; + if (flags !=3D adapter->flags) { adapter->flags =3D flags; =20 diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethern= et/intel/igc/igc_main.c index 1b58811f8cfa..8562565842b1 100644 --- a/drivers/net/ethernet/intel/igc/igc_main.c +++ b/drivers/net/ethernet/intel/igc/igc_main.c @@ -6698,7 +6698,8 @@ static int igc_tc_query_caps(struct igc_adapter *adap= ter, case TC_SETUP_QDISC_TAPRIO: { struct tc_taprio_caps *caps =3D base->caps; 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X-CSE-ConnectionGUID: AIHdbKbGQFyVOdJJUSiWrA== X-CSE-MsgGUID: TusCd+FzTmKaiYL86z/uFQ== X-IronPort-AV: E=McAfee;i="6700,10204,11416"; a="51064648" X-IronPort-AV: E=Sophos;i="6.15,245,1739865600"; d="scan'208";a="51064648" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2025 23:03:44 -0700 X-CSE-ConnectionGUID: S+TFwbhzSx2Y8XF6osNaSw== X-CSE-MsgGUID: cJx9j4iyRhGf1vlemeMyWQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,245,1739865600"; d="scan'208";a="133340830" Received: from mohdfai2-ilbpg12-1.png.intel.com ([10.88.227.73]) by orviesa006.jf.intel.com with ESMTP; 27 Apr 2025 23:03:41 -0700 From: Faizal Rahim To: Tony Nguyen , Przemek Kitszel , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vladimir Oltean Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Faizal Rahim , Chwee-Lin Choong Subject: [PATCH iwl-next v1 6/8] igc: add preemptible queue support in taprio Date: Mon, 28 Apr 2025 02:02:23 -0400 Message-Id: <20250428060225.1306986-7-faizal.abdul.rahim@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250428060225.1306986-1-faizal.abdul.rahim@linux.intel.com> References: <20250428060225.1306986-1-faizal.abdul.rahim@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" igc already supports enabling MAC Merge for FPE. This patch adds support for preemptible queues in taprio. Changes: 1. Introduce tx_enabled flag to control preemptible queue. tx_enabled is set via mmsv module based on multiple factors, including link up/down status, to determine if FPE is active or inactive. 2. Add priority field to TXDCTL for express queue to improve data fetch performance. 3. Block preemptible queue setup in taprio unless reverse-tsn-txq-prio private flag is set. Encourages adoption of standard queue priority scheme for new features. Tested preemption with taprio by: 1. Enable FPE: ethtool --set-mm enp1s0 pmac-enabled on tx-enabled on verify-enabled on 2. Enable private flag to reverse TX queue priority: ethtool --set-priv-flags enp1s0 reverse-txq-prio on 3. Enable preemptible queue in taprio: taprio num_tc 4 map 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 \ queues 1@0 1@1 1@2 1@3 \ fp P P P E Signed-off-by: Faizal Rahim Reviewed-by: Aleksandr Loktionov --- drivers/net/ethernet/intel/igc/igc.h | 5 ++ drivers/net/ethernet/intel/igc/igc_defines.h | 1 + drivers/net/ethernet/intel/igc/igc_main.c | 12 +++- drivers/net/ethernet/intel/igc/igc_tsn.c | 71 ++++++++++++++++++++ drivers/net/ethernet/intel/igc/igc_tsn.h | 4 ++ 5 files changed, 90 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/in= tel/igc/igc.h index 684a11df445c..39444e61003d 100644 --- a/drivers/net/ethernet/intel/igc/igc.h +++ b/drivers/net/ethernet/intel/igc/igc.h @@ -43,6 +43,7 @@ void igc_ethtool_set_ops(struct net_device *); struct igc_fpe_t { struct ethtool_mmsv mmsv; u32 tx_min_frag_size; + bool tx_enabled; }; =20 enum igc_mac_filter_type { @@ -163,6 +164,7 @@ struct igc_ring { bool launchtime_enable; /* true if LaunchTime is enabled */ ktime_t last_tx_cycle; /* end of the cycle with a launchtime tra= nsmission */ ktime_t last_ff_cycle; /* Last cycle with an active first flag */ + bool preemptible; /* True if preemptible queue, false if express queue */ =20 u32 start_time; u32 end_time; @@ -495,6 +497,7 @@ static inline u32 igc_rss_type(const union igc_adv_rx_d= esc *rx_desc) #define IGC_TXDCTL_WTHRESH_MASK GENMASK(20, 16) #define IGC_TXDCTL_QUEUE_ENABLE_MASK GENMASK(25, 25) #define IGC_TXDCTL_SWFLUSH_MASK GENMASK(26, 26) +#define IGC_TXDCTL_PRIORITY_MASK GENMASK(27, 27) =20 #define IGC_TXDCTL_PTHRESH(x) FIELD_PREP(IGC_TXDCTL_PTHRESH_MASK, (x)) #define IGC_TXDCTL_HTHRESH(x) FIELD_PREP(IGC_TXDCTL_HTHRESH_MASK, (x)) @@ -504,6 +507,8 @@ static inline u32 igc_rss_type(const union igc_adv_rx_d= esc *rx_desc) #define IGC_TXDCTL_QUEUE_ENABLE FIELD_PREP(IGC_TXDCTL_QUEUE_ENABLE_MASK, = 1) /* Transmit Software Flush */ #define IGC_TXDCTL_SWFLUSH FIELD_PREP(IGC_TXDCTL_SWFLUSH_MASK, 1) +#define IGC_TXDCTL_PRIORITY(x) FIELD_PREP(IGC_TXDCTL_PRIORITY_MASK, (x)) +#define IGC_TXDCTL_PRIORITY_HIGH IGC_TXDCTL_PRIORITY(1) =20 #define IGC_RX_DMA_ATTR \ (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) diff --git a/drivers/net/ethernet/intel/igc/igc_defines.h b/drivers/net/eth= ernet/intel/igc/igc_defines.h index 7189dfc389ad..86b346687196 100644 --- a/drivers/net/ethernet/intel/igc/igc_defines.h +++ b/drivers/net/ethernet/intel/igc/igc_defines.h @@ -588,6 +588,7 @@ #define IGC_TXQCTL_QUEUE_MODE_LAUNCHT 0x00000001 #define IGC_TXQCTL_STRICT_CYCLE 0x00000002 #define IGC_TXQCTL_STRICT_END 0x00000004 +#define IGC_TXQCTL_PREEMPTIBLE 0x00000008 #define IGC_TXQCTL_QAV_SEL_MASK 0x000000C0 #define IGC_TXQCTL_QAV_SEL_CBS0 0x00000080 #define IGC_TXQCTL_QAV_SEL_CBS1 0x000000C0 diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethern= et/intel/igc/igc_main.c index 8562565842b1..c6e2cfd630df 100644 --- a/drivers/net/ethernet/intel/igc/igc_main.c +++ b/drivers/net/ethernet/intel/igc/igc_main.c @@ -6419,6 +6419,7 @@ static int igc_qbv_clear_schedule(struct igc_adapter = *adapter) ring->start_time =3D 0; ring->end_time =3D NSEC_PER_SEC; ring->max_sdu =3D 0; + ring->preemptible =3D false; } =20 spin_lock_irqsave(&adapter->qbv_tx_lock, flags); @@ -6484,9 +6485,12 @@ static int igc_save_qbv_schedule(struct igc_adapter = *adapter, if (!validate_schedule(adapter, qopt)) return -EINVAL; =20 - /* preemptible isn't supported yet */ - if (qopt->mqprio.preemptible_tcs) - return -EOPNOTSUPP; + if (qopt->mqprio.preemptible_tcs && + !(adapter->flags & IGC_FLAG_TSN_REVERSE_TXQ_PRIO)) { + NL_SET_ERR_MSG_MOD(qopt->extack, + "reverse-tsn-txq-prio private flag must be enabled before setting p= reemptible tc"); + return -ENODEV; + } =20 igc_ptp_read(adapter, &now); =20 @@ -6579,6 +6583,8 @@ static int igc_save_qbv_schedule(struct igc_adapter *= adapter, ring->max_sdu =3D 0; } =20 + igc_fpe_save_preempt_queue(adapter, &qopt->mqprio); + return 0; } =20 diff --git a/drivers/net/ethernet/intel/igc/igc_tsn.c b/drivers/net/etherne= t/intel/igc/igc_tsn.c index 5dc05b42f53f..897813eb2175 100644 --- a/drivers/net/ethernet/intel/igc/igc_tsn.c +++ b/drivers/net/ethernet/intel/igc/igc_tsn.c @@ -115,6 +115,18 @@ static int igc_fpe_xmit_smd_frame(struct igc_adapter *= adapter, return err; } =20 +static void igc_fpe_configure_tx(struct ethtool_mmsv *mmsv, bool tx_enable) +{ + struct igc_fpe_t *fpe =3D container_of(mmsv, struct igc_fpe_t, mmsv); + struct igc_adapter *adapter; + + adapter =3D container_of(fpe, struct igc_adapter, fpe); + adapter->fpe.tx_enabled =3D tx_enable; + + /* Update config since tx_enabled affects preemptible queue configuration= */ + igc_tsn_offload_apply(adapter); +} + static void igc_fpe_send_mpacket(struct ethtool_mmsv *mmsv, enum ethtool_mpacket type) { @@ -136,15 +148,50 @@ static void igc_fpe_send_mpacket(struct ethtool_mmsv = *mmsv, } =20 static const struct ethtool_mmsv_ops igc_mmsv_ops =3D { + .configure_tx =3D igc_fpe_configure_tx, .send_mpacket =3D igc_fpe_send_mpacket, }; =20 void igc_fpe_init(struct igc_adapter *adapter) { adapter->fpe.tx_min_frag_size =3D TX_MIN_FRAG_SIZE; + adapter->fpe.tx_enabled =3D false; ethtool_mmsv_init(&adapter->fpe.mmsv, adapter->netdev, &igc_mmsv_ops); } =20 +static u32 igc_fpe_map_preempt_tc_to_queue(const struct igc_adapter *adapt= er, + unsigned long preemptible_tcs) +{ + struct net_device *dev =3D adapter->netdev; + u32 i, queue =3D 0; + + for (i =3D 0; i < dev->num_tc; i++) { + u32 offset, count; + + if (!(preemptible_tcs & BIT(i))) + continue; + + offset =3D dev->tc_to_txq[i].offset; + count =3D dev->tc_to_txq[i].count; + queue |=3D GENMASK(offset + count - 1, offset); + } + + return queue; +} + +void igc_fpe_save_preempt_queue(struct igc_adapter *adapter, + const struct tc_mqprio_qopt_offload *mqprio) +{ + u32 preemptible_queue =3D igc_fpe_map_preempt_tc_to_queue(adapter, + mqprio->preemptible_tcs); + + for (int i =3D 0; i < adapter->num_tx_queues; i++) { + struct igc_ring *tx_ring =3D adapter->tx_ring[i]; + + tx_ring->preemptible =3D !!(preemptible_queue & BIT(i)); + } +} + static bool is_any_launchtime(struct igc_adapter *adapter) { int i; @@ -317,9 +364,16 @@ static int igc_tsn_disable_offload(struct igc_adapter = *adapter) wr32(IGC_TQAVCTRL, tqavctrl); =20 for (i =3D 0; i < adapter->num_tx_queues; i++) { + int reg_idx =3D adapter->tx_ring[i]->reg_idx; + u32 txdctl; + wr32(IGC_TXQCTL(i), 0); wr32(IGC_STQT(i), 0); wr32(IGC_ENDQT(i), NSEC_PER_SEC); + + txdctl =3D rd32(IGC_TXDCTL(reg_idx)); + txdctl &=3D ~IGC_TXDCTL_PRIORITY_HIGH; + wr32(IGC_TXDCTL(reg_idx), txdctl); } =20 wr32(IGC_QBVCYCLET_S, 0); @@ -400,6 +454,7 @@ static int igc_tsn_enable_offload(struct igc_adapter *a= dapter) =20 for (i =3D 0; i < adapter->num_tx_queues; i++) { struct igc_ring *ring =3D adapter->tx_ring[i]; + u32 txdctl =3D rd32(IGC_TXDCTL(ring->reg_idx)); u32 txqctl =3D 0; u16 cbs_value; u32 tqavcc; @@ -433,6 +488,22 @@ static int igc_tsn_enable_offload(struct igc_adapter *= adapter) if (ring->launchtime_enable) txqctl |=3D IGC_TXQCTL_QUEUE_MODE_LAUNCHT; =20 + if (!adapter->fpe.tx_enabled) { + /* fpe inactive: clear both flags */ + txqctl &=3D ~IGC_TXQCTL_PREEMPTIBLE; + txdctl &=3D ~IGC_TXDCTL_PRIORITY_HIGH; + } else if (ring->preemptible) { + /* fpe active + preemptible: enable preemptible queue + set low priorit= y */ + txqctl |=3D IGC_TXQCTL_PREEMPTIBLE; + txdctl &=3D ~IGC_TXDCTL_PRIORITY_HIGH; + } else { + /* fpe active + express: enable express queue + set high priority */ + txqctl &=3D ~IGC_TXQCTL_PREEMPTIBLE; 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X-CSE-ConnectionGUID: mPQrC9usT4GNTjiWUvpEeA== X-CSE-MsgGUID: 0ybPELGTSaG14HsOvKCRkw== X-IronPort-AV: E=McAfee;i="6700,10204,11416"; a="51064657" X-IronPort-AV: E=Sophos;i="6.15,245,1739865600"; d="scan'208";a="51064657" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2025 23:03:49 -0700 X-CSE-ConnectionGUID: F7tjRAGxQDiikAtPK2RcmA== X-CSE-MsgGUID: y568pPn3TvKc3yU2DWeY7w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,245,1739865600"; d="scan'208";a="133340843" Received: from mohdfai2-ilbpg12-1.png.intel.com ([10.88.227.73]) by orviesa006.jf.intel.com with ESMTP; 27 Apr 2025 23:03:45 -0700 From: Faizal Rahim To: Tony Nguyen , Przemek Kitszel , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vladimir Oltean Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Faizal Rahim , Chwee-Lin Choong Subject: [PATCH iwl-next v1 7/8] igc: add preemptible queue support in mqprio Date: Mon, 28 Apr 2025 02:02:24 -0400 Message-Id: <20250428060225.1306986-8-faizal.abdul.rahim@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250428060225.1306986-1-faizal.abdul.rahim@linux.intel.com> References: <20250428060225.1306986-1-faizal.abdul.rahim@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" igc already supports enabling MAC Merge for FPE. This patch adds support for preemptible queues in mqprio. Tested preemption with mqprio by: 1. Enable FPE: ethtool --set-mm enp1s0 pmac-enabled on tx-enabled on verify-enabled on 2. Enable preemptible queue in mqprio: mqprio num_tc 4 map 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 \ queues 1@0 1@1 1@2 1@3 \ fp P P P E Signed-off-by: Faizal Rahim --- drivers/net/ethernet/intel/igc/igc_main.c | 9 ++------- drivers/net/ethernet/intel/igc/igc_tsn.c | 9 +++++++++ drivers/net/ethernet/intel/igc/igc_tsn.h | 1 + 3 files changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethern= et/intel/igc/igc_main.c index c6e2cfd630df..6b14b0d165f0 100644 --- a/drivers/net/ethernet/intel/igc/igc_main.c +++ b/drivers/net/ethernet/intel/igc/igc_main.c @@ -6755,6 +6755,7 @@ static int igc_tsn_enable_mqprio(struct igc_adapter *= adapter, =20 if (!mqprio->qopt.num_tc) { adapter->strict_priority_enable =3D false; + igc_fpe_clear_preempt_queue(adapter); netdev_reset_tc(adapter->netdev); goto apply; } @@ -6782,13 +6783,6 @@ static int igc_tsn_enable_mqprio(struct igc_adapter = *adapter, return -EOPNOTSUPP; } =20 - /* Preemption is not supported yet. */ - if (mqprio->preemptible_tcs) { - NL_SET_ERR_MSG_MOD(mqprio->extack, - "Preemption is not supported yet"); - return -EOPNOTSUPP; - } - igc_save_mqprio_params(adapter, mqprio->qopt.num_tc, mqprio->qopt.offset); =20 @@ -6808,6 +6802,7 @@ static int igc_tsn_enable_mqprio(struct igc_adapter *= adapter, adapter->queue_per_tc[i] =3D i; =20 mqprio->qopt.hw =3D TC_MQPRIO_HW_OFFLOAD_TCS; + igc_fpe_save_preempt_queue(adapter, mqprio); =20 apply: return igc_tsn_offload_apply(adapter); diff --git a/drivers/net/ethernet/intel/igc/igc_tsn.c b/drivers/net/etherne= t/intel/igc/igc_tsn.c index 897813eb2175..9dd45c6252bf 100644 --- a/drivers/net/ethernet/intel/igc/igc_tsn.c +++ b/drivers/net/ethernet/intel/igc/igc_tsn.c @@ -159,6 +159,15 @@ void igc_fpe_init(struct igc_adapter *adapter) ethtool_mmsv_init(&adapter->fpe.mmsv, adapter->netdev, &igc_mmsv_ops); } =20 +void igc_fpe_clear_preempt_queue(struct igc_adapter *adapter) +{ + for (int i =3D 0; i < adapter->num_tx_queues; i++) { + struct igc_ring *tx_ring =3D adapter->tx_ring[i]; + + tx_ring->preemptible =3D false; + } +} + static u32 igc_fpe_map_preempt_tc_to_queue(const struct igc_adapter *adapt= er, unsigned long preemptible_tcs) { diff --git a/drivers/net/ethernet/intel/igc/igc_tsn.h b/drivers/net/etherne= t/intel/igc/igc_tsn.h index f2e8bfef4871..a95b893459d7 100644 --- a/drivers/net/ethernet/intel/igc/igc_tsn.h +++ b/drivers/net/ethernet/intel/igc/igc_tsn.h @@ -17,6 +17,7 @@ enum igc_txd_popts_type { DECLARE_STATIC_KEY_FALSE(igc_fpe_enabled); =20 void igc_fpe_init(struct igc_adapter *adapter); +void igc_fpe_clear_preempt_queue(struct igc_adapter *adapter); void igc_fpe_save_preempt_queue(struct igc_adapter *adapter, const struct tc_mqprio_qopt_offload *mqprio); u32 igc_fpe_get_supported_frag_size(u32 frag_size); --=20 2.34.1 From nobody Sun Feb 8 05:43:19 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E53E1C84AA; Mon, 28 Apr 2025 06:03:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745820233; cv=none; b=aREVpus182FwOsphqYOZ6JKa0cChSZ5UPrzHGh9CCfS6vPdXIZAVqp0r/5cOc6ffEct95DBOJziBT/i2ggYrfAXLgyTEDI+CMV7RYsYDIXHqZ/cTrhdKr6mh5KQv78U05a6LZHmx3Xko8JPWLZDrdS0yk+MYUqWvjwvXGHXpWzc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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d="scan'208";a="133340847" Received: from mohdfai2-ilbpg12-1.png.intel.com ([10.88.227.73]) by orviesa006.jf.intel.com with ESMTP; 27 Apr 2025 23:03:49 -0700 From: Faizal Rahim To: Tony Nguyen , Przemek Kitszel , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vladimir Oltean Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Faizal Rahim , Chwee-Lin Choong Subject: [PATCH iwl-next v1 8/8] igc: SW pad preemptible frames for correct mCRC calculation Date: Mon, 28 Apr 2025 02:02:25 -0400 Message-Id: <20250428060225.1306986-9-faizal.abdul.rahim@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250428060225.1306986-1-faizal.abdul.rahim@linux.intel.com> References: <20250428060225.1306986-1-faizal.abdul.rahim@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chwee-Lin Choong A hardware-padded frame transmitted from the preemptible queue results in an incorrect mCRC computation by hardware, as the padding bytes are not included in the mCRC calculation. To address this, manually pad frames in preemptible queues to a minimum length of 60 bytes using skb_padto() before transmission. This ensures that the hardware includes the padding bytes in the mCRC computation, producing a correct mCRC value. Signed-off-by: Chwee-Lin Choong Signed-off-by: Faizal Rahim --- drivers/net/ethernet/intel/igc/igc_main.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethern= et/intel/igc/igc_main.c index 6b14b0d165f0..d495aee58601 100644 --- a/drivers/net/ethernet/intel/igc/igc_main.c +++ b/drivers/net/ethernet/intel/igc/igc_main.c @@ -1685,6 +1685,15 @@ static netdev_tx_t igc_xmit_frame_ring(struct sk_buf= f *skb, first->tx_flags =3D tx_flags; first->protocol =3D protocol; =20 + /* For preemptible queue, manually pad the skb so that HW includes + * padding bytes in mCRC calculation + */ + if (tx_ring->preemptible && skb->len < ETH_ZLEN) { + if (skb_padto(skb, ETH_ZLEN)) + goto out_drop; + skb_put(skb, ETH_ZLEN - skb->len); + } + tso =3D igc_tso(tx_ring, first, launch_time, first_flag, &hdr_len); if (tso < 0) goto out_drop; --=20 2.34.1