From nobody Fri Dec 19 19:18:11 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44230823DE; Mon, 28 Apr 2025 09:00:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745830841; cv=none; b=Xg3J6ttTEUYhBhtIyf/lUGR9mpvOrB6xXgdu57fcJ1jyrkN7fUcDApAxY4h58W8m4aNhHiQCd3VBBFYafuneyknLIiYenFrAsbJwvLJ6Sn1ZXcvXgP4jcYRAUKeA0I1LN2upxOWIayHnmbrtV7rSTZsVJMhkul5pLyxkCoGa6zE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745830841; c=relaxed/simple; bh=Qp3waWXnZNeiib80C7SH4AHEY7KYDUl8d8nTGop8bG4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=qyR7JwFuEApHsHyMsj+yn1m2Q0n33oXfgRFFpBYF5B1b+of6nYOcajIQaF9mWSs+PW3wIsJDN9o40Y5r+USiZtDIDE4KRRElZmf25pFcUpYXMH0gTc17XmvcAGJj6kVgV6NmJi6+S8WuCwCWC0arvFHtm7RhUg8pcQhyHHTQAKM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=7oK+1B83; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="7oK+1B83" Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 53S11GYP010486; Mon, 28 Apr 2025 11:00:26 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= mb7szTxe+O4/YlWD5eNPv4K70cyMKU44+b4hZfrYsbU=; b=7oK+1B836G7AwO7h Akmppiq+LTbSTzu109hRh2a1h93D/mAk5IVfgktHhkeK/H/xodG1HHznSAtYgElj xoVQ5XviHelBpjGHdOc+qfxjEKFsQmsGWUX0A5CSModcMaeba9f0BdINBMg8QTMZ FnSMMf2WqdPd29iM541ju6CLfHvBwPUvQ2X173tPH/su5KCjmo8kHNP8v+cxny4K 9JUi4ADPNNFLCULUEbGlstp9KFguZbtepoJ8IbHYfYpnaZniYcY5CRizunxM0/8V Vh1gi1OURhRrJVrNpX5iPM0CilUEVqCB78AGL0B7u9hbSOvmafO/DYwqgEnemz7p ox33jg== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 468pcg5qwd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 28 Apr 2025 11:00:26 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id EAE6E40045; Mon, 28 Apr 2025 10:59:22 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 34D09A40A3C; Mon, 28 Apr 2025 10:58:34 +0200 (CEST) Received: from localhost (10.48.87.62) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 28 Apr 2025 10:58:33 +0200 From: Patrice Chotard Date: Mon, 28 Apr 2025 10:58:30 +0200 Subject: [PATCH v11 1/3] dt-bindings: memory-controllers: Add STM32 Octo Memory Manager controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250428-upstream_ospi_v6-v11-1-1548736fd9d2@foss.st.com> References: <20250428-upstream_ospi_v6-v11-0-1548736fd9d2@foss.st.com> In-Reply-To: <20250428-upstream_ospi_v6-v11-0-1548736fd9d2@foss.st.com> To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Krzysztof Kozlowski , Catalin Marinas , Will Deacon CC: , , , , , Patrice Chotard X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-28_03,2025-04-24_02,2025-02-21_01 Add bindings for STM32 Octo Memory Manager (OMM) controller. OMM manages: - the muxing between 2 OSPI busses and 2 output ports. There are 4 possible muxing configurations: - direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2 output is on port 2 - OSPI1 and OSPI2 are multiplexed over the same output port 1 - swapped mode (no multiplexing), OSPI1 output is on port 2, OSPI2 output is on port 1 - OSPI1 and OSPI2 are multiplexed over the same output port 2 - the split of the memory area shared between the 2 OSPI instances. - chip select selection override. - the time between 2 transactions in multiplexed mode. Signed-off-by: Patrice Chotard Reviewed-by: Rob Herring (Arm) --- .../memory-controllers/st,stm32mp25-omm.yaml | 226 +++++++++++++++++= ++++ 1 file changed, 226 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32m= p25-omm.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm3= 2mp25-omm.yaml new file mode 100644 index 0000000000000000000000000000000000000000..344878db88188f5df5f9ee42633= 5bed38a8fac5c --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32mp25-omm= .yaml @@ -0,0 +1,226 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/st,stm32mp25-omm.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32 Octo Memory Manager (OMM) + +maintainers: + - Patrice Chotard + +description: | + The STM32 Octo Memory Manager is a low-level interface that enables an + efficient OCTOSPI pin assignment with a full I/O matrix (before alternate + function map) and multiplex of single/dual/quad/octal SPI interfaces over + the same bus. It Supports up to: + - Two single/dual/quad/octal SPI interfaces + - Two ports for pin assignment + +properties: + compatible: + const: st,stm32mp25-omm + + "#address-cells": + const: 2 + + "#size-cells": + const: 1 + + ranges: + description: | + Reflects the memory layout per OSPI instance. + Format: + 0 + minItems: 2 + maxItems: 2 + + reg: + items: + - description: OMM registers + - description: OMM memory map area + + reg-names: + items: + - const: regs + - const: memory_map + + memory-region: + description: + Memory region shared between the 2 OCTOSPI instance. + One or two phandle to a node describing a memory mapped region + depending of child number. + minItems: 1 + maxItems: 2 + + memory-region-names: + description: + Identify to which OSPI instance the memory region belongs to. + items: + enum: [ospi1, ospi2] + minItems: 1 + maxItems: 2 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: omm + - const: ospi1 + - const: ospi2 + + resets: + maxItems: 3 + + reset-names: + items: + - const: omm + - const: ospi1 + - const: ospi2 + + access-controllers: + maxItems: 1 + + power-domains: + maxItems: 1 + + st,syscfg-amcr: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + The Address Mapping Control Register (AMCR) is used to split the 256= MB + memory map area shared between the 2 OSPI instance. The Octo Memory + Manager sets the AMCR depending of the memory-region configuration. + The memory split bitmask description is: + - 000: OCTOSPI1 (256 Mbytes), OCTOSPI2 unmapped + - 001: OCTOSPI1 (192 Mbytes), OCTOSPI2 (64 Mbytes) + - 010: OCTOSPI1 (128 Mbytes), OCTOSPI2 (128 Mbytes) + - 011: OCTOSPI1 (64 Mbytes), OCTOSPI2 (192 Mbytes) + - 1xx: OCTOSPI1 unmapped, OCTOSPI2 (256 Mbytes) + items: + - items: + - description: phandle to syscfg + - description: register offset within syscfg + - description: register bitmask for memory split + + st,omm-req2ack-ns: + description: + In multiplexed mode (MUXEN =3D 1), this field defines the time in + nanoseconds between two transactions. + default: 0 + + st,omm-cssel-ovr: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Configure the chip select selector override for the 2 OCTOSPIs. + - 0: OCTOSPI1 chip select send to NCS1 OCTOSPI2 chip select send to = NCS1 + - 1: OCTOSPI1 chip select send to NCS2 OCTOSPI2 chip select send to = NCS1 + - 2: OCTOSPI1 chip select send to NCS1 OCTOSPI2 chip select send to = NCS2 + - 3: OCTOSPI1 chip select send to NCS2 OCTOSPI2 chip select send to = NCS2 + minimum: 0 + maximum: 3 + default: 0 + + st,omm-mux: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Configure the muxing between the 2 OCTOSPIs busses and the 2 output = ports. + - 0: direct mode + - 1: mux OCTOSPI1 and OCTOSPI2 to port 1 + - 2: swapped mode + - 3: mux OCTOSPI1 and OCTOSPI2 to port 2 + minimum: 0 + maximum: 3 + default: 0 + +patternProperties: + ^spi@[0-9]: + type: object + $ref: /schemas/spi/st,stm32mp25-ospi.yaml# + description: Required spi child node + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - clocks + - clock-names + - resets + - reset-names + - st,syscfg-amcr + - ranges + +additionalProperties: false + +examples: + - | + #include + #include + #include + ommanager@40500000 { + compatible =3D "st,stm32mp25-omm"; + reg =3D <0x40500000 0x400>, <0x60000000 0x10000000>; + reg-names =3D "regs", "memory_map"; + ranges =3D <0 0 0x40430000 0x400>, + <1 0 0x40440000 0x400>; + memory-region =3D <&mm_ospi1>, <&mm_ospi2>; + memory-region-names =3D "ospi1", "ospi2"; + pinctrl-0 =3D <&ospi_port1_clk_pins_a + &ospi_port1_io03_pins_a + &ospi_port1_cs0_pins_a>; + pinctrl-1 =3D <&ospi_port1_clk_sleep_pins_a + &ospi_port1_io03_sleep_pins_a + &ospi_port1_cs0_sleep_pins_a>; + pinctrl-names =3D "default", "sleep"; + clocks =3D <&rcc CK_BUS_OSPIIOM>, + <&scmi_clk CK_SCMI_OSPI1>, + <&scmi_clk CK_SCMI_OSPI2>; + clock-names =3D "omm", "ospi1", "ospi2"; + resets =3D <&rcc OSPIIOM_R>, + <&scmi_reset RST_SCMI_OSPI1>, + <&scmi_reset RST_SCMI_OSPI2>; + reset-names =3D "omm", "ospi1", "ospi2"; + access-controllers =3D <&rifsc 111>; + power-domains =3D <&CLUSTER_PD>; + #address-cells =3D <2>; + #size-cells =3D <1>; + st,syscfg-amcr =3D <&syscfg 0x2c00 0x7>; + st,omm-req2ack-ns =3D <0>; + st,omm-mux =3D <0>; + st,omm-cssel-ovr =3D <0>; + + spi@0 { + compatible =3D "st,stm32mp25-ospi"; + reg =3D <0 0 0x400>; + memory-region =3D <&mm_ospi1>; + interrupts =3D ; + dmas =3D <&hpdma 2 0x62 0x00003121 0x0>, + <&hpdma 2 0x42 0x00003112 0x0>; + dma-names =3D "tx", "rx"; + clocks =3D <&scmi_clk CK_SCMI_OSPI1>; + resets =3D <&scmi_reset RST_SCMI_OSPI1>, <&scmi_reset RST_SCMI_OSP= I1DLL>; + access-controllers =3D <&rifsc 74>; + power-domains =3D <&CLUSTER_PD>; + #address-cells =3D <1>; + #size-cells =3D <0>; + st,syscfg-dlyb =3D <&syscfg 0x1000>; + }; + + spi@1 { + compatible =3D "st,stm32mp25-ospi"; + reg =3D <1 0 0x400>; + memory-region =3D <&mm_ospi1>; + interrupts =3D ; + dmas =3D <&hpdma 3 0x62 0x00003121 0x0>, + <&hpdma 3 0x42 0x00003112 0x0>; + dma-names =3D "tx", "rx"; + clocks =3D <&scmi_clk CK_KER_OSPI2>; + resets =3D <&scmi_reset RST_SCMI_OSPI2>, <&scmi_reset RST_SCMI_OSP= I1DLL>; + access-controllers =3D <&rifsc 75>; + power-domains =3D <&CLUSTER_PD>; + #address-cells =3D <1>; + #size-cells =3D <0>; + st,syscfg-dlyb =3D <&syscfg 0x1000>; + }; + }; --=20 2.25.1