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Mon, 28 Apr 2025 12:09:25 +0100 (BST) Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa (172.25.2.134) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 28 Apr 2025 12:09:23 +0100 From: Matt Coster Date: Mon, 28 Apr 2025 12:07:14 +0100 Subject: [PATCH v4 1/2] arm64: dts: ti: k3-am62: New GPU binding details Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250428-bxs-4-64-dts-v4-1-eddafb4ae19f@imgtec.com> References: <20250428-bxs-4-64-dts-v4-0-eddafb4ae19f@imgtec.com> In-Reply-To: <20250428-bxs-4-64-dts-v4-0-eddafb4ae19f@imgtec.com> To: Nishanth Menon , Vignesh Raghavendra , "Tero Kristo" , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley CC: , , , Frank Binns , "Alessio Belle" , Alexandru Dadu , Luigi Santivetti , Randolph Sapp , Darren Etheridge , Matt Coster X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Reviewed-by: Randolph Sapp Signed-off-by: Matt Coster --- Changes in v4: - Remove lore link to previous commit - Link to v3: https://lore.kernel.org/r/20250422-bxs-4-64-dts-v3-1-ec6657bd= e135@imgtec.com Changes in v3: - None - Link to v2: https://lore.kernel.org/r/20250417-bxs-4-64-dts-v2-1-9f8c0923= 3114@imgtec.com Changes in v2: - Add Randolph's Rb - Link to v1: https://lore.kernel.org/r/20250415-bxs-4-64-dts-v1-1-f7d3fa06= 625d@imgtec.com This patch was previously sent as [DO NOT MERGE]: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-17-eda620c5865= f@imgtec.com There was discussion regarding the forward/backward compatibility of the changes in commit 2c01d9099859 referenced above, see: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-1-eda620c5865f= @imgtec.com --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am62-main.dtsi index 7d355aa73ea2116723735f70b9351cefcd8bc118..d17b25cae196b08d24adbe7c913= ccaba7eed37eb 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -691,12 +691,14 @@ ospi0: spi@fc40000 { }; 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Mon, 28 Apr 2025 12:09:24 +0100 From: Matt Coster Date: Mon, 28 Apr 2025 12:07:15 +0100 Subject: [PATCH v4 2/2] arm64: dts: ti: k3-j721s2: Add GPU node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250428-bxs-4-64-dts-v4-2-eddafb4ae19f@imgtec.com> References: <20250428-bxs-4-64-dts-v4-0-eddafb4ae19f@imgtec.com> In-Reply-To: <20250428-bxs-4-64-dts-v4-0-eddafb4ae19f@imgtec.com> To: Nishanth Menon , Vignesh Raghavendra , "Tero Kristo" , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley CC: , , , Frank Binns , "Alessio Belle" , Alexandru Dadu , Luigi Santivetti , Randolph Sapp , Darren Etheridge , Matt Coster X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2459; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=IeXXgzKgQ8kwF0+F01gM2sNmOCQIR4xlPk8JwmdDjm8=; b=owGbwMvMwCFWuUfy8817WRsYT6slMWTwJz4Wfh7ZzninLOGznY/fkeXFrBP+PNu/s+2CWEDAl 5eOEl3+HaUsDGIcDLJiiiw7VliuUPujpiVx41cxzBxWJpAhDFycAjCRi+yMDHcyHAq4RPavMgkJ zHw2vT5v7aq/5WLzk98HCt1jNEgJXM/IcEVt/+8N+Xe6RSZ8SZKt/rrysvAOJtPOoker73DWm9n z8wAA X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Authority-Analysis: v=2.4 cv=WoMrMcfv c=1 sm=1 tr=0 ts=680f61e6 cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=OXfeAiaCWNgA:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=sozttTNsAAAA:8 a=VwQbUJbxAAAA:8 a=r_1tXGB3AAAA:8 a=KjGJ_YhaLPe-tYgPVq4A:9 a=QEXdDO2ut3YA:10 a=S-JV1fTmrHgA:10 a=j2-svP0xy3wA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: vaxiKJJFniPvml___2t2S2s1DCfpFwlG X-Proofpoint-ORIG-GUID: vaxiKJJFniPvml___2t2S2s1DCfpFwlG X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI4MDA5MiBTYWx0ZWRfXx+mtO/Gv5Iuf CJe5917eWgHlSDP3JvBZf4l4n3hTfNJrlf2Aaap1WPfiJ2dNGnxOQ9K2d4EsGb9aNIZrryo/Mlx 1iHBDRUJ0D3zvJ6slLFRHaYP1dNjrbPHCS454Fyd8cSMI+HpohHUzkKsDcHk/QXBHdBEDZVy93n HRg1lWAkYsUhPvuQEryw1O5ZfiN7tnbmXVYyU7zXjNqzhLZP73fXYFd0aLbu4Kt5sEqUijd+Vym ZdglEMtjyizN5wghEC5P2lW64Pz0w3rx5kejjhGe9iAk106NiaOFAPZKaokVE/k8/YLVNNywmdc S2kNZ+yUpDMMJGXhjvl7u0ZtwbI2RJP9Py/MOwnyQwgUwiYu8/jhdpKxagdok1Djeb8dhOjlApO eWEEhTON9OARS7E2n8ZIZBucBcIrL/lL7z3haJbn7JrrqAGz1vgEdOXhLer7jqdGdCKC02b4 The J721S2 binding is based on the TI downstream binding in commit 54b0f2a00d92 ("arm64: dts: ti: k3-j721s2-main: add gpu node") from [1] but with updated compatible strings. The clock[2] and power[3] indices were verified from HTML docs, while the interrupt index comes from the TRM[4] (appendix "J721S2_Appendix_20241106_Public.xlsx", "Interrupts (inputs)", "GPU_BXS464_WRAP0_GPU_SS_0_OS_IRQ_OUT_0"). [1]: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel [2]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/clocks.html [3]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/devices.html [4]: https://www.ti.com/lit/zip/spruj28 (revision E) Reviewed-by: Randolph Sapp Signed-off-by: Matt Coster --- Changes in v4: - Fix typo in commit message (intterupt -> interrupt) - Link to v3: https://lore.kernel.org/r/20250422-bxs-4-64-dts-v3-2-ec6657bd= e135@imgtec.com Changes in v3: - Use assigned-clocks to pre-load the frequency of the core clock - Link to v2: https://lore.kernel.org/r/20250417-bxs-4-64-dts-v2-2-9f8c0923= 3114@imgtec.com Changes in v2: - Add interrupt reference details - Add Randolph's Rb - Link to v1: https://lore.kernel.org/r/20250415-bxs-4-64-dts-v1-2-f7d3fa06= 625d@imgtec.com This patch was previously sent as [DO NOT MERGE]: https://lore.kernel.org/r/20250410-sets-bxs-4-64-patch-v1-v6-18-eda620c5865= f@imgtec.com --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 92bf48fdbeba45ecca8c854db5f72fd3666239c5..9e36cbbe0ea2fefceedcc95b780= 68ded7ef395f0 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -2048,4 +2048,18 @@ watchdog8: watchdog@23f0000 { /* reserved for MAIN_R5F1_1 */ status =3D "reserved"; }; + + gpu: gpu@4e20000000 { + compatible =3D "ti,j721s2-gpu", "img,img-bxs-4-64", "img,img-rogue"; + reg =3D <0x4e 0x20000000 0x00 0x80000>; + clocks =3D <&k3_clks 130 1>; + clock-names =3D "core"; + assigned-clocks =3D <&k3_clks 130 1>; + assigned-clock-rates =3D <800000000>; + interrupts =3D ; + power-domains =3D <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 373 TI_SCI_PD_EXCLUSIVE>; + power-domain-names =3D "a", "b"; + dma-coherent; + }; }; --=20 2.49.0