From nobody Sat Feb 7 05:57:14 2026 Received: from out-176.mta1.migadu.com (out-176.mta1.migadu.com [95.215.58.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABD2225C802 for ; Sat, 26 Apr 2025 14:56:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745679402; cv=none; b=HqeyJfHr2M0ewpI0alqCSMuYmOQljwouKl3F6ouvQkdMirCq1XOxLuKScIOxy57HMemS2vZykjXGZpFzZLUFI9V/pQiJEFDfIHqmaFNfmKKwNdtqYLpPB1+6x2TOlqUQOeGyO9Wq6mhRG02L8cYjV34E1kbFbw7GERZ45i5CrdE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745679402; c=relaxed/simple; bh=A91oyDJzVW2A+SsBR2soCVb/dkMc/nCruf6KCnJLaKo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GhVRwsuMPU8m62S7YWehvMBCkz0o+BOs3Lg+VSd8zi6N5wFDnteebkjqidALE68wVOHCsRUrvzqRchHJVwuKcupnj0pTQejTXcvHycsbWBwC59STBd4C5xAwqPEkjbOQIpxHcgmaayd0eGJcfkUZh5xbZ2BXUyDtBs4fRjWGTVU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=iencinas.com; spf=pass smtp.mailfrom=iencinas.com; dkim=pass (2048-bit key) header.d=iencinas.com header.i=@iencinas.com header.b=X6B2J3t5; arc=none smtp.client-ip=95.215.58.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=iencinas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iencinas.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=iencinas.com header.i=@iencinas.com header.b="X6B2J3t5" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=iencinas.com; s=key1; t=1745679398; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=T3D2Wq7EVGu9ukjexMYuq8e+jDjRLdPow92yjOGXrYg=; b=X6B2J3t5QVaUwP7jK9sXf5HGgOifbaWiOZg7lIwgwDBLFPRYVgRamqlr5U8nc3JXmLJDg9 pvIfOWv387GbCj1rEYzJQhlCqtjAxKhV5yg6gW4rJ6Ez6ct8uUf0QNF5l9vlKVVsJnV5ou k17pnrDQs0cGuZ6dj80CFkBYSYvnqZpUM6fi+oKfAlbm3786HwXtb416wIhHOY9ggXETjv e3owhLIaP/k11iVwMF3+smUv77RheHhryHr9iQfJxHP/Qb+KShLMthcsdrpXD8bNBVij2M qm683yde833B5QC6WMFFbHFVoGEWsi8dO2mxzONqA7hZLVu8ZEuIRq0C891UDg== From: Ignacio Encinas Date: Sat, 26 Apr 2025 16:56:18 +0200 Subject: [PATCH v4 1/2] include/uapi/linux/swab.h: move default implementation for swab macros into asm-generic Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250426-riscv-swab-v4-1-64201404a68c@iencinas.com> References: <20250426-riscv-swab-v4-0-64201404a68c@iencinas.com> In-Reply-To: <20250426-riscv-swab-v4-0-64201404a68c@iencinas.com> To: Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Arnd Bergmann Cc: Eric Biggers , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linux.dev, skhan@linuxfoundation.org, Zhihang Shao , =?utf-8?q?Bj=C3=B6rn_T=C3=B6pel?= , linux-arch@vger.kernel.org, Ignacio Encinas X-Migadu-Flow: FLOW_OUT Move the default byteswap implementation into asm-generic so that it can be included from arch code. This is required by RISC-V in order to have a fallback implementation without duplicating it. Signed-off-by: Ignacio Encinas Acked-by: Palmer Dabbelt --- include/uapi/asm-generic/swab.h | 33 +++++++++++++++++++++++++++++++++ include/uapi/linux/swab.h | 33 +-------------------------------- 2 files changed, 34 insertions(+), 32 deletions(-) diff --git a/include/uapi/asm-generic/swab.h b/include/uapi/asm-generic/swa= b.h index f2da4e4fd4d1..232e81661dc5 100644 --- a/include/uapi/asm-generic/swab.h +++ b/include/uapi/asm-generic/swab.h @@ -3,6 +3,7 @@ #define _ASM_GENERIC_SWAB_H =20 #include +#include =20 /* * 32 bit architectures typically (but not always) want to @@ -16,4 +17,36 @@ #endif #endif =20 +/* + * casts are necessary for constants, because we never know how for sure + * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way. + */ +#define ___constant_swab16(x) ((__u16)( \ + (((__u16)(x) & (__u16)0x00ffU) << 8) | \ + (((__u16)(x) & (__u16)0xff00U) >> 8))) + +#define ___constant_swab32(x) ((__u32)( \ + (((__u32)(x) & (__u32)0x000000ffUL) << 24) | \ + (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \ + (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ + (((__u32)(x) & (__u32)0xff000000UL) >> 24))) + +#define ___constant_swab64(x) ((__u64)( \ + (((__u64)(x) & (__u64)0x00000000000000ffULL) << 56) | \ + (((__u64)(x) & (__u64)0x000000000000ff00ULL) << 40) | \ + (((__u64)(x) & (__u64)0x0000000000ff0000ULL) << 24) | \ + (((__u64)(x) & (__u64)0x00000000ff000000ULL) << 8) | \ + (((__u64)(x) & (__u64)0x000000ff00000000ULL) >> 8) | \ + (((__u64)(x) & (__u64)0x0000ff0000000000ULL) >> 24) | \ + (((__u64)(x) & (__u64)0x00ff000000000000ULL) >> 40) | \ + (((__u64)(x) & (__u64)0xff00000000000000ULL) >> 56))) + +#define ___constant_swahw32(x) ((__u32)( \ + (((__u32)(x) & (__u32)0x0000ffffUL) << 16) | \ + (((__u32)(x) & (__u32)0xffff0000UL) >> 16))) + +#define ___constant_swahb32(x) ((__u32)( \ + (((__u32)(x) & (__u32)0x00ff00ffUL) << 8) | \ + (((__u32)(x) & (__u32)0xff00ff00UL) >> 8))) + #endif /* _ASM_GENERIC_SWAB_H */ diff --git a/include/uapi/linux/swab.h b/include/uapi/linux/swab.h index 01717181339e..ca808c492996 100644 --- a/include/uapi/linux/swab.h +++ b/include/uapi/linux/swab.h @@ -6,38 +6,7 @@ #include #include #include - -/* - * casts are necessary for constants, because we never know how for sure - * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way. - */ -#define ___constant_swab16(x) ((__u16)( \ - (((__u16)(x) & (__u16)0x00ffU) << 8) | \ - (((__u16)(x) & (__u16)0xff00U) >> 8))) - -#define ___constant_swab32(x) ((__u32)( \ - (((__u32)(x) & (__u32)0x000000ffUL) << 24) | \ - (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \ - (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ - (((__u32)(x) & (__u32)0xff000000UL) >> 24))) - -#define ___constant_swab64(x) ((__u64)( \ - (((__u64)(x) & (__u64)0x00000000000000ffULL) << 56) | \ - (((__u64)(x) & (__u64)0x000000000000ff00ULL) << 40) | \ - (((__u64)(x) & (__u64)0x0000000000ff0000ULL) << 24) | \ - (((__u64)(x) & (__u64)0x00000000ff000000ULL) << 8) | \ - (((__u64)(x) & (__u64)0x000000ff00000000ULL) >> 8) | \ - (((__u64)(x) & (__u64)0x0000ff0000000000ULL) >> 24) | \ - (((__u64)(x) & (__u64)0x00ff000000000000ULL) >> 40) | \ - (((__u64)(x) & (__u64)0xff00000000000000ULL) >> 56))) - -#define ___constant_swahw32(x) ((__u32)( \ - (((__u32)(x) & (__u32)0x0000ffffUL) << 16) | \ - (((__u32)(x) & (__u32)0xffff0000UL) >> 16))) - -#define ___constant_swahb32(x) ((__u32)( \ - (((__u32)(x) & (__u32)0x00ff00ffUL) << 8) | \ - (((__u32)(x) & (__u32)0xff00ff00UL) >> 8))) +#include =20 /* * Implement the following as inlines, but define the interface using --=20 2.49.0 From nobody Sat Feb 7 05:57:14 2026 Received: from out-173.mta1.migadu.com (out-173.mta1.migadu.com [95.215.58.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 962CA25CC57 for ; Sat, 26 Apr 2025 14:56:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745679403; cv=none; b=r7UDHL9aQ/4GFjkjbKsq4+FYsU5PYI2fHKfbqLYrIIayUC0r5L3rBfUmeBjs/Y3sQJmYVv8nNtqJQ7YHpaWjbGDZtqZQEWz6neghTGB3QeQGYH2r19tKOfekGacu48M/PcQFnlEi3oefTc7Ci4HqHBPSgQnILBrc7Ff/+q8u8W8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745679403; c=relaxed/simple; bh=khH4WkE0mEFj9busZOZ8flLqC6GG3A9JhSqOV9SegDs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hDXkuzUZs+DFpv0JL/7/H/9w4eqWwt8rHam8hPGnjMflFriihcea0KF9p+bm4/HJ+JAsOBqJNd6223E86OyHBIWdU8bkcO0xbV/lOx3uJCFg7nbwVhCgYz0FF4iSFStjrORcF8jU4zP14tjfnoITY7FlMeOBtn35K17HBRNeM+g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=iencinas.com; spf=pass smtp.mailfrom=iencinas.com; dkim=pass (2048-bit key) header.d=iencinas.com header.i=@iencinas.com header.b=Cynu4gWm; arc=none smtp.client-ip=95.215.58.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=iencinas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iencinas.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=iencinas.com header.i=@iencinas.com header.b="Cynu4gWm" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=iencinas.com; s=key1; t=1745679399; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2kGESmUc5K4aE63sF+pKXsYXoXR44233ot7fuIdc7eY=; b=Cynu4gWmcHLMMh351vsuhpvZBlrDwJN2/KOCWh5A3hAyULSfEYOXSXewFSphEDseSyuP9v dV5Ez5gCNMYOGlS9N7LgVeLYvDcFg6l2yidT5oVjD1MP3cAjs6lIaoQFy255/djZqLMx37 G83QxgEd0YA1aGKOmeVxETiwZUeGNIwZsUTBcEmLzwJtaBzNYnFm+w0Z1Po1YDt/HTDHjd XxaVGqV5dHAc3WFg/6Via63St3EqkjbAL7xjS6/HpMVwuQ+HztkXazkwfzMulJrFU0d7oE hHMdeeMGEGIrtqbVJoZlO0baceoMVP8T9ygPzWF0yGpS5s4bHSx38JYsZ1rH/w== From: Ignacio Encinas Date: Sat, 26 Apr 2025 16:56:19 +0200 Subject: [PATCH v4 2/2] riscv: introduce asm/swab.h Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250426-riscv-swab-v4-2-64201404a68c@iencinas.com> References: <20250426-riscv-swab-v4-0-64201404a68c@iencinas.com> In-Reply-To: <20250426-riscv-swab-v4-0-64201404a68c@iencinas.com> To: Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Arnd Bergmann Cc: Eric Biggers , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linux.dev, skhan@linuxfoundation.org, Zhihang Shao , =?utf-8?q?Bj=C3=B6rn_T=C3=B6pel?= , linux-arch@vger.kernel.org, Ignacio Encinas X-Migadu-Flow: FLOW_OUT Implement endianness swap macros for RISC-V. Use the rev8 instruction when Zbb is available. Otherwise, rely on the default mask-and-shift implementation. Signed-off-by: Ignacio Encinas Acked-by: Palmer Dabbelt --- arch/riscv/include/asm/swab.h | 62 +++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 62 insertions(+) diff --git a/arch/riscv/include/asm/swab.h b/arch/riscv/include/asm/swab.h new file mode 100644 index 000000000000..629f6164c1f3 --- /dev/null +++ b/arch/riscv/include/asm/swab.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASM_RISCV_SWAB_H +#define _ASM_RISCV_SWAB_H + +#include +#include +#include +#include +#include + +#if defined(CONFIG_RISCV_ISA_ZBB) && !defined(NO_ALTERNATIVE) + +#define ARCH_SWAB(size, value) \ +({ \ + unsigned long x =3D value; \ + \ + if (riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) { \ + asm volatile (".option push\n" \ + ".option arch,+zbb\n" \ + "rev8 %0, %1\n" \ + ".option pop\n" \ + : "=3Dr" (x) : "r" (x)); \ + x =3D x >> (BITS_PER_LONG - size); \ + } else { \ + x =3D ___constant_swab##size(value); \ + } \ + x; \ +}) + +static __always_inline __u16 __arch_swab16(__u16 value) +{ + return ARCH_SWAB(16, value); +} + +static __always_inline __u32 __arch_swab32(__u32 value) +{ + return ARCH_SWAB(32, value); +} + +#ifdef CONFIG_64BIT +static __always_inline __u64 __arch_swab64(__u64 value) +{ + return ARCH_SWAB(64, value); +} +#else +static __always_inline __u64 __arch_swab64(__u64 value) +{ + __u32 h =3D value >> 32; + __u32 l =3D value & ((1ULL << 32) - 1); + + return ((__u64)(__arch_swab32(l)) << 32) | ((__u64)(__arch_swab32(h))); +} +#endif + +#define __arch_swab64 __arch_swab64 +#define __arch_swab32 __arch_swab32 +#define __arch_swab16 __arch_swab16 + +#undef ARCH_SWAB + +#endif /* defined(CONFIG_RISCV_ISA_ZBB) && !defined(NO_ALTERNATIVE) */ +#endif /* _ASM_RISCV_SWAB_H */ --=20 2.49.0