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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-317cf659c1dsm10670491fa.1.2025.04.25.21.51.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Apr 2025 21:51:23 -0700 (PDT) From: Dmitry Baryshkov Date: Sat, 26 Apr 2025 07:51:17 +0300 Subject: [PATCH v7] drm/msm/dpu: allow sharing SSPP between planes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250426-dpu-share-sspp-v7-1-6f4c719e373c@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIAERmDGgC/3XMQQrCMBCF4auUrI00aWbauPIe4iI00zYgTUg0K KV3Ny24EHH5Hnz/whJFR4mdqoVFyi45P5fRHirWT2YeiTtbNpO1VEIK4DY8eJpMJJ5SCLwFA4h EveiAFRQiDe65By/XsieX7j6+9n6G7f2bysAFRwQrEUXXDPp8c7OJ/ujjyLZWxo+HWsr2x2Pxy irUWtRDo7/9uq5vBiLsz+0AAAA= X-Change-ID: 20241215-dpu-share-sspp-75a566eec185 To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10784; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=cvM+rFSttFrCnA5Dtpe9rwoSgqfSbbDaMnA+P4ETru4=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoDGZLeUbhv5769s7b6SZbhNjOUa5WNq7iG+Fqy 3roFPEfSi+JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaAxmSwAKCRCLPIo+Aiko 1ZzqB/4ww/TtJNnE8uEyKaYbzOMHOKh372Uw3w4Ods/he1s+dAgfMGYEIFhSHRrwn+g/8K8UyLB FLPyhoZqsDZyLxm8nqAxSmCMYfN57KV0WShuHHJ+kki04wZX22O1FbXt9MxO4buu2pOSOY1BIlH JlQkVmYKFBMHcmz506WPoaExhQCb24/c4LYlhc3PC+OeZm/CY+0S5ppozcOfIvf1papq1FK2BaV 7B2XWhoQNMKDQkSUSm2qgI7WWiUXBB6A0qyocPbx7PTEHl84ukZx0ENVUiQiItsvKpScQf4/iph lzXTSuMS9M6qSBoT1+M0mRbzJZ37DznJ0gnXusq/itNbkUs7 X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: CioBAX2tZqkeXepI0rhPvJ7NkSbM1REg X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI2MDAzMCBTYWx0ZWRfX3aUS33J5Vho9 gKvNKYzrQ4lWLlI6Dq5xNXplHd9HodbzUXP4XHk08s7qL1ngFoaTxjMSePWAabfwrkPTbGAGaq2 eAAXe7kx9xiWwg2+pe1pOGXXmI9tNHIEYFjz0qz97WQhegvPg4D/M766vp7FSm7NnPshCelvHOc lAiBe0x1OnjFwXPJUGRdVA43junwwIBZhJCOGh5/wZuqCdxopPaAyr3poVcb6rX1Coa/SlqQYir qSo8thjp2q3ucKgmVbb+GkYTHFcwOIgim5T6X8qA2ENkaMCwKY+3h6dU8/IU9LtJcth9k8NEVfA U+KUJ2Nh0Rs+M7tG+qo/ISnqdnToJn27TZlOLA8Mv/rQuBHXXEmRYbh63ROuihq0CfmL7oc3fcn PXiX1HGf7nyUk9YtxV5ZO+VTMjX03LCvksCTVt5tEI9OUuU58a/OpHSz6Ttcm9l4b0l7uAfh X-Authority-Analysis: v=2.4 cv=QP1oRhLL c=1 sm=1 tr=0 ts=680c664e cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=8xA1kSRHgp9pt_5ip2oA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: CioBAX2tZqkeXepI0rhPvJ7NkSbM1REg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-26_01,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 clxscore=1015 mlxlogscore=999 lowpriorityscore=0 adultscore=0 mlxscore=0 bulkscore=0 phishscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504260030 From: Dmitry Baryshkov Since SmartDMA planes provide two rectangles, it is possible to use them to drive two different DRM planes, first plane getting the rect_0, another one using rect_1 of the same SSPP. The sharing algorithm is pretty simple, it requires that each of the planes can be driven by the single rectangle and only consecutive planes are considered. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- This patch has been deferred from v4 of virtual wide patchset to simplify the merging path. Now as the wide planes have been merged, pick up the patch that allows sharing of the SSPPs between two planes. --- Changes in v7: - Fixed typo (adjancent -> adjacent) (Abhinav) - Link to v6: https://lore.kernel.org/r/20250227-dpu-share-sspp-v6-1-4d4699= 10f399@linaro.org Changes in v6: - Fixed typo (consecutive) in the commit message (Abhinav) - Renamed prev_plane_state to prev_adjancent_plane_state (Abhinav) - Renamed prev_pstate to prev_adjancent_pstate as a followup to the previous change - Link to v5: https://lore.kernel.org/r/20241215-dpu-share-sspp-v5-1-665d26= 6183f9@linaro.org Changes in v5: - Rebased on top of the current msm-next-lumag - Renamed dpu_plane_try_multirect() to dpu_plane_try_multirect_shared() (Abhinav) - Link to v4: https://lore.kernel.org/dri-devel/20240314000216.392549-11-dm= itry.baryshkov@linaro.org/ --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 156 +++++++++++++++++++++++++-= ---- 1 file changed, 130 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index e03d6091f73640af96604a46740d58ae1f1fced1..421138bc3cb779c45fcfd531905= 6f0d31c862452 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -915,10 +915,9 @@ static int dpu_plane_atomic_check_nosspp(struct drm_pl= ane *plane, return 0; } =20 -static int dpu_plane_is_multirect_parallel_capable(struct dpu_hw_sspp *ssp= p, - struct dpu_sw_pipe_cfg *pipe_cfg, - const struct msm_format *fmt, - uint32_t max_linewidth) +static int dpu_plane_is_multirect_capable(struct dpu_hw_sspp *sspp, + struct dpu_sw_pipe_cfg *pipe_cfg, + const struct msm_format *fmt) { if (drm_rect_width(&pipe_cfg->src_rect) !=3D drm_rect_width(&pipe_cfg->ds= t_rect) || drm_rect_height(&pipe_cfg->src_rect) !=3D drm_rect_height(&pipe_cfg->= dst_rect)) @@ -930,10 +929,6 @@ static int dpu_plane_is_multirect_parallel_capable(str= uct dpu_hw_sspp *sspp, if (MSM_FORMAT_IS_YUV(fmt)) return false; =20 - if (MSM_FORMAT_IS_UBWC(fmt) && - drm_rect_width(&pipe_cfg->src_rect) > max_linewidth / 2) - return false; - if (!test_bit(DPU_SSPP_SMART_DMA_V1, &sspp->cap->features) && !test_bit(DPU_SSPP_SMART_DMA_V2, &sspp->cap->features)) return false; @@ -941,6 +936,27 @@ static int dpu_plane_is_multirect_parallel_capable(str= uct dpu_hw_sspp *sspp, return true; } =20 +static int dpu_plane_is_parallel_capable(struct dpu_sw_pipe_cfg *pipe_cfg, + const struct msm_format *fmt, + uint32_t max_linewidth) +{ + if (MSM_FORMAT_IS_UBWC(fmt) && + drm_rect_width(&pipe_cfg->src_rect) > max_linewidth / 2) + return false; + + return true; +} + +static int dpu_plane_is_multirect_parallel_capable(struct dpu_hw_sspp *ssp= p, + struct dpu_sw_pipe_cfg *pipe_cfg, + const struct msm_format *fmt, + uint32_t max_linewidth) +{ + return dpu_plane_is_multirect_capable(sspp, pipe_cfg, fmt) && + dpu_plane_is_parallel_capable(pipe_cfg, fmt, max_linewidth); +} + + static int dpu_plane_atomic_check_sspp(struct drm_plane *plane, struct drm_atomic_state *state, const struct drm_crtc_state *crtc_state) @@ -1002,6 +1018,69 @@ static bool dpu_plane_try_multirect_parallel(struct = dpu_sw_pipe *pipe, struct dp return true; } =20 +static int dpu_plane_try_multirect_shared(struct dpu_plane_state *pstate, + struct dpu_plane_state *prev_adjacent_pstate, + const struct msm_format *fmt, + uint32_t max_linewidth) +{ + struct dpu_sw_pipe *pipe =3D &pstate->pipe; + struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; + struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; + struct dpu_sw_pipe *prev_pipe =3D &prev_adjacent_pstate->pipe; + struct dpu_sw_pipe_cfg *prev_pipe_cfg =3D &prev_adjacent_pstate->pipe_cfg; + const struct msm_format *prev_fmt =3D msm_framebuffer_format(prev_adjacen= t_pstate->base.fb); + u16 max_tile_height =3D 1; + + if (prev_adjacent_pstate->r_pipe.sspp !=3D NULL || + prev_pipe->multirect_mode !=3D DPU_SSPP_MULTIRECT_NONE) + return false; + + if (!dpu_plane_is_multirect_capable(pipe->sspp, pipe_cfg, fmt) || + !dpu_plane_is_multirect_capable(prev_pipe->sspp, prev_pipe_cfg, prev_= fmt)) + return false; + + if (MSM_FORMAT_IS_UBWC(fmt)) + max_tile_height =3D max(max_tile_height, fmt->tile_height); + + if (MSM_FORMAT_IS_UBWC(prev_fmt)) + max_tile_height =3D max(max_tile_height, prev_fmt->tile_height); + + r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; + r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + + r_pipe->sspp =3D NULL; + + if (dpu_plane_is_parallel_capable(pipe_cfg, fmt, max_linewidth) && + dpu_plane_is_parallel_capable(prev_pipe_cfg, prev_fmt, max_linewidth)= && + (pipe_cfg->dst_rect.x1 >=3D prev_pipe_cfg->dst_rect.x2 || + prev_pipe_cfg->dst_rect.x1 >=3D pipe_cfg->dst_rect.x2)) { + pipe->sspp =3D prev_pipe->sspp; + + pipe->multirect_index =3D DPU_SSPP_RECT_1; + pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_PARALLEL; + + prev_pipe->multirect_index =3D DPU_SSPP_RECT_0; + prev_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_PARALLEL; + + return true; + } + + if (pipe_cfg->dst_rect.y1 >=3D prev_pipe_cfg->dst_rect.y2 + 2 * max_tile_= height || + prev_pipe_cfg->dst_rect.y1 >=3D pipe_cfg->dst_rect.y2 + 2 * max_tile_= height) { + pipe->sspp =3D prev_pipe->sspp; + + pipe->multirect_index =3D DPU_SSPP_RECT_1; + pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_TIME_MX; + + prev_pipe->multirect_index =3D DPU_SSPP_RECT_0; + prev_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_TIME_MX; + + return true; + } + + return false; +} + static int dpu_plane_atomic_check(struct drm_plane *plane, struct drm_atomic_state *state) { @@ -1102,13 +1181,14 @@ static int dpu_plane_virtual_atomic_check(struct dr= m_plane *plane, static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, struct dpu_global_state *global_state, struct drm_atomic_state *state, - struct drm_plane_state *plane_state) + struct drm_plane_state *plane_state, + struct drm_plane_state *prev_adjacent_plane_state) { const struct drm_crtc_state *crtc_state =3D NULL; struct drm_plane *plane =3D plane_state->plane; struct dpu_kms *dpu_kms =3D _dpu_plane_get_kms(plane); struct dpu_rm_sspp_requirements reqs; - struct dpu_plane_state *pstate; + struct dpu_plane_state *pstate, *prev_adjacent_pstate; struct dpu_sw_pipe *pipe; struct dpu_sw_pipe *r_pipe; struct dpu_sw_pipe_cfg *pipe_cfg; @@ -1120,6 +1200,8 @@ static int dpu_plane_virtual_assign_resources(struct = drm_crtc *crtc, plane_state->crtc); =20 pstate =3D to_dpu_plane_state(plane_state); + prev_adjacent_pstate =3D prev_adjacent_plane_state ? + to_dpu_plane_state(prev_adjacent_plane_state) : NULL; pipe =3D &pstate->pipe; r_pipe =3D &pstate->r_pipe; pipe_cfg =3D &pstate->pipe_cfg; @@ -1138,24 +1220,42 @@ static int dpu_plane_virtual_assign_resources(struc= t drm_crtc *crtc, =20 reqs.rot90 =3D drm_rotation_90_or_270(plane_state->rotation); =20 - pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &req= s); - if (!pipe->sspp) - return -ENODEV; + if (drm_rect_width(&r_pipe_cfg->src_rect) =3D=3D 0) { + if (!prev_adjacent_pstate || + !dpu_plane_try_multirect_shared(pstate, prev_adjacent_pstate, fmt, + dpu_kms->catalog->caps->max_linewidth)) { + pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &r= eqs); + if (!pipe->sspp) + return -ENODEV; =20 - if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg, - pipe->sspp, - msm_framebuffer_format(plane_state->fb), - dpu_kms->catalog->caps->max_linewidth)) { - /* multirect is not possible, use two SSPP blocks */ - r_pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &= reqs); - if (!r_pipe->sspp) + r_pipe->sspp =3D NULL; + + pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; + pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + + r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; + r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + } + } else { + pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &re= qs); + if (!pipe->sspp) return -ENODEV; =20 - pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg, + pipe->sspp, + msm_framebuffer_format(plane_state->fb), + dpu_kms->catalog->caps->max_linewidth)) { + /* multirect is not possible, use two SSPP blocks */ + r_pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, = &reqs); + if (!r_pipe->sspp) + return -ENODEV; =20 - r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; + pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + + r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; + r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + } } =20 return dpu_plane_atomic_check_sspp(plane, state, crtc_state); @@ -1168,6 +1268,7 @@ int dpu_assign_plane_resources(struct dpu_global_stat= e *global_state, unsigned int num_planes) { unsigned int i; + struct drm_plane_state *prev_adjacent_plane_state =3D NULL; =20 for (i =3D 0; i < num_planes; i++) { struct drm_plane_state *plane_state =3D states[i]; @@ -1177,9 +1278,12 @@ int dpu_assign_plane_resources(struct dpu_global_sta= te *global_state, continue; =20 int ret =3D dpu_plane_virtual_assign_resources(crtc, global_state, - state, plane_state); + state, plane_state, + prev_adjacent_plane_state); if (ret) - return ret; + break; + + prev_adjacent_plane_state =3D plane_state; } =20 return 0; --- base-commit: 6c0be3e511b9191b90bc73af10f93f0f62b8cbe8 change-id: 20241215-dpu-share-sspp-75a566eec185 Best regards, --=20 Dmitry Baryshkov