From nobody Fri Dec 19 20:15:46 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54E4C23C8B3 for ; Fri, 25 Apr 2025 09:51:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745574679; cv=none; b=oE5leRN2yraYOglXqO8tYXwJuibC4nU1j+Kdl3LQhmWolSvULQeeUBNo4krnN0myNmDbcmj8sXAKbOPWpdLWxSc7oG/9/qL12qzmBEKj6jdewkhw0HCmOxQo5uSu+CozyRU7n63uzD808exP9tbedxKKpfeDCIqVsW/VyFn4/V0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745574679; c=relaxed/simple; bh=xym3v0e44LzfxsP+l23xhraVAo9VPG9pio75t7iRjK4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mDFR4hK9Zq/Lnme5ywGdPCt6J85U3gfgQY8BarJqzlfxctIffiJ12NLqi54gI63SKXQX6iOTp9VllZpGWzLMOWgk1v/WWVjrLKMgqKGFkNa9nut+hPtef4kljeb/aFJHb9bLV8Tz7H76uS1a3p1bwdazTAbtUBu2zhS/CamyRdg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=Dy5DiM3d; arc=none smtp.client-ip=170.10.129.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="Dy5DiM3d" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1745574675; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ulLK6NlOiEAhdPVwDdczTykPb0OkKkVgfQ9oAnDdfac=; b=Dy5DiM3dw0pm2nAQua9/ISPGF3Cpu9FDtqkTQlWIj1R3KhI0FVGXeE3sTPr/BABXe67tHA Y/KtZuTbwdYb1VTbtats0GyVnIPTgBe6nwBC6t8vdv9TQc6kd15cKFbBQb+HjaAcrr8dhT 72DFY88LS1FkY70j0BzvAHROnsCQ1sw= Received: from mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-571-l-cWz9XCOjKsaMtdYlNT6g-1; Fri, 25 Apr 2025 05:51:08 -0400 X-MC-Unique: l-cWz9XCOjKsaMtdYlNT6g-1 X-Mimecast-MFC-AGG-ID: l-cWz9XCOjKsaMtdYlNT6g_1745574667 Received: from mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.17]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id D487F19560AF; Fri, 25 Apr 2025 09:51:06 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.44.34.172]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id D0666195608D; Fri, 25 Apr 2025 09:51:00 +0000 (UTC) From: Jocelyn Falempe To: Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , David Airlie , Simona Vetter , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH v7 7/8] drm/i915/display: Add drm_panic support for Y-tiling with DPT Date: Fri, 25 Apr 2025 11:37:53 +0200 Message-ID: <20250425094949.473060-8-jfalempe@redhat.com> In-Reply-To: <20250425094949.473060-1-jfalempe@redhat.com> References: <20250425094949.473060-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 Content-Type: text/plain; charset="utf-8" On Alder Lake and later, it's not possible to disable tiling when DPT is enabled. So this commit implements Y-Tiling support, to still be able to draw the panic screen. Signed-off-by: Jocelyn Falempe --- .../gpu/drm/i915/display/intel_atomic_plane.c | 69 ++++++++++++++++++- .../drm/i915/display/skl_universal_plane.c | 15 ++-- 2 files changed, 77 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gp= u/drm/i915/display/intel_atomic_plane.c index 505719f53411..c846e300c48c 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -1262,6 +1262,33 @@ intel_cleanup_plane_fb(struct drm_plane *plane, */ static struct iosys_map panic_map; =20 +/* Handle Y-tiling, only if DPT is enabled (otherwise disabling tiling is = easier) + * All DPT hardware have 128-bytes width tiling, so Y-tile dimension is 32= x32 + * pixels for 32bits pixels. + */ +#define YTILE_WIDTH 32 +#define YTILE_HEIGHT 32 +#define YTILE_SIZE (YTILE_WIDTH * YTILE_HEIGHT * 4) + +static void intel_ytile_set_pixel(struct drm_scanout_buffer *sb, unsigned = int x, unsigned int y, + u32 color) +{ + u32 offset; + unsigned int swizzle; + unsigned int width_in_blocks =3D DIV_ROUND_UP(sb->width, 32); + + /* Block offset */ + offset =3D ((y / YTILE_HEIGHT) * width_in_blocks + (x / YTILE_WIDTH)) * Y= TILE_SIZE; + + x =3D x % YTILE_WIDTH; + y =3D y % YTILE_HEIGHT; + + /* bit order inside a block is x4 x3 x2 y4 y3 y2 y1 y0 x1 x0 */ + swizzle =3D (x & 3) | ((y & 0x1f) << 2) | ((x & 0x1c) << 5); + offset +=3D swizzle * 4; + iosys_map_wr(&sb->map[0], offset, u32, color); +} + static void intel_panic_flush(struct drm_plane *plane) { struct intel_plane_state *plane_state =3D to_intel_plane_state(plane->sta= te); @@ -1286,6 +1313,34 @@ static void intel_panic_flush(struct drm_plane *plan= e) iplane->disable_tiling(iplane); } =20 +static void (*intel_get_tiling_func(u64 fb_modifier))(struct drm_scanout_b= uffer *sb, unsigned int x, + unsigned int y, u32 color) +{ + switch (fb_modifier) { + case I915_FORMAT_MOD_Y_TILED: + case I915_FORMAT_MOD_Y_TILED_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: + case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: + case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: + return intel_ytile_set_pixel; + case I915_FORMAT_MOD_X_TILED: + case I915_FORMAT_MOD_4_TILED: + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: + case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: + case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: + case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: + case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: + case I915_FORMAT_MOD_4_TILED_BMG_CCS: + case I915_FORMAT_MOD_4_TILED_LNL_CCS: + case I915_FORMAT_MOD_Yf_TILED: + case I915_FORMAT_MOD_Yf_TILED_CCS: + default: + /* Not supported yet */ + return NULL; + } +} + static int intel_get_scanout_buffer(struct drm_plane *plane, struct drm_scanout_buffer *sb) { @@ -1309,8 +1364,13 @@ static int intel_get_scanout_buffer(struct drm_plane= *plane, } else { int ret; /* Can't disable tiling if DPT is in use */ - if (intel_fb_uses_dpt(fb)) - return -EOPNOTSUPP; + if (intel_fb_uses_dpt(fb)) { + if (fb->format->cpp[0] !=3D 4) + return -EOPNOTSUPP; + sb->set_pixel =3D intel_get_tiling_func(fb->modifier); + if (!sb->set_pixel) + return -EOPNOTSUPP; + } ret =3D intel_bo_panic_map(obj, &panic_map); if (ret) return ret; @@ -1321,7 +1381,10 @@ static int intel_get_scanout_buffer(struct drm_plane= *plane, sb->map[0] =3D panic_map; sb->width =3D fb->width; sb->height =3D fb->height; - sb->format =3D fb->format; + /* Use the generic linear format, because tiling, RC, CCS, CC + * will be disabled in disable_tiling() + */ + sb->format =3D drm_format_info(fb->format->format); sb->pitch[0] =3D fb->pitches[0]; =20 return 0; diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/g= pu/drm/i915/display/skl_universal_plane.c index 64a1e8e7122d..9d84e9aecd93 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2794,15 +2794,22 @@ static void skl_disable_tiling(struct intel_plane *= plane) { struct intel_plane_state *state =3D to_intel_plane_state(plane->base.stat= e); struct intel_display *display =3D to_intel_display(plane); - u32 stride =3D state->view.color_plane[0].scanout_stride / 64; + const struct drm_framebuffer *fb =3D state->hw.fb; u32 plane_ctl; =20 plane_ctl =3D intel_de_read(display, PLANE_CTL(plane->pipe, plane->id)); - plane_ctl &=3D ~PLANE_CTL_TILED_MASK; =20 - intel_de_write_fw(display, PLANE_STRIDE(plane->pipe, plane->id), - PLANE_STRIDE_(stride)); + if (intel_fb_uses_dpt(fb)) { + /* if DPT is enabled, keep tiling, but disable compression */ + plane_ctl &=3D ~PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; + } else { + /* if DPT is not supported, disable tiling, and update stride */ + u32 stride =3D state->view.color_plane[0].scanout_stride / 64; =20 + plane_ctl &=3D ~PLANE_CTL_TILED_MASK; + intel_de_write_fw(display, PLANE_STRIDE(plane->pipe, plane->id), + PLANE_STRIDE_(stride)); + } intel_de_write_fw(display, PLANE_CTL(plane->pipe, plane->id), plane_ctl); =20 intel_de_write_fw(display, PLANE_SURF(plane->pipe, plane->id), --=20 2.49.0