From nobody Fri Dec 19 20:15:55 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D9AF2367BB for ; Fri, 25 Apr 2025 09:50:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745574632; cv=none; b=sXTYZ9apyAJpLvYxNp+YEsWnRHaYR3KN229Ld7qDINOhE5xAAbhjY5g/wMz137KcEYn2GyVmdmSsoHG8gqe54ImLkOx6eDBuylLy5br6KAKlNnVFF02RSy7uAnyczz7MlCF3JxjViDLd6ppmrY++3MAS+h6whFhw+YEJcXdVfzE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745574632; c=relaxed/simple; bh=PHtgF7UfCJaJ7amCBHP7MAuhHq+jm5fnrOJFQiYW3n4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bWmRYdlv2WN5wJAcivZSaNdKHLwu53fK20e50o3ojYK/djgRelvKRSUTTLfgLdnSZakB5U/mH4a/YnBohp5crlU1DVfTnZ85fWFnHzmRfCL0WfYL4Yx2gQgNTG+tZU6co221ZX3dhOgiWNie6NI8mO8aFmjX6HIL9fQr85mnaJc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=amC5xOAx; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="amC5xOAx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1745574630; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UzG3x/gkLWPOScz2+XOG7DZeBmtr2uIxexf3063+54k=; b=amC5xOAxyNi0GjiayQABGl+gPqedjGxMD/Q9KM1ybmKhO0TpzBh/FHwMjTRkoXZt0QWM5S sOFyN/U9ETzgrYkuUmax5biwc8F7nT1ZOo65Kl+HRo33lvy7AYZy6CAuHKF90+kD4tehLL HIHlwuKBs1K5ybng6fVe/6xmtjSixPA= Received: from mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-122-0T4y5msNNn6WQC-GXxuT0g-1; Fri, 25 Apr 2025 05:50:28 -0400 X-MC-Unique: 0T4y5msNNn6WQC-GXxuT0g-1 X-Mimecast-MFC-AGG-ID: 0T4y5msNNn6WQC-GXxuT0g_1745574626 Received: from mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.17]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 48E071800446; Fri, 25 Apr 2025 09:50:26 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.44.34.172]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 9F715195608F; Fri, 25 Apr 2025 09:50:21 +0000 (UTC) From: Jocelyn Falempe To: Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , David Airlie , Simona Vetter , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH v7 2/8] drm/i915/display/i9xx: Add a disable_tiling() for i9xx planes Date: Fri, 25 Apr 2025 11:37:48 +0200 Message-ID: <20250425094949.473060-3-jfalempe@redhat.com> In-Reply-To: <20250425094949.473060-1-jfalempe@redhat.com> References: <20250425094949.473060-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 drm_panic draws in linear framebuffer, so it's easier to re-use the current framebuffer, and disable tiling in the panic handler, to show the panic screen. This assumes that the alignment restriction is always smaller in linear than in tiled. It also assumes that the linear framebuffer size is always smaller than the tiled. Signed-off-by: Jocelyn Falempe --- v7: * Reword commit message about alignment/size when disabling tiling (Ville = Syrj=C3=A4l=C3=A4) drivers/gpu/drm/i915/display/i9xx_plane.c | 23 +++++++++++++++++++ .../drm/i915/display/intel_display_types.h | 2 ++ 2 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i9= 15/display/i9xx_plane.c index 5e8344fdfc28..9c93d5ac7129 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -908,6 +908,27 @@ static const struct drm_plane_funcs i8xx_plane_funcs = =3D { .format_mod_supported =3D i8xx_plane_format_mod_supported, }; =20 +static void i9xx_disable_tiling(struct intel_plane *plane) +{ + struct intel_display *display =3D to_intel_display(plane); + enum i9xx_plane_id i9xx_plane =3D plane->i9xx_plane; + u32 dspcntr; + u32 reg; + + dspcntr =3D intel_de_read_fw(display, DSPCNTR(display, i9xx_plane)); + dspcntr &=3D ~DISP_TILED; + intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr); + + if (DISPLAY_VER(display) >=3D 4) { + reg =3D intel_de_read_fw(display, DSPSURF(display, i9xx_plane)); + intel_de_write_fw(display, DSPSURF(display, i9xx_plane), reg); + + } else { + reg =3D intel_de_read_fw(display, DSPADDR(display, i9xx_plane)); + intel_de_write_fw(display, DSPADDR(display, i9xx_plane), reg); + } +} + struct intel_plane * intel_primary_plane_create(struct intel_display *display, enum pipe pipe) { @@ -1050,6 +1071,8 @@ intel_primary_plane_create(struct intel_display *disp= lay, enum pipe pipe) } } =20 + plane->disable_tiling =3D i9xx_disable_tiling; + modifiers =3D intel_fb_plane_get_modifiers(display, INTEL_PLANE_CAP_TILIN= G_X); =20 if (DISPLAY_VER(display) >=3D 5 || display->platform.g4x) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/g= pu/drm/i915/display/intel_display_types.h index 7415564d058a..69deb6ae14a0 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1513,6 +1513,8 @@ struct intel_plane { bool async_flip); void (*enable_flip_done)(struct intel_plane *plane); void (*disable_flip_done)(struct intel_plane *plane); + /* For drm_panic */ + void (*disable_tiling)(struct intel_plane *plane); }; =20 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state= , base) --=20 2.49.0