From nobody Mon Feb 9 15:26:57 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass(p=none dis=none) header.from=zytor.com ARC-Seal: i=1; a=rsa-sha256; t=1745570160; cv=none; d=zohomail.com; s=zohoarc; b=ksOBgumO7dAV7mlglkUe5W/I9cfL1Xn/d7L6qpy5KdbPM1SbC0RdAVFDMmcoDTC6lozt7NlB/NcMRwUb7oEoqeWnV6bPpazaetmsBOgwmk6LLF0hTH0TPY5GALM6padQgzym+FhaKS4/5/JO4avbo/4pSWnzxULBkE2GhvwSKnY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1745570160; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Rr0vTnv8pBflcTi5rZDOYZSrbHCmv/JEcdKGNOUNlWI=; b=YqJ9nEZOGZ85OZF3MsY7S9lsQohASTR+RIt5Rf+H0bxZs9ejUlk9EdDkU8F2FvtD6VGy8AfVXbzWnhu9p/L4B0pitsmCOc7Ll8RIeJBYxX5n2tPy1Msbra80QS3LpB+vdxuGcfMrswsw6TA9qgJCAHYMLKf87NENB4vHazrwIMQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 1745570160358468.5366511782804; Fri, 25 Apr 2025 01:36:00 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.967319.1357195 (Exim 4.92) (envelope-from ) id 1u8EX3-0004Ix-C5; Fri, 25 Apr 2025 08:35:37 +0000 Received: by outflank-mailman (output) from mailman id 967319.1357195; Fri, 25 Apr 2025 08:35:37 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u8EX2-0004Eg-OS; Fri, 25 Apr 2025 08:35:36 +0000 Received: by outflank-mailman (input) for mailman id 967319; Fri, 25 Apr 2025 08:35:35 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u8EX0-0002sz-Uw for xen-devel@lists.xenproject.org; Fri, 25 Apr 2025 08:35:34 +0000 Received: from mail.zytor.com (unknown [2607:7c80:54:3::138]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 3b131b3d-21b0-11f0-9ffb-bf95429c2676; Fri, 25 Apr 2025 10:35:24 +0200 (CEST) Received: from terminus.zytor.com (terminus.zytor.com [IPv6:2607:7c80:54:3:0:0:0:136]) (authenticated bits=0) by mail.zytor.com (8.18.1/8.17.1) with ESMTPSA id 53P8Yg5W2390085 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NO); Fri, 25 Apr 2025 01:35:04 -0700 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 3b131b3d-21b0-11f0-9ffb-bf95429c2676 DKIM-Filter: OpenDKIM Filter v2.11.0 mail.zytor.com 53P8Yg5W2390085 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=zytor.com; s=2025042001; t=1745570105; bh=Rr0vTnv8pBflcTi5rZDOYZSrbHCmv/JEcdKGNOUNlWI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QO2yTydNX7XYERdeG5etf9HFKP49Ph8IgVoixKPgmmAhHGegY4da2C1VI38Eiik3C H1TrRnrbAOCOP7xQkCODJl7YJYgJ8Se0Ixj47f5h3u0O+FWA5WwEzSHceNuxjXorrJ Cnhp0O1E0sGRQzi1ZwghIUhPFm5/3YaCbplo6tu3wvW9UgqNm/q9LjiY7VYRFTD791 d+0NlR9p9GKXGtx2f1oZ/9tTBOrqd/sWkJgG/jx9dprkZEnqIOqEObT82almfwI9Un UfhlrG6uJ0+j4K6T6NqiZtKIdZXHGUA5gLpjA5P3mHRAnTXtRgeqeQ6FcqKd+/IhoF KUd8njE+zgiPg== From: "Xin Li (Intel)" To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-hyperv@vger.kernel.org, virtualization@lists.linux.dev, linux-pm@vger.kernel.org, linux-edac@vger.kernel.org, xen-devel@lists.xenproject.org, linux-acpi@vger.kernel.org, linux-hwmon@vger.kernel.org, netdev@vger.kernel.org, platform-driver-x86@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, acme@kernel.org, jgross@suse.com, andrew.cooper3@citrix.com, peterz@infradead.org, namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, kan.liang@linux.intel.com, wei.liu@kernel.org, ajay.kaher@broadcom.com, bcm-kernel-feedback-list@broadcom.com, tony.luck@intel.com, pbonzini@redhat.com, vkuznets@redhat.com, seanjc@google.com, luto@kernel.org, boris.ostrovsky@oracle.com, kys@microsoft.com, haiyangz@microsoft.com, decui@microsoft.com, dapeng1.mi@linux.intel.com Subject: [PATCH v3 08/14] x86/msr: Convert __rdmsr() uses to native_rdmsrq() uses Date: Fri, 25 Apr 2025 01:34:31 -0700 Message-ID: <20250425083442.2390017-9-xin@zytor.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250425083442.2390017-1-xin@zytor.com> References: <20250425083442.2390017-1-xin@zytor.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @zytor.com) X-ZM-MESSAGEID: 1745570161925019000 Content-Type: text/plain; charset="utf-8" __rdmsr() is the lowest level MSR write API, with native_rdmsr() and native_rdmsrq() serving as higher-level wrappers around it. #define native_rdmsr(msr, val1, val2) \ do { \ u64 __val =3D __rdmsr((msr)); \ (void)((val1) =3D (u32)__val); \ (void)((val2) =3D (u32)(__val >> 32)); \ } while (0) static __always_inline u64 native_rdmsrq(u32 msr) { return __rdmsr(msr); } However, __rdmsr() continues to be utilized in various locations. MSR APIs are designed for different scenarios, such as native or pvops, with or without trace, and safe or non-safe. Unfortunately, the current MSR API names do not adequately reflect these factors, making it challenging to select the most appropriate API for various situations. To pave the way for improving MSR API names, convert __rdmsr() uses to native_rdmsrq() to ensure consistent usage. Later, these APIs can be renamed to better reflect their implications, such as native or pvops, with or without trace, and safe or non-safe. No functional change intended. Signed-off-by: Xin Li (Intel) --- arch/x86/coco/sev/core.c | 2 +- arch/x86/events/amd/brs.c | 2 +- arch/x86/hyperv/hv_vtl.c | 4 ++-- arch/x86/hyperv/ivm.c | 2 +- arch/x86/include/asm/mshyperv.h | 2 +- arch/x86/kernel/cpu/common.c | 2 +- arch/x86/kernel/cpu/mce/core.c | 4 ++-- arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 2 +- arch/x86/kvm/vmx/vmx.c | 4 ++-- arch/x86/mm/mem_encrypt_identity.c | 4 ++-- 10 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c index b18a33fe8dd3..c4137c94678d 100644 --- a/arch/x86/coco/sev/core.c +++ b/arch/x86/coco/sev/core.c @@ -276,7 +276,7 @@ static noinstr struct ghcb *__sev_get_ghcb(struct ghcb_= state *state) =20 static inline u64 sev_es_rd_ghcb_msr(void) { - return __rdmsr(MSR_AMD64_SEV_ES_GHCB); + return native_rdmsrq(MSR_AMD64_SEV_ES_GHCB); } =20 static __always_inline void sev_es_wr_ghcb_msr(u64 val) diff --git a/arch/x86/events/amd/brs.c b/arch/x86/events/amd/brs.c index 3f5ecfd80d1e..06f35a6b58a5 100644 --- a/arch/x86/events/amd/brs.c +++ b/arch/x86/events/amd/brs.c @@ -49,7 +49,7 @@ static __always_inline void set_debug_extn_cfg(u64 val) =20 static __always_inline u64 get_debug_extn_cfg(void) { - return __rdmsr(MSR_AMD_DBG_EXTN_CFG); + return native_rdmsrq(MSR_AMD_DBG_EXTN_CFG); } =20 static bool __init amd_brs_detect(void) diff --git a/arch/x86/hyperv/hv_vtl.c b/arch/x86/hyperv/hv_vtl.c index 13242ed8ff16..c6343e699154 100644 --- a/arch/x86/hyperv/hv_vtl.c +++ b/arch/x86/hyperv/hv_vtl.c @@ -149,11 +149,11 @@ static int hv_vtl_bringup_vcpu(u32 target_vp_index, i= nt cpu, u64 eip_ignored) input->vp_context.rip =3D rip; input->vp_context.rsp =3D rsp; input->vp_context.rflags =3D 0x0000000000000002; - input->vp_context.efer =3D __rdmsr(MSR_EFER); + input->vp_context.efer =3D native_rdmsrq(MSR_EFER); input->vp_context.cr0 =3D native_read_cr0(); input->vp_context.cr3 =3D __native_read_cr3(); input->vp_context.cr4 =3D native_read_cr4(); - input->vp_context.msr_cr_pat =3D __rdmsr(MSR_IA32_CR_PAT); + input->vp_context.msr_cr_pat =3D native_rdmsrq(MSR_IA32_CR_PAT); input->vp_context.idtr.limit =3D idt_ptr.size; input->vp_context.idtr.base =3D idt_ptr.address; input->vp_context.gdtr.limit =3D gdt_ptr.size; diff --git a/arch/x86/hyperv/ivm.c b/arch/x86/hyperv/ivm.c index 8209de792388..09a165a3c41e 100644 --- a/arch/x86/hyperv/ivm.c +++ b/arch/x86/hyperv/ivm.c @@ -111,7 +111,7 @@ u64 hv_ghcb_hypercall(u64 control, void *input, void *o= utput, u32 input_size) =20 static inline u64 rd_ghcb_msr(void) { - return __rdmsr(MSR_AMD64_SEV_ES_GHCB); + return native_rdmsrq(MSR_AMD64_SEV_ES_GHCB); } =20 static inline void wr_ghcb_msr(u64 val) diff --git a/arch/x86/include/asm/mshyperv.h b/arch/x86/include/asm/mshyper= v.h index 15d00dace70f..778444310cfb 100644 --- a/arch/x86/include/asm/mshyperv.h +++ b/arch/x86/include/asm/mshyperv.h @@ -305,7 +305,7 @@ void hv_set_non_nested_msr(unsigned int reg, u64 value); =20 static __always_inline u64 hv_raw_get_msr(unsigned int reg) { - return __rdmsr(reg); + return native_rdmsrq(reg); } =20 #else /* CONFIG_HYPERV */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 079ded4eeb86..cefc99990bde 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -164,7 +164,7 @@ static void ppin_init(struct cpuinfo_x86 *c) =20 /* Is the enable bit set? */ if (val & 2UL) { - c->ppin =3D __rdmsr(info->msr_ppin); + c->ppin =3D native_rdmsrq(info->msr_ppin); set_cpu_cap(c, info->feature); return; } diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 1ae75ec7ac95..32286bad75e6 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -121,7 +121,7 @@ void mce_prep_record_common(struct mce *m) { m->cpuid =3D cpuid_eax(1); m->cpuvendor =3D boot_cpu_data.x86_vendor; - m->mcgcap =3D __rdmsr(MSR_IA32_MCG_CAP); + m->mcgcap =3D native_rdmsrq(MSR_IA32_MCG_CAP); /* need the internal __ version to avoid deadlocks */ m->time =3D __ktime_get_real_seconds(); } @@ -1298,7 +1298,7 @@ static noinstr bool mce_check_crashing_cpu(void) (crashing_cpu !=3D -1 && crashing_cpu !=3D cpu)) { u64 mcgstatus; =20 - mcgstatus =3D __rdmsr(MSR_IA32_MCG_STATUS); + mcgstatus =3D native_rdmsrq(MSR_IA32_MCG_STATUS); =20 if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_ZHAOXIN) { if (mcgstatus & MCG_STATUS_LMCES) diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cp= u/resctrl/pseudo_lock.c index 6e5edd76086e..324bd4919300 100644 --- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c +++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c @@ -482,7 +482,7 @@ int resctrl_arch_pseudo_lock_fn(void *_plr) * the buffer and evict pseudo-locked memory read earlier from the * cache. */ - saved_msr =3D __rdmsr(MSR_MISC_FEATURE_CONTROL); + saved_msr =3D native_rdmsrq(MSR_MISC_FEATURE_CONTROL); native_wrmsrq(MSR_MISC_FEATURE_CONTROL, prefetch_disable_bits); closid_p =3D this_cpu_read(pqr_state.cur_closid); rmid_p =3D this_cpu_read(pqr_state.cur_rmid); diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index cd0d6c1fcf9c..68c8bb247fc4 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -380,7 +380,7 @@ static __always_inline void vmx_disable_fb_clear(struct= vcpu_vmx *vmx) if (!vmx->disable_fb_clear) return; =20 - msr =3D __rdmsr(MSR_IA32_MCU_OPT_CTRL); + msr =3D native_rdmsrq(MSR_IA32_MCU_OPT_CTRL); msr |=3D FB_CLEAR_DIS; native_wrmsrq(MSR_IA32_MCU_OPT_CTRL, msr); /* Cache the MSR value to avoid reading it later */ @@ -7307,7 +7307,7 @@ void noinstr vmx_spec_ctrl_restore_host(struct vcpu_v= mx *vmx, return; =20 if (flags & VMX_RUN_SAVE_SPEC_CTRL) - vmx->spec_ctrl =3D __rdmsr(MSR_IA32_SPEC_CTRL); + vmx->spec_ctrl =3D native_rdmsrq(MSR_IA32_SPEC_CTRL); =20 /* * If the guest/host SPEC_CTRL values differ, restore the host value. diff --git a/arch/x86/mm/mem_encrypt_identity.c b/arch/x86/mm/mem_encrypt_i= dentity.c index afda349db35b..32af1cc378e4 100644 --- a/arch/x86/mm/mem_encrypt_identity.c +++ b/arch/x86/mm/mem_encrypt_identity.c @@ -527,7 +527,7 @@ void __head sme_enable(struct boot_params *bp) me_mask =3D 1UL << (ebx & 0x3f); =20 /* Check the SEV MSR whether SEV or SME is enabled */ - RIP_REL_REF(sev_status) =3D msr =3D __rdmsr(MSR_AMD64_SEV); + RIP_REL_REF(sev_status) =3D msr =3D native_rdmsrq(MSR_AMD64_SEV); feature_mask =3D (msr & MSR_AMD64_SEV_ENABLED) ? AMD_SEV_BIT : AMD_SME_BI= T; =20 /* @@ -558,7 +558,7 @@ void __head sme_enable(struct boot_params *bp) return; =20 /* For SME, check the SYSCFG MSR */ - msr =3D __rdmsr(MSR_AMD64_SYSCFG); + msr =3D native_rdmsrq(MSR_AMD64_SYSCFG); if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT)) return; } --=20 2.49.0