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Fri, 25 Apr 2025 01:26:01 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:4b10:d9aa:98d0:5bb5]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-309f77417d6sm1019179a91.4.2025.04.25.01.25.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Apr 2025 01:26:00 -0700 (PDT) From: Chen-Yu Tsai To: Liam Girdwood , Mark Brown , Matthias Brugger , AngeloGioacchino Del Regno Cc: Chen-Yu Tsai , Jaroslav Kysela , Takashi Iwai , Jiaxin Yu , linux-sound@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Darren Ye Subject: [PATCH 2/3] ASoC: mediatek: mt8183-afe-pcm: Shorten irq_data table using macros Date: Fri, 25 Apr 2025 16:25:49 +0800 Message-ID: <20250425082551.1467042-3-wenst@chromium.org> X-Mailer: git-send-email 2.49.0.850.g28803427d3-goog In-Reply-To: <20250425082551.1467042-1-wenst@chromium.org> References: <20250425082551.1467042-1-wenst@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The irq_data table describes all the supported interrupts for the audio frontend. The parameters are either the same or can be derived from the interrupt number. This results in a very long table (in source code) that can be shortened with macros. Do just that. Signed-off-by: Chen-Yu Tsai --- sound/soc/mediatek/mt8183/mt8183-afe-pcm.c | 176 ++++----------------- 1 file changed, 33 insertions(+), 143 deletions(-) diff --git a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c b/sound/soc/mediate= k/mt8183/mt8183-afe-pcm.c index 3e2334e9324b..5e340e77b9d5 100644 --- a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c +++ b/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c @@ -492,150 +492,40 @@ static const struct mtk_base_memif_data memif_data[M= T8183_MEMIF_NUM] =3D { MT8183_MEMIF_BASE(HDMI, -1, -1, -1), }; =20 +#define MT8183_AFE_IRQ_BASE(_id, _fs_reg, _fs_shift, _fs_maskbit) \ + [MT8183_IRQ_##_id] =3D { \ + .id =3D MT8183_IRQ_##_id, \ + .irq_cnt_reg =3D AFE_IRQ_MCU_CNT##_id, \ + .irq_cnt_shift =3D 0, \ + .irq_cnt_maskbit =3D 0x3ffff, \ + .irq_fs_reg =3D _fs_reg, \ + .irq_fs_shift =3D _fs_shift, \ + .irq_fs_maskbit =3D _fs_maskbit, \ + .irq_en_reg =3D AFE_IRQ_MCU_CON0, \ + .irq_en_shift =3D IRQ##_id##_MCU_ON_SFT, \ + .irq_clr_reg =3D AFE_IRQ_MCU_CLR, \ + .irq_clr_shift =3D IRQ##_id##_MCU_CLR_SFT, \ + } + +#define MT8183_AFE_IRQ(_id) \ + MT8183_AFE_IRQ_BASE(_id, AFE_IRQ_MCU_CON1 + _id / 8 * 4, \ + IRQ##_id##_MCU_MODE_SFT, \ + IRQ##_id##_MCU_MODE_MASK) + +#define MT8183_AFE_IRQ_NOFS(_id) MT8183_AFE_IRQ_BASE(_id, -1, -1, -1) + static const struct mtk_base_irq_data irq_data[MT8183_IRQ_NUM] =3D { - [MT8183_IRQ_0] =3D { - .id =3D MT8183_IRQ_0, - .irq_cnt_reg =3D AFE_IRQ_MCU_CNT0, - .irq_cnt_shift =3D 0, - .irq_cnt_maskbit =3D 0x3ffff, - .irq_fs_reg =3D AFE_IRQ_MCU_CON1, - .irq_fs_shift =3D IRQ0_MCU_MODE_SFT, - .irq_fs_maskbit =3D IRQ0_MCU_MODE_MASK, - .irq_en_reg =3D AFE_IRQ_MCU_CON0, - .irq_en_shift =3D IRQ0_MCU_ON_SFT, - .irq_clr_reg =3D AFE_IRQ_MCU_CLR, - .irq_clr_shift =3D IRQ0_MCU_CLR_SFT, - }, - [MT8183_IRQ_1] =3D { - .id =3D MT8183_IRQ_1, - .irq_cnt_reg =3D AFE_IRQ_MCU_CNT1, - .irq_cnt_shift =3D 0, - .irq_cnt_maskbit =3D 0x3ffff, - .irq_fs_reg =3D AFE_IRQ_MCU_CON1, - .irq_fs_shift =3D IRQ1_MCU_MODE_SFT, - .irq_fs_maskbit =3D IRQ1_MCU_MODE_MASK, - .irq_en_reg =3D AFE_IRQ_MCU_CON0, - .irq_en_shift =3D IRQ1_MCU_ON_SFT, - .irq_clr_reg =3D AFE_IRQ_MCU_CLR, - .irq_clr_shift =3D IRQ1_MCU_CLR_SFT, - }, - [MT8183_IRQ_2] =3D { - .id =3D MT8183_IRQ_2, - .irq_cnt_reg =3D AFE_IRQ_MCU_CNT2, - .irq_cnt_shift =3D 0, - .irq_cnt_maskbit =3D 0x3ffff, - .irq_fs_reg =3D AFE_IRQ_MCU_CON1, - .irq_fs_shift =3D IRQ2_MCU_MODE_SFT, - .irq_fs_maskbit =3D IRQ2_MCU_MODE_MASK, - .irq_en_reg =3D AFE_IRQ_MCU_CON0, - .irq_en_shift =3D IRQ2_MCU_ON_SFT, - .irq_clr_reg =3D AFE_IRQ_MCU_CLR, - .irq_clr_shift =3D IRQ2_MCU_CLR_SFT, - }, - [MT8183_IRQ_3] =3D { - .id =3D MT8183_IRQ_3, - .irq_cnt_reg =3D AFE_IRQ_MCU_CNT3, - .irq_cnt_shift =3D 0, - .irq_cnt_maskbit =3D 0x3ffff, - .irq_fs_reg =3D AFE_IRQ_MCU_CON1, - .irq_fs_shift =3D IRQ3_MCU_MODE_SFT, - .irq_fs_maskbit =3D IRQ3_MCU_MODE_MASK, - .irq_en_reg =3D AFE_IRQ_MCU_CON0, - .irq_en_shift =3D IRQ3_MCU_ON_SFT, - .irq_clr_reg =3D AFE_IRQ_MCU_CLR, - .irq_clr_shift =3D IRQ3_MCU_CLR_SFT, - }, - [MT8183_IRQ_4] =3D { - .id =3D MT8183_IRQ_4, - .irq_cnt_reg =3D AFE_IRQ_MCU_CNT4, - .irq_cnt_shift =3D 0, - .irq_cnt_maskbit =3D 0x3ffff, - .irq_fs_reg =3D AFE_IRQ_MCU_CON1, - .irq_fs_shift =3D IRQ4_MCU_MODE_SFT, - .irq_fs_maskbit =3D IRQ4_MCU_MODE_MASK, - .irq_en_reg =3D AFE_IRQ_MCU_CON0, - .irq_en_shift =3D IRQ4_MCU_ON_SFT, - .irq_clr_reg =3D AFE_IRQ_MCU_CLR, - .irq_clr_shift =3D IRQ4_MCU_CLR_SFT, - }, - [MT8183_IRQ_5] =3D { - .id =3D MT8183_IRQ_5, - .irq_cnt_reg =3D AFE_IRQ_MCU_CNT5, - .irq_cnt_shift =3D 0, - .irq_cnt_maskbit =3D 0x3ffff, - .irq_fs_reg =3D AFE_IRQ_MCU_CON1, - .irq_fs_shift =3D IRQ5_MCU_MODE_SFT, - .irq_fs_maskbit =3D IRQ5_MCU_MODE_MASK, - .irq_en_reg =3D AFE_IRQ_MCU_CON0, - .irq_en_shift =3D IRQ5_MCU_ON_SFT, - .irq_clr_reg =3D AFE_IRQ_MCU_CLR, - .irq_clr_shift =3D IRQ5_MCU_CLR_SFT, - }, - [MT8183_IRQ_6] =3D { - .id =3D MT8183_IRQ_6, - .irq_cnt_reg =3D AFE_IRQ_MCU_CNT6, - .irq_cnt_shift =3D 0, - .irq_cnt_maskbit =3D 0x3ffff, - .irq_fs_reg =3D AFE_IRQ_MCU_CON1, - .irq_fs_shift =3D IRQ6_MCU_MODE_SFT, - .irq_fs_maskbit =3D IRQ6_MCU_MODE_MASK, - .irq_en_reg =3D AFE_IRQ_MCU_CON0, - .irq_en_shift =3D IRQ6_MCU_ON_SFT, - .irq_clr_reg =3D AFE_IRQ_MCU_CLR, - .irq_clr_shift =3D IRQ6_MCU_CLR_SFT, - }, - [MT8183_IRQ_7] =3D { - .id =3D MT8183_IRQ_7, - .irq_cnt_reg =3D AFE_IRQ_MCU_CNT7, - .irq_cnt_shift =3D 0, - .irq_cnt_maskbit =3D 0x3ffff, - .irq_fs_reg =3D AFE_IRQ_MCU_CON1, - .irq_fs_shift =3D IRQ7_MCU_MODE_SFT, - .irq_fs_maskbit =3D IRQ7_MCU_MODE_MASK, - .irq_en_reg =3D AFE_IRQ_MCU_CON0, - .irq_en_shift =3D IRQ7_MCU_ON_SFT, - .irq_clr_reg =3D AFE_IRQ_MCU_CLR, - .irq_clr_shift =3D IRQ7_MCU_CLR_SFT, - }, - [MT8183_IRQ_8] =3D { - .id =3D MT8183_IRQ_8, - .irq_cnt_reg =3D AFE_IRQ_MCU_CNT8, - .irq_cnt_shift =3D 0, - .irq_cnt_maskbit =3D 0x3ffff, - .irq_fs_reg =3D -1, - .irq_fs_shift =3D -1, - .irq_fs_maskbit =3D -1, - .irq_en_reg =3D AFE_IRQ_MCU_CON0, - .irq_en_shift =3D IRQ8_MCU_ON_SFT, - .irq_clr_reg =3D AFE_IRQ_MCU_CLR, - .irq_clr_shift =3D IRQ8_MCU_CLR_SFT, - }, - [MT8183_IRQ_11] =3D { - .id =3D MT8183_IRQ_11, - .irq_cnt_reg =3D AFE_IRQ_MCU_CNT11, - .irq_cnt_shift =3D 0, - .irq_cnt_maskbit =3D 0x3ffff, - .irq_fs_reg =3D AFE_IRQ_MCU_CON2, - .irq_fs_shift =3D IRQ11_MCU_MODE_SFT, - .irq_fs_maskbit =3D IRQ11_MCU_MODE_MASK, - .irq_en_reg =3D AFE_IRQ_MCU_CON0, - .irq_en_shift =3D IRQ11_MCU_ON_SFT, - .irq_clr_reg =3D AFE_IRQ_MCU_CLR, - .irq_clr_shift =3D IRQ11_MCU_CLR_SFT, - }, - [MT8183_IRQ_12] =3D { - .id =3D MT8183_IRQ_12, - .irq_cnt_reg =3D AFE_IRQ_MCU_CNT12, - .irq_cnt_shift =3D 0, - .irq_cnt_maskbit =3D 0x3ffff, - .irq_fs_reg =3D AFE_IRQ_MCU_CON2, - .irq_fs_shift =3D IRQ12_MCU_MODE_SFT, - .irq_fs_maskbit =3D IRQ12_MCU_MODE_MASK, - .irq_en_reg =3D AFE_IRQ_MCU_CON0, - .irq_en_shift =3D IRQ12_MCU_ON_SFT, - .irq_clr_reg =3D AFE_IRQ_MCU_CLR, - .irq_clr_shift =3D IRQ12_MCU_CLR_SFT, - }, + MT8183_AFE_IRQ(0), + MT8183_AFE_IRQ(1), + MT8183_AFE_IRQ(2), + MT8183_AFE_IRQ(3), + MT8183_AFE_IRQ(4), + MT8183_AFE_IRQ(5), + MT8183_AFE_IRQ(6), + MT8183_AFE_IRQ(7), + MT8183_AFE_IRQ_NOFS(8), + MT8183_AFE_IRQ(11), + MT8183_AFE_IRQ(12), }; =20 static bool mt8183_is_volatile_reg(struct device *dev, unsigned int reg) --=20 2.49.0.850.g28803427d3-goog