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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73e25a9a308sm3868948b3a.136.2025.04.25.16.48.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Apr 2025 16:48:07 -0700 (PDT) From: Unnathi Chalicheemala Date: Fri, 25 Apr 2025 16:48:01 -0700 Subject: [PATCH v6 1/3] firmware: qcom_scm: Add API to get waitqueue IRQ info Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250425-multi_waitq_scm-v6-1-cba8ca5a6d03@oss.qualcomm.com> References: <20250425-multi_waitq_scm-v6-0-cba8ca5a6d03@oss.qualcomm.com> In-Reply-To: <20250425-multi_waitq_scm-v6-0-cba8ca5a6d03@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@oss.qualcomm.com, Prasad Sodagudi , Satya Durga Srinivasu Prabhala , Trilok Soni , Bartosz Golaszewski , Unnathi Chalicheemala X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1745624885; l=4335; i=unnathi.chalicheemala@oss.qualcomm.com; s=20240514; h=from:subject:message-id; bh=HwSmczY1BPfAzd6mqaQZTmW0WxFuAC6Q6eQmyL2FVcg=; b=uDBkoWIyiXlYh0Cny/rX2dEV+G7u6bEMULbDg3HWxfc5BNFsYGmpNODZ8wpdviHmeNUdCLEj/ IXbMilpSbdRBhR8zZJng++qWgGrvusNCJ30TkEe4tS0zSgsGNVmWm9T X-Developer-Key: i=unnathi.chalicheemala@oss.qualcomm.com; a=ed25519; pk=o+hVng49r5k2Gc/f9xiwzvR3y1q4kwLOASwo+cFowXI= X-Proofpoint-GUID: 5Mr2oQbDs32Q7y_lJ-h_KF23Mkk-sPh0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI1MDE3MiBTYWx0ZWRfX+7Ngm3zC802n picTGKn0hglzHXXRnq4MRZ9kmvHjBpMtRh19R4VsYTQm0odlZkk12TQYIcK+4EolhwEYEvsKO0F kYsei5vhz4cnCxKcUB4wVmcsPIQuo9dMk6nlrhxiBJvvQDI6dFLu3tlddvYzp+uo8PrGFs+QVPH FyLyWbh89Ysa1n5kmnYNVXUFdu0MvW4udNYKU0dY36nGNzlqyTqmZWW0gVnTmZTk8eL46z4WBWS devmk3JxFfDFmUTsDmJyFkqQfSpk/f7vsfioHFndDmFpfRw2s2XHRB104vRk83Wb7YgRUvAMOcA 2arV0r5mn47sjRq358+JVqcOErr9xlkX27n24qLn/WxBXzZxh7yLy0bmC7c/EgHwY1nUXhbeSIM IFgtG600j2w2oNAiI1ns6nWQUQtwvcc0EkwPZfF1ejbZCIrQLIfClBLPIeih4NyxsgnAsqur X-Authority-Analysis: v=2.4 cv=Tu/mhCXh c=1 sm=1 tr=0 ts=680c1f39 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=BWC7kBQSOfkspHPoMaoA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: 5Mr2oQbDs32Q7y_lJ-h_KF23Mkk-sPh0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-25_07,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 phishscore=0 mlxlogscore=999 bulkscore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504250172 Bootloader and firmware for SM8650 and older chipsets expect node name as "qcom_scm", in order to patch the wait queue IRQ information. However, DeviceTree uses node name "scm" and this mismatch prevents firmware from correctly identifying waitqueue IRQ information. Waitqueue IRQ is used for signaling between secure and non-secure worlds. To resolve this, introduce qcom_scm_get_waitq_irq() that'll get the hardware IRQ number to be used from firmware instead of relying on data provided by devicetree, thereby bypassing the DeviceTree node name mismatch. This hardware IRQ number is converted to a Linux IRQ number using newly defined fill_irq_fwspec_params(). This Linux IRQ number is then supplied to the threaded_irq call. Reviewed-by: Bartosz Golaszewski Signed-off-by: Unnathi Chalicheemala --- drivers/firmware/qcom/qcom_scm.c | 60 ++++++++++++++++++++++++++++++++++++= +++- drivers/firmware/qcom/qcom_scm.h | 1 + 2 files changed, 60 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index fc4d67e4c4a67efc77e0135c06db47bc14d0aeaa..529e1d067b1901c4417a1f1fd9c= 3255ee31de532 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -29,12 +29,18 @@ #include #include #include +#include =20 #include "qcom_scm.h" #include "qcom_tzmem.h" =20 static u32 download_mode; =20 +#define GIC_SPI_BASE 32 +#define GIC_MAX_SPI 1019 // SPIs in GICv3 spec range from 32..1019 +#define GIC_ESPI_BASE 4096 +#define GIC_MAX_ESPI 5119 // ESPIs in GICv3 spec range from 4096..5119 + struct qcom_scm { struct device *dev; struct clk *core_clk; @@ -2094,6 +2100,55 @@ bool qcom_scm_is_available(void) } EXPORT_SYMBOL_GPL(qcom_scm_is_available); =20 +static int qcom_scm_fill_irq_fwspec_params(struct irq_fwspec *fwspec, u32 = virq) +{ + if (virq >=3D GIC_SPI_BASE && virq <=3D GIC_MAX_SPI) { + fwspec->param[0] =3D GIC_SPI; + fwspec->param[1] =3D virq - GIC_SPI_BASE; + } else if (virq >=3D GIC_ESPI_BASE && virq <=3D GIC_MAX_ESPI) { + fwspec->param[0] =3D GIC_ESPI; + fwspec->param[1] =3D virq - GIC_ESPI_BASE; + } else { + WARN(1, "Unexpected virq: %d\n", virq); + return -ENXIO; + } + fwspec->param[2] =3D IRQ_TYPE_EDGE_RISING; + fwspec->param_count =3D 3; + + return 0; +} + +static int qcom_scm_get_waitq_irq(void) +{ + int ret; + u32 hwirq; + struct qcom_scm_desc desc =3D { + .svc =3D QCOM_SCM_SVC_WAITQ, + .cmd =3D QCOM_SCM_WAITQ_GET_INFO, + .owner =3D ARM_SMCCC_OWNER_SIP + }; + struct qcom_scm_res res; + struct irq_fwspec fwspec; + struct device_node *parent_irq_node; + + ret =3D qcom_scm_call_atomic(__scm->dev, &desc, &res); + if (ret) + return ret; + + hwirq =3D res.result[1] & GENMASK(15, 0); + + ret =3D qcom_scm_fill_irq_fwspec_params(&fwspec, hwirq); + if (ret) + return ret; + parent_irq_node =3D of_irq_find_parent(__scm->dev->of_node); + + fwspec.fwnode =3D of_node_to_fwnode(parent_irq_node); + + ret =3D irq_create_fwspec_mapping(&fwspec); + + return ret; +} + static int qcom_scm_assert_valid_wq_ctx(u32 wq_ctx) { /* FW currently only supports a single wq_ctx (zero). @@ -2250,7 +2305,10 @@ static int qcom_scm_probe(struct platform_device *pd= ev) /* Paired with smp_load_acquire() in qcom_scm_is_available(). */ smp_store_release(&__scm, scm); =20 - irq =3D platform_get_irq_optional(pdev, 0); + irq =3D qcom_scm_get_waitq_irq(); + if (irq < 0) + irq =3D platform_get_irq_optional(pdev, 0); + if (irq < 0) { if (irq !=3D -ENXIO) { ret =3D irq; diff --git a/drivers/firmware/qcom/qcom_scm.h b/drivers/firmware/qcom/qcom_= scm.h index 097369d38b84efbce5d672c4f36cc87373aac24b..7c6cb3154b394ab910bf7775a5a= e07a28e0b57a5 100644 --- a/drivers/firmware/qcom/qcom_scm.h +++ b/drivers/firmware/qcom/qcom_scm.h @@ -148,6 +148,7 @@ struct qcom_tzmem_pool *qcom_scm_get_tzmem_pool(void); #define QCOM_SCM_SVC_WAITQ 0x24 #define QCOM_SCM_WAITQ_RESUME 0x02 #define QCOM_SCM_WAITQ_GET_WQ_CTX 0x03 +#define QCOM_SCM_WAITQ_GET_INFO 0x04 =20 #define QCOM_SCM_SVC_GPU 0x28 #define QCOM_SCM_SVC_GPU_INIT_REGS 0x01 --=20 2.34.1 From nobody Sun Feb 8 21:06:00 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C72D1267F75 for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73e25a9a308sm3868948b3a.136.2025.04.25.16.48.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Apr 2025 16:48:08 -0700 (PDT) From: Unnathi Chalicheemala Date: Fri, 25 Apr 2025 16:48:02 -0700 Subject: [PATCH v6 2/3] firmware: qcom_scm: Support multiple waitq contexts Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250425-multi_waitq_scm-v6-2-cba8ca5a6d03@oss.qualcomm.com> References: <20250425-multi_waitq_scm-v6-0-cba8ca5a6d03@oss.qualcomm.com> In-Reply-To: <20250425-multi_waitq_scm-v6-0-cba8ca5a6d03@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@oss.qualcomm.com, Prasad Sodagudi , Satya Durga Srinivasu Prabhala , Trilok Soni , Unnathi Chalicheemala X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1745624885; l=4913; i=unnathi.chalicheemala@oss.qualcomm.com; s=20240514; h=from:subject:message-id; bh=CxAQMDuh9krf1N30Zll9vwqxkcHp/5I1Da/5rxIOxLU=; b=dz2NiBZ9DGZH4/87bJKCw9aH1uTMzvimIZ3Ing3QOSgd092wkyhzGNap/LUVA9DhgcYTM0wfa Ix6f0hXcRETAzOHs8oABuucTO4yO1ccZvK3wnsnn/S0rSL7roKBMA48 X-Developer-Key: i=unnathi.chalicheemala@oss.qualcomm.com; a=ed25519; pk=o+hVng49r5k2Gc/f9xiwzvR3y1q4kwLOASwo+cFowXI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI1MDE3MiBTYWx0ZWRfX0+LW58598I81 51SrhodxWBaxSxrWtvBbsqrIHws7hhWne6CRXckCyqVStyQL5uijEjUgbrvrkyuSSeASJINJSxo AsvfigrfXozxgrWjAE0nHaRLA3Gmnj1cNAzi6rvGXFJfCqeGThmWIeTT66EQgkI7wU+7cgB8OJ7 POb+qckX+hUNAEzNDQMypHGwKR8QNtLsnCa/osgHTEOrgN4f/yJYt9WET9koJGaNsa7BvuM8uLD 42U+ebWujxBvxdKaBEhxHV+Wa3+1kz+/nYSphB1r77GIL+k9wcAO9lTz7XGwPrvFpZ4Fgwl87GH TAC3E04TgPsudCKzt8o4ob09i30XafUGXr4rLGtIOg/f1Ix2Uvr4Y+cNH3paCV7Uk/sgIU8Yis1 W8h3w5XxTJZZf1cYeKhco4YX89MTUDWqesASIOJNFTuB3zClpKVqBdpkhkWfw7KNG7JmX3sE X-Authority-Analysis: v=2.4 cv=bs1MBFai c=1 sm=1 tr=0 ts=680c1f3a cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=EUspDBNiAAAA:8 a=IoDWPEjDBkkTTY39AZoA:9 a=+jEqtf1s3R9VXZ0wqowq2kgwd+I=:19 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-ORIG-GUID: IRN2rtQhYUUJXsDWZPfOpxr0j3iqdAJc X-Proofpoint-GUID: IRN2rtQhYUUJXsDWZPfOpxr0j3iqdAJc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-25_07,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 suspectscore=0 mlxlogscore=999 mlxscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 impostorscore=0 malwarescore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504250172 Currently, only a single waitqueue context exists, with waitqueue id zero. Multi-waitqueue mechanism is added in firmware to support the case when multiple VMs make SMC calls or single VM making multiple calls on same CPU. When VMs make SMC call, firmware will allocate waitqueue context assuming the SMC call to be a blocking call. SMC calls that cannot acquire resources are returned to sleep in the calling VM. When resource is available, VM will be notified to wake sleeping thread and resume SMC call. SM8650 firmware can allocate two such waitq contexts so create these two waitqueue contexts. Unique waitqueue contexts are supported by a dynamically sized array where each unique wq_ctx is associated with a struct completion variable for easy lookup. To get the number of waitqueue contexts directly from firmware, qcom_scm_query_waitq_count() is introduced. On older targets which support only a single waitqueue, wq_cnt is set to 1 as SCM call for query_waitq_count() is not implemented for single waitqueue case. Signed-off-by: Unnathi Chalicheemala --- drivers/firmware/qcom/qcom_scm.c | 78 ++++++++++++++++++++++++++++--------= ---- 1 file changed, 56 insertions(+), 22 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index 529e1d067b1901c4417a1f1fd9c3255ee31de532..9f8db13ef1ce14cc324fa9f0abf= 5c6a97ceb7b8b 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -47,7 +47,7 @@ struct qcom_scm { struct clk *iface_clk; struct clk *bus_clk; struct icc_path *path; - struct completion waitq_comp; + struct completion *waitq; struct reset_controller_dev reset; =20 /* control access to the interconnect path */ @@ -57,6 +57,7 @@ struct qcom_scm { u64 dload_mode_addr; =20 struct qcom_tzmem_pool *mempool; + unsigned int wq_cnt; }; =20 struct qcom_scm_current_perm_info { @@ -2118,6 +2119,28 @@ static int qcom_scm_fill_irq_fwspec_params(struct ir= q_fwspec *fwspec, u32 virq) return 0; } =20 +static int qcom_scm_query_waitq_count(struct qcom_scm *scm) +{ + int ret; + struct qcom_scm_desc desc =3D { + .svc =3D QCOM_SCM_SVC_WAITQ, + .cmd =3D QCOM_SCM_WAITQ_GET_INFO, + .owner =3D ARM_SMCCC_OWNER_SIP + }; + struct qcom_scm_res res; + + if (!__qcom_scm_is_call_available(scm->dev, QCOM_SCM_SVC_WAITQ, QCOM_SCM_= WAITQ_GET_INFO)) { + dev_info(scm->dev, "Multi-waitqueue support unavailable\n"); + return 1; + } + + ret =3D qcom_scm_call_atomic(scm->dev, &desc, &res); + if (ret) + return ret; + + return res.result[0] & GENMASK(7, 0); +} + static int qcom_scm_get_waitq_irq(void) { int ret; @@ -2149,42 +2172,40 @@ static int qcom_scm_get_waitq_irq(void) return ret; } =20 -static int qcom_scm_assert_valid_wq_ctx(u32 wq_ctx) +static struct completion *qcom_scm_get_completion(u32 wq_ctx) { - /* FW currently only supports a single wq_ctx (zero). - * TODO: Update this logic to include dynamic allocation and lookup of - * completion structs when FW supports more wq_ctx values. - */ - if (wq_ctx !=3D 0) { - dev_err(__scm->dev, "Firmware unexpectedly passed non-zero wq_ctx\n"); - return -EINVAL; - } + struct completion *wq; =20 - return 0; + if (WARN_ON_ONCE(wq_ctx >=3D __scm->wq_cnt)) + return ERR_PTR(-EINVAL); + + wq =3D &__scm->waitq[wq_ctx]; + + return wq; } =20 int qcom_scm_wait_for_wq_completion(u32 wq_ctx) { - int ret; + struct completion *wq; =20 - ret =3D qcom_scm_assert_valid_wq_ctx(wq_ctx); - if (ret) - return ret; + wq =3D qcom_scm_get_completion(wq_ctx); + if (IS_ERR(wq)) + return PTR_ERR(wq); =20 - wait_for_completion(&__scm->waitq_comp); + wait_for_completion(wq); =20 return 0; } =20 static int qcom_scm_waitq_wakeup(unsigned int wq_ctx) { - int ret; + struct completion *wq; =20 - ret =3D qcom_scm_assert_valid_wq_ctx(wq_ctx); - if (ret) - return ret; + wq =3D qcom_scm_get_completion(wq_ctx); + if (IS_ERR(wq)) + return PTR_ERR(wq); =20 - complete(&__scm->waitq_comp); + complete(wq); =20 return 0; } @@ -2260,6 +2281,7 @@ static int qcom_scm_probe(struct platform_device *pde= v) struct qcom_tzmem_pool_config pool_config; struct qcom_scm *scm; int irq, ret; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73e25a9a308sm3868948b3a.136.2025.04.25.16.48.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Apr 2025 16:48:10 -0700 (PDT) From: Unnathi Chalicheemala Date: Fri, 25 Apr 2025 16:48:03 -0700 Subject: [PATCH v6 3/3] firmware: qcom_scm: Check for waitq state in wait_for_wq_completion() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250425-multi_waitq_scm-v6-3-cba8ca5a6d03@oss.qualcomm.com> References: <20250425-multi_waitq_scm-v6-0-cba8ca5a6d03@oss.qualcomm.com> In-Reply-To: <20250425-multi_waitq_scm-v6-0-cba8ca5a6d03@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@oss.qualcomm.com, Prasad Sodagudi , Satya Durga Srinivasu Prabhala , Trilok Soni , Unnathi Chalicheemala X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1745624885; l=956; i=unnathi.chalicheemala@oss.qualcomm.com; s=20240514; h=from:subject:message-id; bh=gwwTPMyq05pjTkKOQrslTYp8aVG/FQQzoFZPwY0uOew=; b=0CAPlycTtrHQjH6dpC9Sdnb9RW1CnD6mYUNayot61XtWt57KYcFiLU7eYQ6KnMoHBBYP18axg e2GNFHyEQhwDP6GZwlGtLFvVF7BGPj7iGY9+Jq776+O1DnCXYXdrONp X-Developer-Key: i=unnathi.chalicheemala@oss.qualcomm.com; a=ed25519; pk=o+hVng49r5k2Gc/f9xiwzvR3y1q4kwLOASwo+cFowXI= X-Proofpoint-GUID: onuzu49xmoNK5dnroFAc15Nn0MALp-Cs X-Proofpoint-ORIG-GUID: onuzu49xmoNK5dnroFAc15Nn0MALp-Cs X-Authority-Analysis: v=2.4 cv=Fv0F/3rq c=1 sm=1 tr=0 ts=680c1f3c cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=EUspDBNiAAAA:8 a=X2av7gLQQKfhQ01XcpoA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI1MDE3MiBTYWx0ZWRfX7N7kzGJrW0y6 d8FeygITWCydtGl9+uzvSXaEvdaRbuHOPOY1Co8FB2a/fqAAs7Jo2gYBB+HxnRfy/z3GRAhWe5N +wVifLr6RabNV19oUDVH//dITv+i66QauJEQpfRIeAKvvPV0UZZhaKX3rhbXpOlDrMYfs2FnlJV s1Kc3wULGYJ5OkQljJ1gaaCyDuQDa0zU9PI7DXwT5MtlZR8zoDnb6MliJZlXhcF1JehI1ZgZQdn GFVdWaTABCtPEXkrreCsx5ykWuhw/oVZ+L8IoNGTR2tLyL2ZrYp8TEGljq52+iCkaD/6EVs52jd A7AxzGhdBIZiGaotMW3mWyK8suqWr72uw2OOq3dlylwRr0ecJRGO9B6gbajwmG9LqPx49cusvFK PMr9P7B2aLTc94DL2H04JP2bqdj1Xv0lEVZPpfsaIMQRHt/puVCzsWvv4k+r4vZtP/et+MCB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-25_07,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 malwarescore=0 mlxlogscore=892 priorityscore=1501 suspectscore=0 adultscore=0 bulkscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504250172 Modify wait_for_wq_completion() to check if task is in idle state using wait_for_completion_state(). This allows for detecting when waitq contexts are in idle state and propagates it to __scm_smc_do(), which is beneficial when task is idle and waiting for a kick to accept new requests. Signed-off-by: Unnathi Chalicheemala --- drivers/firmware/qcom/qcom_scm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index 9f8db13ef1ce14cc324fa9f0abf5c6a97ceb7b8b..a03c18fadd9c6ca6ab5fcd5e386= 834dcc3663eb8 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -2192,7 +2192,7 @@ int qcom_scm_wait_for_wq_completion(u32 wq_ctx) if (IS_ERR(wq)) return PTR_ERR(wq); =20 - wait_for_completion(wq); + wait_for_completion_state(wq, TASK_IDLE); =20 return 0; } --=20 2.34.1