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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54e7ccb7c99sm539164e87.218.2025.04.25.02.51.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Apr 2025 02:51:59 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 25 Apr 2025 12:51:53 +0300 Subject: [PATCH v4 3/7] drm/msm/mdp4: register the LVDS PLL as a clock provider Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250425-fd-mdp4-lvds-v4-3-6b212160b44c@oss.qualcomm.com> References: <20250425-fd-mdp4-lvds-v4-0-6b212160b44c@oss.qualcomm.com> In-Reply-To: <20250425-fd-mdp4-lvds-v4-0-6b212160b44c@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3936; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=p1IT7slnVG8OxIiWvFIYnjVg2GsFl620wCCz7LSey7Y=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoC1s5zHFbFUsFBUaPCTVFVTZYS/OOWyjMl5RFl LJ56EsTJsiJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaAtbOQAKCRCLPIo+Aiko 1SmgB/kBSZl7DR5mdH319Q7IjDuxugjrvDTqfN0OW7Hax/kXdA6o9r1/XNhMlAR3p76mdAzj7vD JLuiAtSJeYXUSdUis6xvxhWP+5HyqGlF9U1c9+A9BoZ3TS+OsWez1z6CKhEMVHdq1haPKc6aBTC OugfsPPtzCA0ynJhnJ/+snE4r6gOk1XhQe2U67A6mEz78aanZkgrbHq1wce4GeEKBNoL2ABlv9M zz5o3lB3R4Ddq7M5JlyQJP84JKNcZ1Qg9/nlNNk8/LH1sGkOisMuROp2pPWfR4orL99WxQ2/1jH tQhpFJ0in5sE972LvIgawuejazSBoeXVvOqmRocjy4SS4zmW X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI1MDA3MSBTYWx0ZWRfXxEXPxTxesz5L nMm7b5hVlzn883uMD/GeZJmndNzXmsMhiGywre4Eca364f+CRDekkPEfUICP3aARP7MKGL4xOsN N3RB4u5uCLv/lREimtgCClcMPtvVnYxxVhXvM14wQxi4AgORuO9erkB3SkcMYEdYWN3kkaWHl0T CpbNMoTP4/I6M5IqBevwR0hgRbA+Wh3Gn0Ss8nBJU6daKXD1MlHXt91Gldw4NwowNGSxGwsRkI6 XePOeqx3xj+3qBQk4n3N4AEnSurZV0F8bPm/JwG/r5Dw/IkCuxC5QF2sJx1tC0UcURGaR2aJ1Ny 1QTP8K3Y7m2sr8VygvoV4h1PfrP26a8udDRu0Wspl7Mn8AbnBwc+zmPCRiWt3e7d2u23nyaT74q Oray3kRS5VkRb4ikbvSYMMRp0/S+3vNdJArM/UdEwQ7jrmxKC1Vr+33QdhB3BO6aDlHXDm35 X-Proofpoint-GUID: PXDyBepszcuLpTEaxXBW3QeIdwETFbAi X-Authority-Analysis: v=2.4 cv=B/S50PtM c=1 sm=1 tr=0 ts=680b5b41 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=TDJnK0Sta0nlXdS-8S8A:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: PXDyBepszcuLpTEaxXBW3QeIdwETFbAi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-25_02,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=948 lowpriorityscore=0 bulkscore=0 impostorscore=0 suspectscore=0 mlxscore=0 priorityscore=1501 phishscore=0 malwarescore=0 spamscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504250071 From: Dmitry Baryshkov The LVDS/LCDC controller uses pixel clock coming from the multimedia controller (mmcc) rather than using the PLL directly. Stop using LVDS PLL directly and register it as a clock provider. Use lcdc_clk as a pixel clock for the LCDC. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h | 2 +- drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c | 3 +- drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c | 45 ++++++++++++++++---= ---- 3 files changed, 34 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h b/drivers/gpu/drm/msm= /disp/mdp4/mdp4_kms.h index 142ccb68b435263f91ba1ab27676e426d43e5d84..3d7ffd874e0d234f450f6170e62= 3f87572456757 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h @@ -207,6 +207,6 @@ static inline struct drm_encoder *mdp4_dsi_encoder_init= (struct drm_device *dev) } #endif =20 -struct clk *mpd4_lvds_pll_init(struct drm_device *dev); +struct clk *mpd4_get_lcdc_clock(struct drm_device *dev); =20 #endif /* __MDP4_KMS_H__ */ diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c b/drivers/gp= u/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c index 8bbc7fb881d599e7d309cc61bda83697fecd253a..8694e5d7d3f012070c72214df06= 3a6488b2ef707 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c @@ -380,8 +380,7 @@ struct drm_encoder *mdp4_lcdc_encoder_init(struct drm_d= evice *dev, =20 drm_encoder_helper_add(encoder, &mdp4_lcdc_encoder_helper_funcs); =20 - /* TODO: do we need different pll in other cases? */ - mdp4_lcdc_encoder->lcdc_clk =3D mpd4_lvds_pll_init(dev); + mdp4_lcdc_encoder->lcdc_clk =3D mpd4_get_lcdc_clock(dev); if (IS_ERR(mdp4_lcdc_encoder->lcdc_clk)) { DRM_DEV_ERROR(dev->dev, "failed to get lvds_clk\n"); return ERR_CAST(mdp4_lcdc_encoder->lcdc_clk); diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c b/drivers/gpu/dr= m/msm/disp/mdp4/mdp4_lvds_pll.c index ab8c0c187fb2cd05e26f5019244af15f1b2470c8..df2bbd475cc2a11da20ac07be8e= 757527ef41ae8 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c @@ -133,29 +133,48 @@ static struct clk_init_data pll_init =3D { .num_parents =3D ARRAY_SIZE(mpd4_lvds_pll_parents), }; =20 -struct clk *mpd4_lvds_pll_init(struct drm_device *dev) +static struct clk_hw *mpd4_lvds_pll_init(struct drm_device *dev) { struct mdp4_lvds_pll *lvds_pll; - struct clk *clk; int ret; =20 lvds_pll =3D devm_kzalloc(dev->dev, sizeof(*lvds_pll), GFP_KERNEL); - if (!lvds_pll) { - ret =3D -ENOMEM; - goto fail; - } + if (!lvds_pll) + return ERR_PTR(-ENOMEM); =20 lvds_pll->dev =3D dev; =20 lvds_pll->pll_hw.init =3D &pll_init; - clk =3D devm_clk_register(dev->dev, &lvds_pll->pll_hw); - if (IS_ERR(clk)) { - ret =3D PTR_ERR(clk); - goto fail; + ret =3D devm_clk_hw_register(dev->dev, &lvds_pll->pll_hw); + if (ret) + return ERR_PTR(ret); + + ret =3D devm_of_clk_add_hw_provider(dev->dev, of_clk_hw_simple_get, &lvds= _pll->pll_hw); + if (ret) + return ERR_PTR(ret); + + return &lvds_pll->pll_hw; +} + +struct clk *mpd4_get_lcdc_clock(struct drm_device *dev) +{ + struct clk_hw *hw; + struct clk *clk; + + + /* TODO: do we need different pll in other cases? */ + hw =3D mpd4_lvds_pll_init(dev); + if (IS_ERR(hw)) { + DRM_DEV_ERROR(dev->dev, "failed to register LVDS PLL\n"); + return ERR_CAST(hw); } =20 - return clk; + clk =3D devm_clk_get(dev->dev, "lcdc_clk"); + if (clk =3D=3D ERR_PTR(-ENOENT)) { + drm_warn(dev, "can't get LCDC clock, using PLL directly\n"); =20 -fail: - return ERR_PTR(ret); + return devm_clk_hw_get_clk(dev->dev, hw, "lcdc_clk"); + } + + return clk; } --=20 2.39.5