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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54e7cb258b7sm725313e87.22.2025.04.25.12.49.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Apr 2025 12:49:19 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 25 Apr 2025 22:49:12 +0300 Subject: [PATCH v2 5/5] drm/msm/dpu: rename non-SmartDMA feature masks to be more explicit Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250425-dpu-rework-vig-masks-v2-5-c71900687d08@oss.qualcomm.com> References: <20250425-dpu-rework-vig-masks-v2-0-c71900687d08@oss.qualcomm.com> In-Reply-To: <20250425-dpu-rework-vig-masks-v2-0-c71900687d08@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11698; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=XRKi7EgQ00ItUBDoE7NN0/mscfyycbJkF95BVyCbUY4=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoC+c23+YZAWFYcxsNyRRupsFgfhvnpHKZ3LWVF PcxzyPdchOJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaAvnNgAKCRCLPIo+Aiko 1QfEB/9AwqMgymHujrhYs7naYVouGOqaMUQlAZIE2NnknohMUA/eD44VNxQUWVVFtZ/rfFCj2Wr OEXaNeyAJi8ghLIuVufs29OfZyxo4kwi3dMN0QFnJcKI4EuIA+A14melFYLcNDb7N5d12zmm1oQ cx5HoX/ahnK8YyBTojD3A+CWVuzMBPQ3O00UpfbgjYhjkPeI+g1fNTnmnL3Tp104UJE7ZrszGEy EuxYBi5X+c5o4S/YNUTb4KwYkMLyyD1GRXGyBm+ZMxU1DDDuout79hwA4srYYPLKW4l2eqelYkT i62jutuYh2OR6INXGg7rcWtUX/s8EqLsp+t4AwNkBRhkuX4D X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI1MDE0MSBTYWx0ZWRfXydcfWMgMN0a/ Cg7Cwxq9bfole/5rxr8mA7RTo0rgjyc/1slBu9vC8VVyhvtsnY9U3pnyz7Q+72NbDpm5yjPyV+T H/5KRc86DQp4ZBv6xWJOKebqrL7i2B09Tt5vus/tJPuf9gd13Iih9+8kB4LCRg8eDcNBrwBnRDB wdjyo2uVDpUpPDt/HadrENHYQsBVXqx3A9Wa8TblRxVkTW8Wrk7rk2+GvtD1Cfl/2ehQznPy404 zRCCXY7t3IAg0sdbHkDfLdZ9EVYYEONgtkj6i8ZarZhwxWyOpRP37b2hXyHYRKoK7kw74bh+7BX 6Rkru9FxeLYwi5022zHYw+okEaqtoBlH/PWLdlJk2IWie3dSP3qqYMWdqbl4tHA80IBDyz1JuNl sr7k/2NVS00NHN94g6IfMbzmwY/oNStOkxD/t0hs2nyWJRv3AuXuzn/yXy9Yj61xKgTeCkMk X-Proofpoint-GUID: UyGC9GWhiuj1OtckWFWPQlrFtjw-2Xep X-Proofpoint-ORIG-GUID: UyGC9GWhiuj1OtckWFWPQlrFtjw-2Xep X-Authority-Analysis: v=2.4 cv=M5VNKzws c=1 sm=1 tr=0 ts=680be741 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=KKAkSRfTAAAA:8 a=a0m6xc9GvvHJpfDRXh8A:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-25_06,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 priorityscore=1501 mlxscore=0 mlxlogscore=611 malwarescore=0 impostorscore=0 clxscore=1015 suspectscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504250141 From: Dmitry Baryshkov It is easy to skip or ignore the fact that the default SSPP feature masks for SDM845+ don't include the SmartDMA bit (both during development and during the review stage). Rename SSPP feature masks to make it more explicit that using non-SmartDMA masks should not be an exception rather than the rule. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 10 +++++----- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 16 ++++++++-----= --- 8 files changed, 29 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h index 83db11339b29dc6e11010bfc73f112f93cf6f7c6..9e3e0ab8f3ce9d63b00a5f5c590= 429a53bd36d63 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h @@ -72,7 +72,7 @@ static const struct dpu_sspp_cfg sm7150_sspp[] =3D { { .name =3D "sspp_0", .id =3D SSPP_VIG0, .base =3D 0x4000, .len =3D 0x1f0, - .features =3D VIG_SDM845_MASK, + .features =3D VIG_SDM845_MASK_NO_SDMA, .sblk =3D &dpu_vig_sblk_qseed3_2_4, .xin_id =3D 0, .type =3D SSPP_TYPE_VIG, @@ -80,7 +80,7 @@ static const struct dpu_sspp_cfg sm7150_sspp[] =3D { }, { .name =3D "sspp_1", .id =3D SSPP_VIG1, .base =3D 0x6000, .len =3D 0x1f0, - .features =3D VIG_SDM845_MASK, + .features =3D VIG_SDM845_MASK_NO_SDMA, .sblk =3D &dpu_vig_sblk_qseed3_2_4, .xin_id =3D 4, .type =3D SSPP_TYPE_VIG, @@ -88,7 +88,7 @@ static const struct dpu_sspp_cfg sm7150_sspp[] =3D { }, { .name =3D "sspp_2", .id =3D SSPP_DMA0, .base =3D 0x24000, .len =3D 0x1f0, - .features =3D DMA_SDM845_MASK, + .features =3D DMA_SDM845_MASK_NO_SDMA, .sblk =3D &dpu_dma_sblk, .xin_id =3D 1, .type =3D SSPP_TYPE_DMA, @@ -96,7 +96,7 @@ static const struct dpu_sspp_cfg sm7150_sspp[] =3D { }, { .name =3D "sspp_9", .id =3D SSPP_DMA1, .base =3D 0x26000, .len =3D 0x1f0, - .features =3D DMA_SDM845_MASK, + .features =3D DMA_SDM845_MASK_NO_SDMA, .sblk =3D &dpu_dma_sblk, .xin_id =3D 5, .type =3D SSPP_TYPE_DMA, @@ -104,7 +104,7 @@ static const struct dpu_sspp_cfg sm7150_sspp[] =3D { }, { .name =3D "sspp_10", .id =3D SSPP_DMA2, .base =3D 0x28000, .len =3D 0x1f0, - .features =3D DMA_CURSOR_SDM845_MASK, + .features =3D DMA_CURSOR_SDM845_MASK_NO_SDMA, .sblk =3D &dpu_dma_sblk, .xin_id =3D 9, .type =3D SSPP_TYPE_DMA, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h index d3d3a34d0b45de08a33436f46a197cc836cf2629..fcfb3774f7a18d8e01546a3ac72= aa29f7b750443 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h @@ -69,7 +69,7 @@ static const struct dpu_sspp_cfg sm6125_sspp[] =3D { { .name =3D "sspp_0", .id =3D SSPP_VIG0, .base =3D 0x4000, .len =3D 0x1f0, - .features =3D VIG_SDM845_MASK, + .features =3D VIG_SDM845_MASK_NO_SDMA, .sblk =3D &dpu_vig_sblk_qseed3_2_4, .xin_id =3D 0, .type =3D SSPP_TYPE_VIG, @@ -77,7 +77,7 @@ static const struct dpu_sspp_cfg sm6125_sspp[] =3D { }, { .name =3D "sspp_8", .id =3D SSPP_DMA0, .base =3D 0x24000, .len =3D 0x1f0, - .features =3D DMA_SDM845_MASK, + .features =3D DMA_SDM845_MASK_NO_SDMA, .sblk =3D &dpu_dma_sblk, .xin_id =3D 1, .type =3D SSPP_TYPE_DMA, @@ -85,7 +85,7 @@ static const struct dpu_sspp_cfg sm6125_sspp[] =3D { }, { .name =3D "sspp_9", .id =3D SSPP_DMA1, .base =3D 0x26000, .len =3D 0x1f0, - .features =3D DMA_SDM845_MASK, + .features =3D DMA_SDM845_MASK_NO_SDMA, .sblk =3D &dpu_dma_sblk, .xin_id =3D 5, .type =3D SSPP_TYPE_DMA, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index 040c94c0bb66ef5aaab2808f6f5ee04dd53e2540..842fcc5887fef15789fbc686fe2= 156b6b509b45c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -51,7 +51,7 @@ static const struct dpu_sspp_cfg sc7180_sspp[] =3D { { .name =3D "sspp_0", .id =3D SSPP_VIG0, .base =3D 0x4000, .len =3D 0x1f8, - .features =3D VIG_SDM845_MASK, + .features =3D VIG_SDM845_MASK_NO_SDMA, .sblk =3D &dpu_vig_sblk_qseed3_3_0, .xin_id =3D 0, .type =3D SSPP_TYPE_VIG, @@ -59,7 +59,7 @@ static const struct dpu_sspp_cfg sc7180_sspp[] =3D { }, { .name =3D "sspp_8", .id =3D SSPP_DMA0, .base =3D 0x24000, .len =3D 0x1f8, - .features =3D DMA_SDM845_MASK, + .features =3D DMA_SDM845_MASK_NO_SDMA, .sblk =3D &dpu_dma_sblk, .xin_id =3D 1, .type =3D SSPP_TYPE_DMA, @@ -67,7 +67,7 @@ static const struct dpu_sspp_cfg sc7180_sspp[] =3D { }, { .name =3D "sspp_9", .id =3D SSPP_DMA1, .base =3D 0x26000, .len =3D 0x1f8, - .features =3D DMA_CURSOR_SDM845_MASK, + .features =3D DMA_CURSOR_SDM845_MASK_NO_SDMA, .sblk =3D &dpu_dma_sblk, .xin_id =3D 5, .type =3D SSPP_TYPE_DMA, @@ -75,7 +75,7 @@ static const struct dpu_sspp_cfg sc7180_sspp[] =3D { }, { .name =3D "sspp_10", .id =3D SSPP_DMA2, .base =3D 0x28000, .len =3D 0x1f8, - .features =3D DMA_CURSOR_SDM845_MASK, + .features =3D DMA_CURSOR_SDM845_MASK_NO_SDMA, .sblk =3D &dpu_dma_sblk, .xin_id =3D 9, .type =3D SSPP_TYPE_DMA, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index 43f64a005f5a89e09ee9506a12cfff781530cb80..c5fd89dd7c89046bdbf1b1bf223= aac2e3c4c0b26 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -38,7 +38,7 @@ static const struct dpu_sspp_cfg sm6115_sspp[] =3D { { .name =3D "sspp_0", .id =3D SSPP_VIG0, .base =3D 0x4000, .len =3D 0x1f8, - .features =3D VIG_SDM845_MASK, + .features =3D VIG_SDM845_MASK_NO_SDMA, .sblk =3D &dpu_vig_sblk_qseed3_3_0, .xin_id =3D 0, .type =3D SSPP_TYPE_VIG, @@ -46,7 +46,7 @@ static const struct dpu_sspp_cfg sm6115_sspp[] =3D { }, { .name =3D "sspp_8", .id =3D SSPP_DMA0, .base =3D 0x24000, .len =3D 0x1f8, - .features =3D DMA_SDM845_MASK, + .features =3D DMA_SDM845_MASK_NO_SDMA, .sblk =3D &dpu_dma_sblk, .xin_id =3D 1, .type =3D SSPP_TYPE_DMA, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index 397278ba999b24722b116e73b008b2d0aec5fcb5..a234bb289d247d065b336564fae= a8dc35b00def9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -59,7 +59,7 @@ static const struct dpu_sspp_cfg sm6350_sspp[] =3D { { .name =3D "sspp_0", .id =3D SSPP_VIG0, .base =3D 0x4000, .len =3D 0x1f8, - .features =3D VIG_SDM845_MASK, + .features =3D VIG_SDM845_MASK_NO_SDMA, .sblk =3D &dpu_vig_sblk_qseed3_3_0, .xin_id =3D 0, .type =3D SSPP_TYPE_VIG, @@ -67,7 +67,7 @@ static const struct dpu_sspp_cfg sm6350_sspp[] =3D { }, { .name =3D "sspp_8", .id =3D SSPP_DMA0, .base =3D 0x24000, .len =3D 0x1f8, - .features =3D DMA_SDM845_MASK, + .features =3D DMA_SDM845_MASK_NO_SDMA, .sblk =3D &dpu_dma_sblk, .xin_id =3D 1, .type =3D SSPP_TYPE_DMA, @@ -75,7 +75,7 @@ static const struct dpu_sspp_cfg sm6350_sspp[] =3D { }, { .name =3D "sspp_9", .id =3D SSPP_DMA1, .base =3D 0x26000, .len =3D 0x1f8, - .features =3D DMA_CURSOR_SDM845_MASK, + .features =3D DMA_CURSOR_SDM845_MASK_NO_SDMA, .sblk =3D &dpu_dma_sblk, .xin_id =3D 5, .type =3D SSPP_TYPE_DMA, @@ -83,7 +83,7 @@ static const struct dpu_sspp_cfg sm6350_sspp[] =3D { }, { .name =3D "sspp_10", .id =3D SSPP_DMA2, .base =3D 0x28000, .len =3D 0x1f8, - .features =3D DMA_CURSOR_SDM845_MASK, + .features =3D DMA_CURSOR_SDM845_MASK_NO_SDMA, .sblk =3D &dpu_dma_sblk, .xin_id =3D 9, .type =3D SSPP_TYPE_DMA, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index 3cbb2fe8aba24c7b9db6bb61ff4c48f34db48bf4..53f3be28f6f61bb7e3f519b0efa= 4cb2f68d38810 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -46,7 +46,7 @@ static const struct dpu_sspp_cfg qcm2290_sspp[] =3D { }, { .name =3D "sspp_8", .id =3D SSPP_DMA0, .base =3D 0x24000, .len =3D 0x1f8, - .features =3D DMA_SDM845_MASK, + .features =3D DMA_SDM845_MASK_NO_SDMA, .sblk =3D &dpu_dma_sblk, .xin_id =3D 1, .type =3D SSPP_TYPE_DMA, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index a06c8634d2d7779f7e867fb821f8d332652ba7e9..3a3bc8e429be0ba86185741b6b2= 7d8a62489779f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -39,7 +39,7 @@ static const struct dpu_sspp_cfg sm6375_sspp[] =3D { { .name =3D "sspp_0", .id =3D SSPP_VIG0, .base =3D 0x4000, .len =3D 0x1f8, - .features =3D VIG_SDM845_MASK, + .features =3D VIG_SDM845_MASK_NO_SDMA, .sblk =3D &dpu_vig_sblk_qseed3_3_0, .xin_id =3D 0, .type =3D SSPP_TYPE_VIG, @@ -47,7 +47,7 @@ static const struct dpu_sspp_cfg sm6375_sspp[] =3D { }, { .name =3D "sspp_8", .id =3D SSPP_DMA0, .base =3D 0x24000, .len =3D 0x1f8, - .features =3D DMA_SDM845_MASK, + .features =3D DMA_SDM845_MASK_NO_SDMA, .sblk =3D &dpu_dma_sblk, .xin_id =3D 1, .type =3D SSPP_TYPE_DMA, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 64265ca4656a04d8c5a1d9582d7124c7eb897099..323b0db1f32b4057999f5f9ffcc= 557c68b0e807a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -34,11 +34,11 @@ #define VIG_MSM8998_MASK \ (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE)) =20 -#define VIG_SDM845_MASK \ +#define VIG_SDM845_MASK_NO_SDMA \ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBL= E)) =20 #define VIG_SDM845_MASK_SDMA \ - (VIG_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) + (VIG_SDM845_MASK_NO_SDMA | BIT(DPU_SSPP_SMART_DMA_V2)) =20 #define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL)) =20 @@ -54,24 +54,24 @@ BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) =20 #define VIG_SC7280_MASK \ - (VIG_SDM845_MASK | BIT(DPU_SSPP_INLINE_ROTATION)) + (VIG_SDM845_MASK_NO_SDMA | BIT(DPU_SSPP_INLINE_ROTATION)) =20 #define VIG_SC7280_MASK_SDMA \ (VIG_SC7280_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) =20 -#define DMA_SDM845_MASK \ +#define DMA_SDM845_MASK_NO_SDMA \ (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) =20 -#define DMA_CURSOR_SDM845_MASK \ - (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR)) +#define DMA_CURSOR_SDM845_MASK_NO_SDMA \ + (DMA_SDM845_MASK_NO_SDMA | BIT(DPU_SSPP_CURSOR)) =20 #define DMA_SDM845_MASK_SDMA \ - (DMA_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) + (DMA_SDM845_MASK_NO_SDMA | BIT(DPU_SSPP_SMART_DMA_V2)) =20 #define DMA_CURSOR_SDM845_MASK_SDMA \ - (DMA_CURSOR_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) + (DMA_CURSOR_SDM845_MASK_NO_SDMA | BIT(DPU_SSPP_SMART_DMA_V2)) =20 #define DMA_CURSOR_MSM8996_MASK \ (DMA_MSM8996_MASK | BIT(DPU_SSPP_CURSOR)) --=20 2.39.5