From nobody Sat Feb 7 21:24:24 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0870158858; Thu, 24 Apr 2025 13:47:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745502467; cv=none; b=OwPRw6bINabIPSTLRfqrHB1GHltPSOUFARdnBbhbBELDFXmrYZUujmNMWr3I6YZdboezEXrBA+Dqw21Ts8VHxe6fV9eLufDJ3n4raDfE3P03I4G7suiYfjqkrLW4CfD1kfcgaaNQWGYnarjmK5WWRh1eV5sAkIVSd0bG5mUBjDs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745502467; c=relaxed/simple; bh=ZPdaq82mG+JRpwl8l1yKHK/Uc2NMfolvwuRLY9459r8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DXHndqCd1wRVkKwJ3AM3qjfthnj2otNPdIBh8p3u0q9zMwSz+jC8S+/YQ5CiSkyXyY92CCnh+qR2pmGQoaXEsz63tzha65dYBbzjDjsK0lLzCQlYi3tWji+m+f5L1Y/DoubJqYdi+ENt0ZlTMxxJ5WZTqnXegjAxX3NMwypTiOM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=cQqSZRys; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="cQqSZRys" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1745502466; x=1777038466; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZPdaq82mG+JRpwl8l1yKHK/Uc2NMfolvwuRLY9459r8=; b=cQqSZRysIUliate2XS55Ea0zlQy4OM33WoiwFLHMpflUEweUawcrMDSZ TAOv6KqTzLmIK7G5zrUt5wbhc5VdEStWMPTJUQ0m9EMjCapqfzk8DlbFf zN59+q9N+nGu8AWGtc0LQQjas9TJjeRVvaE6tdr2n0Qt0MmCK9tHzUCY9 Zte8x+SOSmbl+xmM/r78fJrjTL2c2L0vOel/fNdIBUWXDK7hZbf0cu/xx R7nGFuSRsCLvR4MNegiLCmck3z3xUbNeGnd76i5ZvTg8I3c+wx1ZyRI1j M/wP10ZAIvFlm3huZBy2gH43hTJOtBX62d38rb/dvpJPtLTi74JrY5cvY A==; X-CSE-ConnectionGUID: pulsRbC4QQyZLPACZcqicw== X-CSE-MsgGUID: vChKJFoFR+u0GYOL9q3oAg== X-IronPort-AV: E=McAfee;i="6700,10204,11413"; a="58508196" X-IronPort-AV: E=Sophos;i="6.15,236,1739865600"; d="scan'208";a="58508196" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2025 06:47:44 -0700 X-CSE-ConnectionGUID: B3bl+cM3SfCd8QF0CBMMlQ== X-CSE-MsgGUID: +/T9vHjtQbKiDTGombv6NQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,236,1739865600"; d="scan'208";a="137718958" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by fmviesa004.fm.intel.com with ESMTP; 24 Apr 2025 06:47:44 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org, irogers@google.com, linux-kernel@vger.kernel.org Cc: Kan Liang , Luo Gengkun , stable@vger.kernel.org Subject: [PATCH V2 1/5] perf/x86/intel: Only check the group flag for X86 leader Date: Thu, 24 Apr 2025 06:47:14 -0700 Message-Id: <20250424134718.311934-2-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20250424134718.311934-1-kan.liang@linux.intel.com> References: <20250424134718.311934-1-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kan Liang A warning in intel_pmu_lbr_counters_reorder() may be triggered by below perf command. perf record -e "{cpu-clock,cycles/call-graph=3D"lbr"/}" -- sleep 1 It's because the group is mistakenly treated as a branch counter group. The hw.flags of the leader are used to determine whether a group is a branch counters group. However, the hw.flags is only available for a hardware event. The field to store the flags is a union type. For a software event, it's a hrtimer. The corresponding bit may be set if the leader is a software event. For a branch counter group and other groups that have a group flag (e.g., topdown, PEBS counters snapshotting, and ACR), the leader must be a X86 event. Check the X86 event before checking the flag. The patch only fixes the issue for the branch counter group. The following patch will fix the other groups. There may be an alternative way to fix the issue by moving the hw.flags out of the union type. It should work for now. But it's still possible that the flags will be used by other types of events later. As long as that type of event is used as a leader, a similar issue will be triggered. So the alternative way is dropped. Fixes: 33744916196b ("perf/x86/intel: Support branch counters logging") Reported-by: Luo Gengkun Closes: https://lore.kernel.org/lkml/20250412091423.1839809-1-luogengkun@hu= aweicloud.com/ Signed-off-by: Kan Liang Cc: stable@vger.kernel.org --- arch/x86/events/perf_event.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 902bc42a6cfe..4fc61a09c30e 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -110,9 +110,16 @@ static inline bool is_topdown_event(struct perf_event = *event) return is_metric_event(event) || is_slots_event(event); } =20 +int is_x86_event(struct perf_event *event); + +static inline bool check_leader_group(struct perf_event *leader, int flags) +{ + return is_x86_event(leader) ? !!(leader->hw.flags & flags) : false; +} + static inline bool is_branch_counters_group(struct perf_event *event) { - return event->group_leader->hw.flags & PERF_X86_EVENT_BRANCH_COUNTERS; + return check_leader_group(event->group_leader, PERF_X86_EVENT_PEBS_CNTR); } =20 static inline bool is_pebs_counter_event_group(struct perf_event *event) @@ -1129,7 +1136,6 @@ static struct perf_pmu_format_hybrid_attr format_attr= _hybrid_##_name =3D {\ .pmu_type =3D _pmu, \ } =20 -int is_x86_event(struct perf_event *event); struct pmu *x86_get_pmu(unsigned int cpu); extern struct x86_pmu x86_pmu __read_mostly; =20 --=20 2.38.1 From nobody Sat Feb 7 21:24:24 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D50215B102 for ; Thu, 24 Apr 2025 13:47:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745502467; cv=none; b=KBq/zXy9DVApx8litQagerkeIhnjcRla/eDLKt6jbdJNQf4IYe33WZqV2XbCNjOjQjp1RiuVQFBhh+9xi1EQM3mpYVRg0PZM29FAkXz7SYMFs5tZaV1WaMrjr04fJTHQTDe4vTDbLPPTDnwWVtrun/TO+rGU4JqxiSLIGJvfkkU= ARC-Message-Signature: i=1; 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d="scan'208";a="137718960" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by fmviesa004.fm.intel.com with ESMTP; 24 Apr 2025 06:47:44 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org, irogers@google.com, linux-kernel@vger.kernel.org Cc: Kan Liang Subject: [PATCH V2 2/5] perf/x86/intel: Check the X86 leader for pebs_counter_event_group Date: Thu, 24 Apr 2025 06:47:15 -0700 Message-Id: <20250424134718.311934-3-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20250424134718.311934-1-kan.liang@linux.intel.com> References: <20250424134718.311934-1-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kan Liang The PEBS counters snapshotting group also requires a group flag in the leader. The leader must be a X86 event. Fixes: e02e9b0374c3 ("perf/x86/intel: Support PEBS counters snapshotting") Signed-off-by: Kan Liang --- arch/x86/events/perf_event.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 4fc61a09c30e..fd409d70e568 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -124,7 +124,7 @@ static inline bool is_branch_counters_group(struct perf= _event *event) =20 static inline bool is_pebs_counter_event_group(struct perf_event *event) { - return event->group_leader->hw.flags & PERF_X86_EVENT_PEBS_CNTR; + return check_leader_group(event->group_leader, PERF_X86_EVENT_PEBS_CNTR); } =20 static inline bool is_acr_event_group(struct perf_event *event) --=20 2.38.1 From nobody Sat Feb 7 21:24:24 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A427317FAC2 for ; Thu, 24 Apr 2025 13:47:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745502468; cv=none; b=lotRlL2/+iAaOR1ZZk0dgZPHiZPVdqIrv7TbQWYNLENiYcKkOORWGnYX4FyYWpVboxTe0XmEw52eiU5XhaYqbLeZ9lQB7kQkU7rr42LCRaYcKCeHZeO0yISKgNKDcKj0Ag69is6gd6h/rPwKO89fzmAFMgM38Dg+B6BICOUJ4Is= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745502468; c=relaxed/simple; bh=e8tbn6z5Wzsvp7tPLqFuVaLqmzq6ZAwM8Ecg0eO97Fo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RkQCg01yruWPjWxgPi/1h4oVH6yZWnvHHPX2RwzbeT/qQyh41CJTwAJHpmERUnwVEA2CLUzHvtOZUu8sZ1BZi6ZFriafXkN1zWlotZYPy+ppw4dzBdQPTblGjZxnFxnAbcJ5o6Bo3oPhSSY/Z33YTHltuyYpkdmU0TzkQzOkIKI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Cbb0+Xfe; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Cbb0+Xfe" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1745502466; x=1777038466; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=e8tbn6z5Wzsvp7tPLqFuVaLqmzq6ZAwM8Ecg0eO97Fo=; b=Cbb0+Xfeb8iiuV1Z9Fku8x0+jSPCJvXLK4vy3R2LQOI/qBipbv4Mt0y8 b1QkZgzvgtEE5XXVcjX4A9Aty3iAoAnrZxNl9+wuhQMFOathJ56QOllTc CuktOBDPh9s/w+u9Mqe6QRQkBSyCJyOh3Dw+GltpCG3yg03mhjdEE3Lcb jwa0hXJB2+7jno9wRWhmlDoUtA1tygpCyEDjUKZ8xor7Q/RFSTyU47Zc3 sGPBaOZG3IHJcUqHoMXnVb7UeGeNftMPn9ZisI2Z0CRY21JLR2S9Z/8W8 dP7QIAT5iZFYRg6ewf5GQrQThzerRgq9Jc2qayYg5OCWCAISdI7kyMvbq Q==; X-CSE-ConnectionGUID: DiC64V1FRyqgI4P1TVOY7g== X-CSE-MsgGUID: 8ah2dR6AQSGKnVPfUi/k5g== X-IronPort-AV: E=McAfee;i="6700,10204,11413"; a="58508208" X-IronPort-AV: E=Sophos;i="6.15,236,1739865600"; d="scan'208";a="58508208" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2025 06:47:44 -0700 X-CSE-ConnectionGUID: eEJ7OrSaT0ea8OUV7Prh9g== X-CSE-MsgGUID: 6/Ui7NI2QR+uSegqm47ZuQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,236,1739865600"; d="scan'208";a="137718963" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by fmviesa004.fm.intel.com with ESMTP; 24 Apr 2025 06:47:44 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org, irogers@google.com, linux-kernel@vger.kernel.org Cc: Kan Liang Subject: [PATCH V2 3/5] perf/x86/intel: Check the X86 leader for ACR group Date: Thu, 24 Apr 2025 06:47:16 -0700 Message-Id: <20250424134718.311934-4-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20250424134718.311934-1-kan.liang@linux.intel.com> References: <20250424134718.311934-1-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kan Liang The auto counter reload group also requires a group flag in the leader. The leader must be a X86 event. Signed-off-by: Kan Liang --- arch/x86/events/perf_event.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index fd409d70e568..bac252ba3da6 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -129,7 +129,7 @@ static inline bool is_pebs_counter_event_group(struct p= erf_event *event) =20 static inline bool is_acr_event_group(struct perf_event *event) { - return event->group_leader->hw.flags & PERF_X86_EVENT_ACR; + return check_leader_group(event->group_leader, PERF_X86_EVENT_ACR); } =20 struct amd_nb { --=20 2.38.1 From nobody Sat Feb 7 21:24:24 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8107518DB34 for ; Thu, 24 Apr 2025 13:47:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745502469; cv=none; b=N0w189YavigCk0zhMgkQKDm0fIozqQmmr/anrBIZxTNcGe/GXsInFl4wj8TYLs2yjtXjepM4QdvblToceyEMl8BY+1xJCOT8YlkmACM2xRExR3arrpWupKQC3rslsreSRWJfCvIvXpzpvLjlJjB8eu+r0XrLSxIothOKVCblwNk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745502469; c=relaxed/simple; bh=ZdZJog103PjdTsGGO0CcUxRKRwD5l2l9ILCbQlG9Z9k=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NypzyNsbsEXHeRz1XQaWtUNUHPIwaO1b8yGit44Jw1MtkIKiGGcRvcIuExZmH6aJloJQW+Z8dZSl/SCBfFICGSByOL+OXfR4g9N8LyIvDsifg6XoHWoJXgZL1nQ7E9gSMpvSzaVy2jWsu5++b5U0KI3VLLGMlle/UYY1N/RG/Ss= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=NmeD5rY2; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="NmeD5rY2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1745502467; x=1777038467; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZdZJog103PjdTsGGO0CcUxRKRwD5l2l9ILCbQlG9Z9k=; b=NmeD5rY2AQvGWNZz9iRnAzx3MVvi4YiI443E36RcM0ox3SJjbRyKy+KC 4DUmNWF/fYm1Wk29+WShhEdI//v4MI0fVntQAfO9MkLUYqDJoiNlpWj4N Md+LfCUotaUKk7IwRLcloUpV/opm6d0dvrrkbtM7C06zaZS+0lF0L88HR emkWFiT/eECrh7p08VJepzLSIxgVMLZo3BMd7CAXrJglF4HIGMFTgymKk HRhZwQvVWKjdhmPMhwO2IxSVQqnXSpJ6PFlOH4qHQRcoVqiN6brJwikWz DbnlZlmZQFBrWI3tBzhAPti6FYZtybo4DdD9rIku3vHLRijZDMg4r0lfg A==; X-CSE-ConnectionGUID: eDXpCZUFSsa8s1iYVuUxcQ== X-CSE-MsgGUID: 1OXxS6feT+asAs7eI6qlaw== X-IronPort-AV: E=McAfee;i="6700,10204,11413"; a="58508213" X-IronPort-AV: E=Sophos;i="6.15,236,1739865600"; d="scan'208";a="58508213" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2025 06:47:44 -0700 X-CSE-ConnectionGUID: Vw3gdJ8hQBSZce4R1O6gcw== X-CSE-MsgGUID: IibXVzH4S2uQcRdGse4OjA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,236,1739865600"; d="scan'208";a="137718966" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by fmviesa004.fm.intel.com with ESMTP; 24 Apr 2025 06:47:44 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org, irogers@google.com, linux-kernel@vger.kernel.org Cc: Kan Liang Subject: [PATCH V2 4/5] perf/x86: Optimize the is_x86_event Date: Thu, 24 Apr 2025 06:47:17 -0700 Message-Id: <20250424134718.311934-5-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20250424134718.311934-1-kan.liang@linux.intel.com> References: <20250424134718.311934-1-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kan Liang The current is_x86_event has to go through the hybrid_pmus list to find the matched pmu, then check if it's a X86 PMU and a X86 event. It's not necessary. The X86 PMU has a unique type ID on a non-hybrid machine, and a unique capability type. They are good enough to do the check. Signed-off-by: Kan Liang --- arch/x86/events/core.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index b0ef07d14c83..43053ddd7073 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -757,15 +757,16 @@ void x86_pmu_enable_all(int added) =20 int is_x86_event(struct perf_event *event) { - int i; - - if (!is_hybrid()) - return event->pmu =3D=3D &pmu; - - for (i =3D 0; i < x86_pmu.num_hybrid_pmus; i++) { - if (event->pmu =3D=3D &x86_pmu.hybrid_pmu[i].pmu) - return true; - } + /* + * For a non-hybrid platforms, the type of X86 pmu is + * always PERF_TYPE_RAW. + * For a hybrid platform, the PERF_PMU_CAP_EXTENDED_HW_TYPE + * is a unique capability for the X86 PMU. + * Use them to detect a X86 event. + */ + if (event->pmu->type =3D=3D PERF_TYPE_RAW || + event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_HW_TYPE) + return true; =20 return false; } --=20 2.38.1 From nobody Sat Feb 7 21:24:24 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0F5C1917C2 for ; Thu, 24 Apr 2025 13:47:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745502469; cv=none; b=ngeVd5JlxmILUaCOrl8RbR8Dw+QGS4Lm5EvbxQSkwmmZUPZ4pokWJfKNOVd5EjqGgg7JcmfalwQ+4znhp2dtO4jIDJbyrM0M1EguT7Cga1Y7srgO1iWY3o4NUQcxqvfULjkSbniHxIoMWY23fHGwS/PZ+1lRbsRcNXgZUVbCm64= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745502469; c=relaxed/simple; bh=xmC+569+8AF2+9YjjAU1ncRPqd/+A4Q4tbSC+zlSkTA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XS76N/s+MOsy2hFlm0c702WJW114dVo3PSiQyX7FkGNBgPp9O3Z3hvo2nQCwZ8KE4549a6q9Qp6u5U13euRtSPu3aYaCcRf14tpfUOxX4V58sOum98GMUKjAhG+Mso3CO4Xhf0IBFEld5QS+awQlDTS+27Z8XO2SzSHJc+Bgnys= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=k5/nUQGs; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="k5/nUQGs" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1745502468; x=1777038468; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xmC+569+8AF2+9YjjAU1ncRPqd/+A4Q4tbSC+zlSkTA=; b=k5/nUQGsv3v306nY4P2i2X8HSvXbuPdzNSAfM/G0ZJp5feS/6q0SgSHo 9zQevawJhoRMEXXOUl5D2w2Ew2uGmoApzB3ZKKOgeFypH+jXtAGaBNS33 TaKM/NPMeKI2Q0U0ftTHuQmUh44GCxVz+LWz1xsa12Jp0rJxveRFs9wRe RdCujcX8L/oRFhbJziy2pHGUCv8cNEliBHouTSv3bvbZwhzaTT3w4Kk3k VpgJ0vJGosPLLJTTWvrojNO9JvkMfb5rlzYjXWC294jEQOWkm2moANdua FWzIzK4QtlP7734eSN9ZIZ8R6ZPyCsTKz+7g5wmP4Cl7TtoPiM18TH/T+ Q==; X-CSE-ConnectionGUID: qPlZ19QoQC+CPeuO5Q8MjQ== X-CSE-MsgGUID: DpLqQ+NGS1SeZzF8P0sD7w== X-IronPort-AV: E=McAfee;i="6700,10204,11413"; a="58508220" X-IronPort-AV: E=Sophos;i="6.15,236,1739865600"; d="scan'208";a="58508220" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2025 06:47:45 -0700 X-CSE-ConnectionGUID: JySRxCZ3SvmiqKVATCXWIA== X-CSE-MsgGUID: iFtgBmQYTRKQZUZoXprd2A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,236,1739865600"; d="scan'208";a="137718967" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by fmviesa004.fm.intel.com with ESMTP; 24 Apr 2025 06:47:45 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org, irogers@google.com, linux-kernel@vger.kernel.org Cc: Kan Liang Subject: [PATCH V2 5/5] perf/x86/intel/ds: Fix counter backwards of non-precise events counters-snapshotting Date: Thu, 24 Apr 2025 06:47:18 -0700 Message-Id: <20250424134718.311934-6-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20250424134718.311934-1-kan.liang@linux.intel.com> References: <20250424134718.311934-1-kan.liang@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kan Liang The counter backwards may be observed in the PMI handler when counters-snapshotting some non-precise events in the freq mode. For the non-precise events, it's possible the counters-snapshotting records a positive value for an overflowed PEBS event. Then the HW auto-reload mechanism reset the counter to 0 immediately. Because the pebs_event_reset is cleared in the freq mode, which doesn't set the PERF_X86_EVENT_AUTO_RELOAD. In the PMI handler, 0 will be read rather than the positive value recorded in the counters-snapshotting record. The counters-snapshotting case has to be specially handled. Since the event value has been updated when processing the counters-snapshotting record, only needs to set the new period for the counter via x86_pmu_set_period(). Fixes: e02e9b0374c3 ("perf/x86/intel: Support PEBS counters snapshotting") Signed-off-by: Kan Liang --- arch/x86/events/intel/ds.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 486881fe162e..83ffbfdf4982 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -2376,8 +2376,25 @@ __intel_pmu_pebs_last_event(struct perf_event *event, */ intel_pmu_save_and_restart_reload(event, count); } - } else - intel_pmu_save_and_restart(event); + } else { + /* + * For a non-precise event, it's possible the + * counters-snapshotting records a positive value for the + * overflowed event. Then the HW auto-reload mechanism + * reset the counter to 0 immediately, because the + * pebs_event_reset is cleared if the PERF_X86_EVENT_AUTO_RELOAD + * is not set. The counter backwards may be observed in a + * PMI handler. + * + * Since the event value has been updated when processing the + * counters-snapshotting record, only needs to set the new + * period for the counter. + */ + if (is_pebs_counter_event_group(event)) + static_call(x86_pmu_set_period)(event); + else + intel_pmu_save_and_restart(event); + } } =20 static __always_inline void --=20 2.38.1