From nobody Mon Feb 9 13:37:22 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB25E27D79B for ; Thu, 24 Apr 2025 13:38:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745501923; cv=none; b=X9tMVaTEbDVx/51g69ii3viJDz8wljsxq3rBcyt+QwAGjH3JrWgp5jYqlaw980BQfEmGyPMd9X1Xh52ea7mY/m8vGHrcYEN3/MYjGSKYuYrj0xjtXs/CpJV8mTzbzo49YsiWh1961ZWePSw97JthhQFhmUAYwAr5dUfAfXLwZZ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745501923; c=relaxed/simple; bh=U92c1PJ/qLawtJ9HQpghJXWeJo5jiaoFnblKRYCvOD4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=o0jLdYx7/xBqDDP1kgP9wKf6SpeGafDOgm1rlD4YXQO6cZGaFPpRCvk/W1KOVknKkjtEtjLnW+DeWOv+2X5REpI+1WV2rvMwcGl+CF9yKV1AYU8e8S0JHndMYbCp9DtsAQTikZhJPoUZY6qh/boPlHfKVP15i7NHr+XRoABT7kc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Z3vSaQ2d; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Z3vSaQ2d" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1745501922; x=1777037922; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=U92c1PJ/qLawtJ9HQpghJXWeJo5jiaoFnblKRYCvOD4=; b=Z3vSaQ2dMXem2FIgH2tzuY+pBAgAIsMS1TpyzH5J7Xovih2duSqINJYJ GHCBtA8Xv3chtAdahSgOa4V32yt599hSWhJUWX3II/YJGKzFkZC4XJzf1 4p27Q9KdBVtFmLsgBljq0Rg39IeZAJZZIw5ETuBPDvCZ3DXqaQPb2rvsP uY2VRE0ZuvA3qBALQCVtAGzk8eJlO8caCfOoN4l+4C14Lqi1D94Ath3yT VUfTJ9FUrnBcpoawANMvTVxQKUOktnUFECnR27AK4zkJ7f04rsTfKntS+ Ii84hn8dvK/suatC2VjzI86nK8ySXqCNoEYyXQyb5WVnQSnd2UAxYeqEs A==; X-CSE-ConnectionGUID: iL1lHeQwQ06D53wEeIRZkw== X-CSE-MsgGUID: P/wkFm6BSjG1oEkLhT5ilg== X-IronPort-AV: E=McAfee;i="6700,10204,11413"; a="46368227" X-IronPort-AV: E=Sophos;i="6.15,236,1739865600"; d="scan'208";a="46368227" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2025 06:38:41 -0700 X-CSE-ConnectionGUID: dLQ3W9H9QtyAoFBQOZR9Lg== X-CSE-MsgGUID: j5OuZRBGT2O6X22YgGNeJA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,236,1739865600"; d="scan'208";a="136701452" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2025 06:38:36 -0700 From: Alexander Usyskin To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Rodrigo Vivi , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula , Joonas Lahtinen , Tvrtko Ursulin , Karthik Poosa Cc: Reuven Abliyev , Oren Weil , linux-mtd@lists.infradead.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Alexander Usyskin Subject: [PATCH v9 12/12] drm/xe/nvm: add support for non-posted erase Date: Thu, 24 Apr 2025 16:25:36 +0300 Message-ID: <20250424132536.3043825-13-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250424132536.3043825-1-alexander.usyskin@intel.com> References: <20250424132536.3043825-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Reuven Abliyev Erase command is slow on discrete graphics storage and may overshot PCI completion timeout. BMG introduces the ability to have non-posted erase. Add driver support for non-posted erase with polling for erase completion. Reviewed-by: Rodrigo Vivi Acked-by: Rodrigo Vivi Signed-off-by: Reuven Abliyev Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/xe/xe_nvm.c | 25 +++++++++++++++++ drivers/mtd/devices/mtd_intel_dg.c | 43 ++++++++++++++++++++++++++++-- include/linux/intel_dg_nvm_aux.h | 2 ++ 3 files changed, 68 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_nvm.c b/drivers/gpu/drm/xe/xe_nvm.c index 8aec20bc629a..dd91f2e37661 100644 --- a/drivers/gpu/drm/xe/xe_nvm.c +++ b/drivers/gpu/drm/xe/xe_nvm.c @@ -14,7 +14,15 @@ #include "xe_sriov.h" =20 #define GEN12_GUNIT_NVM_BASE 0x00102040 +#define GEN12_DEBUG_NVM_BASE 0x00101018 + +#define GEN12_CNTL_PROTECTED_NVM_REG 0x0010100C + #define GEN12_GUNIT_NVM_SIZE 0x80 +#define GEN12_DEBUG_NVM_SIZE 0x4 + +#define NVM_NON_POSTED_ERASE_CHICKEN_BIT BIT(13) + #define HECI_FW_STATUS_2_NVM_ACCESS_MODE BIT(3) =20 static const struct intel_dg_nvm_region regions[INTEL_DG_NVM_REGIONS] =3D { @@ -28,6 +36,16 @@ static void xe_nvm_release_dev(struct device *dev) { } =20 +static bool xe_nvm_non_posted_erase(struct xe_device *xe) +{ + struct xe_gt *gt =3D xe_root_mmio_gt(xe); + + if (xe->info.platform !=3D XE_BATTLEMAGE) + return false; + return !(xe_mmio_read32(>->mmio, XE_REG(GEN12_CNTL_PROTECTED_NVM_REG)) & + NVM_NON_POSTED_ERASE_CHICKEN_BIT); +} + static bool xe_nvm_writable_override(struct xe_device *xe) { struct xe_gt *gt =3D xe_root_mmio_gt(xe); @@ -85,6 +103,7 @@ void xe_nvm_init(struct xe_device *xe) nvm =3D xe->nvm; =20 nvm->writable_override =3D xe_nvm_writable_override(xe); + nvm->non_posted_erase =3D xe_nvm_non_posted_erase(xe); nvm->bar.parent =3D &pdev->resource[0]; nvm->bar.start =3D GEN12_GUNIT_NVM_BASE + pdev->resource[0].start; nvm->bar.end =3D nvm->bar.start + GEN12_GUNIT_NVM_SIZE - 1; @@ -92,6 +111,12 @@ void xe_nvm_init(struct xe_device *xe) nvm->bar.desc =3D IORES_DESC_NONE; nvm->regions =3D regions; =20 + nvm->bar2.parent =3D &pdev->resource[0]; + nvm->bar2.start =3D GEN12_DEBUG_NVM_BASE + pdev->resource[0].start; + nvm->bar2.end =3D nvm->bar2.start + GEN12_DEBUG_NVM_SIZE - 1; + nvm->bar2.flags =3D IORESOURCE_MEM; + nvm->bar2.desc =3D IORES_DESC_NONE; + aux_dev =3D &nvm->aux_dev; =20 aux_dev->name =3D "nvm"; diff --git a/drivers/mtd/devices/mtd_intel_dg.c b/drivers/mtd/devices/mtd_i= ntel_dg.c index 9f4bb15a03b8..3016e9cab00e 100644 --- a/drivers/mtd/devices/mtd_intel_dg.c +++ b/drivers/mtd/devices/mtd_intel_dg.c @@ -28,6 +28,9 @@ struct intel_dg_nvm { struct mtd_info mtd; struct mutex lock; /* region access lock */ void __iomem *base; + void __iomem *base2; + bool non_posted_erase; + size_t size; unsigned int nregions; struct { @@ -44,6 +47,7 @@ struct intel_dg_nvm { #define NVM_VALSIG_REG 0x00000010 #define NVM_ADDRESS_REG 0x00000040 #define NVM_REGION_ID_REG 0x00000044 +#define NVM_DEBUG_REG 0x00000000 /* * [15:0]-Erase size =3D 0x0010 4K 0x0080 32K 0x0100 64K * [23:16]-Reserved @@ -75,6 +79,9 @@ struct intel_dg_nvm { #define NVM_FREG_ADDR_SHIFT 12 #define NVM_FREG_MIN_REGION_SIZE 0xFFF =20 +#define NVM_NON_POSTED_ERASE_DONE BIT(23) +#define NVM_NON_POSTED_ERASE_DONE_ITER 3000 + static inline void idg_nvm_set_region_id(struct intel_dg_nvm *nvm, u8 regi= on) { iowrite32((u32)region, nvm->base + NVM_REGION_ID_REG); @@ -370,11 +377,30 @@ idg_erase(struct intel_dg_nvm *nvm, u8 region, loff_t= from, u64 len, u64 *fail_a { u64 i; const u32 block =3D 0x10; + u32 reg; + u32 iter =3D 0; void __iomem *base =3D nvm->base; + void __iomem *base2 =3D nvm->base2; =20 for (i =3D 0; i < len; i +=3D SZ_4K) { iowrite32(from + i, base + NVM_ADDRESS_REG); iowrite32(region << 24 | block, base + NVM_ERASE_REG); + if (nvm->non_posted_erase) { + /* Wait for Erase Done */ + reg =3D ioread32(base2 + NVM_DEBUG_REG); + while (!(reg & NVM_NON_POSTED_ERASE_DONE) && + ++iter < NVM_NON_POSTED_ERASE_DONE_ITER) { + msleep(10); + reg =3D ioread32(base2 + NVM_DEBUG_REG); + } + if (reg & NVM_NON_POSTED_ERASE_DONE) { + /* Clear Erase Done */ + iowrite32(reg, base2 + NVM_DEBUG_REG); + } else { + *fail_addr =3D from + i; + return -ETIME; + } + } /* Since the writes are via sguint * we cannot do back to back erases. */ @@ -383,7 +409,8 @@ idg_erase(struct intel_dg_nvm *nvm, u8 region, loff_t f= rom, u64 len, u64 *fail_a return len; } =20 -static int intel_dg_nvm_init(struct intel_dg_nvm *nvm, struct device *devi= ce) +static int intel_dg_nvm_init(struct intel_dg_nvm *nvm, struct device *devi= ce, + bool non_posted_erase) { int ret; unsigned int i, n; @@ -443,7 +470,10 @@ static int intel_dg_nvm_init(struct intel_dg_nvm *nvm,= struct device *device) n++; } =20 + nvm->non_posted_erase =3D non_posted_erase; + dev_dbg(device, "Registered %d regions\n", n); + dev_dbg(device, "Non posted erase %d\n", nvm->non_posted_erase); =20 /* Need to add 1 to the amount of memory * so it is reported as an even block @@ -778,7 +808,16 @@ static int intel_dg_mtd_probe(struct auxiliary_device = *aux_dev, goto err; } =20 - ret =3D intel_dg_nvm_init(nvm, device); + if (invm->non_posted_erase) { + nvm->base2 =3D devm_ioremap_resource(device, &invm->bar2); + if (IS_ERR(nvm->base2)) { + dev_err(device, "base2 mmio not mapped\n"); + ret =3D PTR_ERR(nvm->base2); + goto err; + } + } + + ret =3D intel_dg_nvm_init(nvm, device, invm->non_posted_erase); if (ret < 0) { dev_err(device, "cannot initialize nvm %d\n", ret); goto err; diff --git a/include/linux/intel_dg_nvm_aux.h b/include/linux/intel_dg_nvm_= aux.h index 68df634c994c..bee25dfc6982 100644 --- a/include/linux/intel_dg_nvm_aux.h +++ b/include/linux/intel_dg_nvm_aux.h @@ -17,7 +17,9 @@ struct intel_dg_nvm_region { struct intel_dg_nvm_dev { struct auxiliary_device aux_dev; bool writable_override; + bool non_posted_erase; struct resource bar; + struct resource bar2; const struct intel_dg_nvm_region *regions; }; =20 --=20 2.43.0