From nobody Tue Feb 10 17:53:05 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68BC31E0DB3; Thu, 24 Apr 2025 06:24:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745475900; cv=none; b=djgdL7U8Pb0SB9iL2SgcdmIOTM60nzxWnKa17zwOP3jUg+FKWp/GaGdrUakV4wwskhyZcVWVJhoBPxCiPVwVkF5Z25MQz02G+kxozuMOJlswSqIzW3bIEzfQyFz02tta4Um9alFRmsuv3v68BILaRveTJH2uLkiZ4LIalvmvy9M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745475900; c=relaxed/simple; bh=exdwzMT2XPAsj7mwik3tgQyZ5TnoBOkJBqtp9yXU0qE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=u/DMdyvTjE/nmY1Obj04Mb/BNw/FJ+RkPCJ5ORnUlYL2WKUcP8J4urdBdAPiFKhOrc/CCqDY7gptrI1bnGxmGkMbLZ5y4Wiho/1edDk7bkFdKX+rDM0r7gtp8hIiwuUhov11T3q5laGBosv8vu7NA6KPEYUww9EPTIjxou4aC4k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=IsCZ2Diw; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="IsCZ2Diw" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 53O0F5ww016952; Thu, 24 Apr 2025 06:24:39 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=yopZIdGlEPS e7UYtTlLskvuAdG4hKGeUMFs3e0xIP9k=; b=IsCZ2Diwbad+at0dd6W6Zy7pWMJ Rp8qDnENL5CZzHJ4iJkMQ73IFG/QzUgtehXg8mBsxPQapfAni13aVAGDcVqqjg0p cCgtkc+DD4+8VOtpcog3HaPvo85M10T/0/ra/PARj6NKY055I/8+4eTBKx6ATPOa YlU0Ps9MM9GzbfE5N7gWIMVKuSSEGe/C+g8Byob8G0yaQnBcIeQK4QHb3s4dySq7 jRdWERs5LrGpWVWwPt76Tk66uez4O6IICyUUUjSChmuW3ffW9lLt8R+gd8QhTBOo 38RDZ9TdHNUP2LDtnPAkHlaAm3u2Es+pPwUDIRxJfL0qckmExZ/uIfW51Rw== Received: from apblrppmta02.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 466jh14du1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 24 Apr 2025 06:24:39 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 53O6OZHu003920; Thu, 24 Apr 2025 06:24:35 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 4644wn00yc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 24 Apr 2025 06:24:35 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 53O6OZ4x003871; Thu, 24 Apr 2025 06:24:35 GMT Received: from hu-devc-hyd-u22-c.qualcomm.com (hu-amakhija-hyd.qualcomm.com [10.213.99.91]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 53O6OYTs003864 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 24 Apr 2025 06:24:35 +0000 Received: by hu-devc-hyd-u22-c.qualcomm.com (Postfix, from userid 4090850) id B3860598; Thu, 24 Apr 2025 11:54:33 +0530 (+0530) From: Ayushi Makhija To: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ayushi Makhija , robdclark@gmail.com, dmitry.baryshkov@oss.qualcomm.com, sean@poorly.run, marijn.suijten@somainline.org, andersson@kernel.org, robh@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, konradybcio@kernel.org, conor+dt@kernel.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, quic_abhinavk@quicinc.com, quic_rajeevny@quicinc.com, quic_vproddut@quicinc.com, quic_jesszhan@quicinc.com, Dmitry Baryshkov Subject: [PATCH v5 04/11] drm/msm/dsi: add DSI PHY configuration on SA8775P Date: Thu, 24 Apr 2025 11:54:24 +0530 Message-Id: <20250424062431.2040692-5-quic_amakhija@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250424062431.2040692-1-quic_amakhija@quicinc.com> References: <20250424062431.2040692-1-quic_amakhija@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: p0XY_t2kG4WacKI3NuCL003OWtm9p__P X-Authority-Analysis: v=2.4 cv=OY6YDgTY c=1 sm=1 tr=0 ts=6809d927 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=XR8D0OoHHMoA:10 a=COk6AnOGAAAA:8 a=VwQbUJbxAAAA:8 a=UZNEAvMi2Rj6Meq9XXQA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: p0XY_t2kG4WacKI3NuCL003OWtm9p__P X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI0MDA0MCBTYWx0ZWRfXxKj/nX/ajFS7 UPYrzEjFoOaWFlOPecAQWyaY9OkNh5wOgtKuR2gKzY/TAdQ95c1Yj7DzWimEwfg6bQLZj/nQtF5 +JffMHnoWE+lNai4ZoINlarn8UKeXgv0vS8Lc7gCnlvquvWuNrchSR1kHHc1Ndh8S3X9T+WEwB4 LmEDwhXeWjPBlkJEbTGCBJL7tN2snrYsEW/q4ri9303LzH8m0eAhSrzn1b1WANQDKceuUq5JNre +/Iu5OaYX7SFJu7LjpuSO3GKDpWX309XLOCeLvPA7Wm/XMvoHuFOai1L7rOF5xT4wV0G/3ijZfg obdnw8w7Oh5YnUhi+z0KxwnAWEyKnYYOxLrkoBfgA0zuJTWMVjiF9/nXmOSRy3xpM9/gI+5ojbx tpc0rBNjhJ9kp6aN+3Ev2ovmtpPSKaSLL1YB+sLlNmMKkqOY123f1FameooJ27b1g4MAa0lt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.680,FMLib:17.12.80.40 definitions=2025-04-24_02,2025-04-22_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 mlxscore=0 clxscore=1015 malwarescore=0 mlxlogscore=999 phishscore=0 priorityscore=1501 spamscore=0 adultscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504240040 Content-Type: text/plain; charset="utf-8" The SA8775P SoC uses the 5nm (v4.2) DSI PHY driver with different enable regulator load. Signed-off-by: Ayushi Makhija Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 27 +++++++++++++++++++++++ 3 files changed, 30 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.c index c0bcc6828963..92be08ac5f65 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -581,6 +581,8 @@ static const struct of_device_id dsi_phy_dt_match[] =3D= { .data =3D &dsi_phy_7nm_cfgs }, { .compatible =3D "qcom,dsi-phy-7nm-8150", .data =3D &dsi_phy_7nm_8150_cfgs }, + { .compatible =3D "qcom,sa8775p-dsi-phy-5nm", + .data =3D &dsi_phy_5nm_8775p_cfgs }, { .compatible =3D "qcom,sc7280-dsi-phy-7nm", .data =3D &dsi_phy_7nm_7280_cfgs }, { .compatible =3D "qcom,sm6375-dsi-phy-7nm", diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.h index 1925418d9999..8d9a541f9f09 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -59,6 +59,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8775p_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs; =20 diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/ms= m/dsi/phy/dsi_phy_7nm.c index a92decbee5b5..2bfe6f921c7e 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -1147,6 +1147,10 @@ static const struct regulator_bulk_data dsi_phy_7nm_= 37750uA_regulators[] =3D { { .supply =3D "vdds", .init_load_uA =3D 37550 }, }; =20 +static const struct regulator_bulk_data dsi_phy_7nm_48000uA_regulators[] = =3D { + { .supply =3D "vdds", .init_load_uA =3D 48000 }, +}; + static const struct regulator_bulk_data dsi_phy_7nm_98000uA_regulators[] = =3D { { .supply =3D "vdds", .init_load_uA =3D 98000 }, }; @@ -1289,6 +1293,29 @@ const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = =3D { .quirks =3D DSI_PHY_7NM_QUIRK_V4_3, }; =20 +const struct msm_dsi_phy_cfg dsi_phy_5nm_8775p_cfgs =3D { + .has_phy_lane =3D true, + .regulator_data =3D dsi_phy_7nm_48000uA_regulators, + .num_regulators =3D ARRAY_SIZE(dsi_phy_7nm_48000uA_regulators), + .ops =3D { + .enable =3D dsi_7nm_phy_enable, + .disable =3D dsi_7nm_phy_disable, + .pll_init =3D dsi_pll_7nm_init, + .save_pll_state =3D dsi_7nm_pll_save_state, + .restore_pll_state =3D dsi_7nm_pll_restore_state, + .set_continuous_clock =3D dsi_7nm_set_continuous_clock, + }, + .min_pll_rate =3D 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate =3D 5000000000UL, +#else + .max_pll_rate =3D ULONG_MAX, +#endif + .io_start =3D { 0xae94400, 0xae96400 }, + .num_dsi_phy =3D 2, + .quirks =3D DSI_PHY_7NM_QUIRK_V4_2, +}; + const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs =3D { .has_phy_lane =3D true, .regulator_data =3D dsi_phy_7nm_98400uA_regulators, --=20 2.34.1