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Thu, 24 Apr 2025 00:21:34 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22db52163d6sm6240765ad.214.2025.04.24.00.21.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Apr 2025 00:21:34 -0700 (PDT) From: Deepak Gupta Date: Thu, 24 Apr 2025 00:20:37 -0700 Subject: [PATCH v13 22/28] riscv: Add Firmware Feature SBI extensions definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-v5_user_cfi_series-v13-22-971437de586a@rivosinc.com> References: <20250424-v5_user_cfi_series-v13-0-971437de586a@rivosinc.com> In-Reply-To: <20250424-v5_user_cfi_series-v13-0-971437de586a@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, rust-for-linux@vger.kernel.org, Zong Li X-Mailer: b4 0.13.0 From: Cl=C3=A9ment L=C3=A9ger Add necessary SBI definitions to use the FWFT extension. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Zong Li --- arch/riscv/include/asm/sbi.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 3d250824178b..23bfb254e3f4 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -35,6 +35,7 @@ enum sbi_ext_id { SBI_EXT_DBCN =3D 0x4442434E, SBI_EXT_STA =3D 0x535441, SBI_EXT_NACL =3D 0x4E41434C, + SBI_EXT_FWFT =3D 0x46574654, =20 /* Experimentals extensions must lie within this range */ SBI_EXT_EXPERIMENTAL_START =3D 0x08000000, @@ -401,6 +402,31 @@ enum sbi_ext_nacl_feature { =20 #define SBI_NACL_SHMEM_SRET_X(__i) ((__riscv_xlen / 8) * (__i)) #define SBI_NACL_SHMEM_SRET_X_LAST 31 +/* SBI function IDs for FW feature extension */ +#define SBI_EXT_FWFT_SET 0x0 +#define SBI_EXT_FWFT_GET 0x1 + +enum sbi_fwft_feature_t { + SBI_FWFT_MISALIGNED_EXC_DELEG =3D 0x0, + SBI_FWFT_LANDING_PAD =3D 0x1, + SBI_FWFT_SHADOW_STACK =3D 0x2, + SBI_FWFT_DOUBLE_TRAP =3D 0x3, + SBI_FWFT_PTE_AD_HW_UPDATING =3D 0x4, + SBI_FWFT_LOCAL_RESERVED_START =3D 0x5, + SBI_FWFT_LOCAL_RESERVED_END =3D 0x3fffffff, + SBI_FWFT_LOCAL_PLATFORM_START =3D 0x40000000, + SBI_FWFT_LOCAL_PLATFORM_END =3D 0x7fffffff, + + SBI_FWFT_GLOBAL_RESERVED_START =3D 0x80000000, + SBI_FWFT_GLOBAL_RESERVED_END =3D 0xbfffffff, + SBI_FWFT_GLOBAL_PLATFORM_START =3D 0xc0000000, + SBI_FWFT_GLOBAL_PLATFORM_END =3D 0xffffffff, +}; + +#define SBI_FWFT_GLOBAL_FEATURE_BIT (1 << 31) +#define SBI_FWFT_PLATFORM_FEATURE_BIT (1 << 30) + +#define SBI_FWFT_SET_FLAG_LOCK (1 << 0) =20 /* SBI spec version fields */ #define SBI_SPEC_VERSION_DEFAULT 0x1 --=20 2.43.0