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Thu, 24 Apr 2025 06:04:41 -0700 (PDT) From: Krzysztof Kozlowski Date: Thu, 24 Apr 2025 15:04:25 +0200 Subject: [PATCH RFC/WIP 1/4] arm64: dts: qcom: sm8750: Add display (MDSS) with Display CC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-sm8750-display-dts-v1-1-6fb22ca95f38@linaro.org> References: <20250424-sm8750-display-dts-v1-0-6fb22ca95f38@linaro.org> In-Reply-To: <20250424-sm8750-display-dts-v1-0-6fb22ca95f38@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jessica Zhang , Abhinav Kumar , Abel Vesa , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=11528; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=7ugfQMszcHvHRUWtXIg4mzvRmiSjFZ9os0x6k4Z3O4g=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBoCjbjKcAUdLmUVwY3qeJNLFj37nms00KoLQy6I uBru+wRVa+JAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaAo24wAKCRDBN2bmhouD 11YFEACOrK4AtRKf2FXsRwDjMoeHBXPBRo8gMlDVv7TBd7fUwAJojINeN7hZgqtBGNxzTB2a1Xb hnKvq1UeEorY1/EpjfaJrXLaArHEFG2+a/I91PCRfUqIJrV0XVTJX4vriaNSvBxSJ4Dn/OCx+9a QUNHaOpuYPyu/AgW8rWSmValT8bHXB0GOcq2qkePMcTuIECF/egtBsfx92zzkeiTv6tgF1IlS3X cFSjv9tKUvl8qkuUvi0sSO64L2XGIyAGH4rwktc552QtW9EJMj7SX65uDtLR6hjGluZXQXlslVo vnSUrNgKSGw4x4DeREr6+nhq530+ymOYqg5zoqNE1RUu178HhiR9wJ2HcazDw45aQJdw/zY3EPT NvcujWUNbVXIAaUkHSu2SaSInI3lummVCu9bbkJ1RP+XRqJGBD5NO7DstQZq2mW7h9QhgcZ84An JBIVB7RW1vyOrM7LqMwr+HHaojR63SYKklMOwMLYmdpotho8HnYjFCo5gZ3ZgLsW16CgaaZm40m 7o2nfrqjptfZeWdCNrEKeBCw2pZeBK6hKuVvE8F3qptkn1WI73oLt+zfB67xYKcj5OgUtU0kHWb UIyJGlkh24G/rdDmfkbidTcjykIjeQwwjuPyOU6Wgfju+yjB0yzEaWJxM43wnhPz6Ecbp/TbqTY hPC68DgQMZyeg3A== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add device nodes for entire display: MDSS, DPU, DSI, DSI PHYs, DisplayPort and Display Clock Controller. Signed-off-by: Krzysztof Kozlowski --- Bindings (dtbs_check dependency): https://lore.kernel.org/r/20250311-b4-sm8750-display-v4-0-da6b3e959c76@lina= ro.org/ --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 415 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 415 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qco= m/sm8750.dtsi index 30ee98567b6078e8225142f2e13b25b5f35a3038..753b069cab1de636a3b1108747f= 300bec0f33980 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -3,7 +3,9 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ =20 +#include #include +#include #include #include #include @@ -2585,6 +2587,419 @@ data-pins { }; }; =20 + mdss: display-subsystem@ae00000 { + compatible =3D "qcom,sm8750-mdss"; + reg =3D <0x0 0x0ae00000 0x0 0x1000>; + reg-names =3D "mdss"; + + interrupts =3D ; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets =3D <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interconnects =3D <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "mdp0-mem", + "cpu-cfg"; + + power-domains =3D <&dispcc MDSS_GDSC>; + + iommus =3D <&apps_smmu 0x800 0x2>; + + interrupt-controller; + #interrupt-cells =3D <1>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible =3D "qcom,sm8750-dpu"; + reg =3D <0 0x0ae01000 0 0x93000>, + <0 0x0aeb0000 0 0x2008>; + reg-names =3D "mdp", + "vbif"; + + interrupts-extended =3D <&mdss 0>; + + clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dpu_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + + dpu_intf2_out: endpoint { + remote-endpoint =3D <&mdss_dsi1_in>; + }; + }; + + port@2 { + reg =3D <2>; + + dpu_intf0_out: endpoint { + remote-endpoint =3D <&mdss_dp0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-207000000 { + opp-hz =3D /bits/ 64 <207000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-337000000 { + opp-hz =3D /bits/ 64 <337000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-417000000 { + opp-hz =3D /bits/ 64 <417000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-532000000 { + opp-hz =3D /bits/ 64 <532000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz =3D /bits/ 64 <575000000>; + required-opps =3D <&rpmhpd_opp_nom_l1>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible =3D "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0x0 0x0ae94000 0x0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupts-extended =3D <&mdss 4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&dispcc DISP_CC_ESYNC0_CLK>, + <&dispcc DISP_CC_OSC_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus", + "dsi_pll_pixel", + "dsi_pll_byte", + "esync", + "osc", + "byte_src", + "pixel_src"; + + operating-points-v2 =3D <&mdss_dsi_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + phys =3D <&mdss_dsi0_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae95000 { + compatible =3D "qcom,sm8750-dsi-phy-3nm"; + reg =3D <0x0 0x0ae95000 0x0 0x200>, + <0x0 0x0ae95200 0x0 0x280>, + <0x0 0x0ae95500 0x0 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&bi_tcxo_div2>; + clock-names =3D "iface", + "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible =3D "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0x0 0x0ae96000 0x0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupts-extended =3D <&mdss 5>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 =3D <&mdss_dsi_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + phys =3D <&mdss_dsi1_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi1_in: endpoint { + remote-endpoint =3D <&dpu_intf2_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae97000 { + compatible =3D "qcom,sm8750-dsi-phy-3nm"; + reg =3D <0x0 0x0ae97000 0x0 0x200>, + <0x0 0x0ae97200 0x0 0x280>, + <0x0 0x0ae97500 0x0 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", + "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + mdss_dp0: displayport-controller@af54000 { + compatible =3D "qcom,sm8750-dp", "qcom,sm8650-dp"; + reg =3D <0x0 0xaf54000 0x0 0x104>, + <0x0 0xaf54200 0x0 0xc0>, + <0x0 0xaf55000 0x0 0x770>, + <0x0 0xaf56000 0x0 0x9c>, + <0x0 0xaf57000 0x0 0x9c>; + + interrupts-extended =3D <&mdss 12>; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; + clock-names =3D "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + assigned-clock-parents =3D <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + + operating-points-v2 =3D <&dp_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + phys =3D <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; + phy-names =3D "dp"; + + #sound-dai-cells =3D <0>; + + status =3D "disabled"; + + dp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-192000000 { + opp-hz =3D /bits/ 64 <192000000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz =3D /bits/ 64 <540000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz =3D /bits/ 64 <810000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dp0_in: endpoint { + remote-endpoint =3D <&dpu_intf0_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dp0_out: endpoint { + }; + }; + }; + }; + }; + + dispcc: clock-controller@af00000 { + compatible =3D "qcom,sm8750-dispcc"; + reg =3D <0 0x0af00000 0 0x20000>; + + clocks =3D <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, + <0>, /* dp1 */ + <0>, + <0>, /* dp2 */ + <0>, + <0>, /* dp3 */ + <0>; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Enable display on MTP8750 board with Novatek NT37801 panel. Signed-off-by: Krzysztof Kozlowski --- Depends on WIP https://github.com/krzk/linux/tree/b4/sm8750-display-panel for display panel bindings (novatek,nt37801) --- arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 70 +++++++++++++++++++++++++++++= ++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/= qcom/sm8750-mtp.dts index 140a3a36d03008f700bb54ca52f437f81e6c68e2..bd0918e8a7a7e03530eea577c76= 09454fecfdaf7 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -853,6 +853,48 @@ &lpass_vamacro { qcom,dmic-sample-rate =3D <4800000>; }; =20 +&mdss { + status =3D "okay"; +}; + +&mdss_dsi0 { + vdda-supply =3D <&vreg_l3g_1p2>; + + status =3D "okay"; + + panel@0 { + compatible =3D "novatek,nt37801"; + reg =3D <0>; + + reset-gpios =3D <&tlmm 98 GPIO_ACTIVE_LOW>; + + vddio-supply =3D <&vreg_l12b_1p8>; + vci-supply =3D <&vreg_l13b_3p0>; + vdd-supply =3D <&vreg_l11b_1p0>; + + pinctrl-0 =3D <&disp0_reset_n_active>, <&mdp_vsync_active>; + pinctrl-1 =3D <&disp0_reset_n_suspend>, <&mdp_vsync_suspend>; + pinctrl-names =3D "default", "sleep"; + + port { + panel0_in: endpoint { + remote-endpoint =3D <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint =3D <&panel0_in>; + data-lanes =3D <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply =3D <&vreg_l3i_0p88>; + + status =3D "okay"; +}; + &pm8550_flash { status =3D "okay"; =20 @@ -1078,6 +1120,34 @@ spkr_1_sd_n_active: spkr-1-sd-n-active-state { }; =20 &tlmm { + disp0_reset_n_active: disp0-reset-n-active-state { + pins =3D "gpio98"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-disable; + }; + + disp0_reset_n_suspend: disp0-reset-n-suspend-state { + pins =3D "gpio98"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + mdp_vsync_active: mdp-vsync-active-state { + pins =3D "gpio86"; + function =3D "mdp_vsync"; + drive-strength =3D <2>; + bias-pull-down; + }; + + mdp_vsync_suspend: mdp-vsync-suspend-state { + pins =3D "gpio86"; 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Thu, 24 Apr 2025 06:04:44 -0700 (PDT) From: Krzysztof Kozlowski Date: Thu, 24 Apr 2025 15:04:27 +0200 Subject: [PATCH RFC/WIP 3/4] arm64: dts: qcom: sm8750-mtp: Enable USB headset and Type-C altmode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-sm8750-display-dts-v1-3-6fb22ca95f38@linaro.org> References: <20250424-sm8750-display-dts-v1-0-6fb22ca95f38@linaro.org> In-Reply-To: <20250424-sm8750-display-dts-v1-0-6fb22ca95f38@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jessica Zhang , Abhinav Kumar , Abel Vesa , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2233; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; 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Add necessary nodes for proper audio headset support along with USB Type-C altmode and orientation. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 58 +++++++++++++++++++++++++++++= ++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/= qcom/sm8750-mtp.dts index bd0918e8a7a7e03530eea577c7609454fecfdaf7..c3470e1daa6b7f31196645759be= 23fb168ce8eb7 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -53,6 +53,15 @@ wcd939x: audio-codec { vdd-mic-bias-supply =3D <&vreg_bob1>; =20 #sound-dai-cells =3D <1>; + + mode-switch; + orientation-switch; + + port { + wcd_codec_headset_in: endpoint { + remote-endpoint =3D <&wcd_usbss_headset_out>; + }; + }; }; =20 chosen { @@ -220,6 +229,14 @@ port@1 { pmic_glink_ss_in: endpoint { }; }; + + port@2 { + reg =3D <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint =3D <&wcd_usbss_sbu_mux>; + }; + }; }; }; }; @@ -845,6 +862,42 @@ vreg_l7n_3p3: ldo7 { }; }; =20 +&i2c3 { + status =3D "okay"; + + wcd_usbss: typec-mux@e { + compatible =3D "qcom,wcd9395-usbss", "qcom,wcd9390-usbss"; + reg =3D <0xe>; + + vdd-supply =3D <&vreg_l15b_1p8>; + reset-gpios =3D <&tlmm 152 GPIO_ACTIVE_HIGH>; + + mode-switch; + orientation-switch; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + wcd_usbss_sbu_mux: endpoint { + remote-endpoint =3D <&pmic_glink_sbu>; + }; + }; + + port@1 { + reg =3D <1>; + + wcd_usbss_headset_out: endpoint { + remote-endpoint =3D <&wcd_codec_headset_in>; + }; + }; + }; + }; +}; + &lpass_vamacro { pinctrl-0 =3D <&dmic01_default>, <&dmic23_default>; pinctrl-names =3D "default"; @@ -973,6 +1026,11 @@ &pmih0108_eusb2_repeater { vdd3-supply =3D <&vreg_l5b_3p1>; }; =20 +&qup_i2c3_data_clk { + /* Use internal I2C pull-up */ + bias-pull-up =3D <2200>; +}; + &qupv3_1 { status =3D "okay"; }; --=20 2.45.2 From nobody Mon Feb 9 03:20:09 2026 Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA6D5281356 for ; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Hook up DisplayPort parts over Type-C USB on MTP8750. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 8 ++++++++ arch/arm64/boot/dts/qcom/sm8750.dtsi | 2 ++ 2 files changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/= qcom/sm8750-mtp.dts index c3470e1daa6b7f31196645759be23fb168ce8eb7..69a54ac0f85d5ae20d005a09fbf= 8da7d769a9c2e 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -910,6 +910,14 @@ &mdss { status =3D "okay"; }; =20 +&mdss_dp0 { + status =3D "okay"; +}; + +&mdss_dp0_out { + data-lanes =3D <0 1>; +}; + &mdss_dsi0 { vdda-supply =3D <&vreg_l3g_1p2>; =20 diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qco= m/sm8750.dtsi index 753b069cab1de636a3b1108747f300bec0f33980..b20fc5b5bdfab598fc7b9be53ee= f96cc16bc5985 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -2965,6 +2965,7 @@ port@1 { reg =3D <1>; =20 mdss_dp0_out: endpoint { + remote-endpoint =3D <&usb_dp_qmpphy_dp_in>; }; }; }; @@ -3064,6 +3065,7 @@ port@2 { reg =3D <2>; =20 usb_dp_qmpphy_dp_in: endpoint { + remote-endpoint =3D <&mdss_dp0_out>; }; }; }; --=20 2.45.2