From nobody Mon Feb 9 00:53:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8C2C22D7B2; Thu, 24 Apr 2025 10:27:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490431; cv=none; b=SX28LkgCT0JXt2CIXTkZoCI73DEXf3nNYwFKFoW1m6GMsCTooQAMpo6sx7u/bhEMp4Yv5MH+QnktD4jBRHmUyh7zszy/y14nnE1nyTSvu/JHQMhmM57gPEwC/4vADf/KVAPDNeWFaTmCugz6jHqisUh0Slh0cYYW7pX5tp/zPiY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490431; c=relaxed/simple; bh=J4d+23jK1xcMwImyyVNILtAarSzyfyzelW1CaxCFjwc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lMxmgH5OZhrXhU0+xFvuWjKSN5ZevUYles/+JV6w7A5MjA0ovqMbjAbe8iwemOZmaN4APtXJoHdLsVGrgqZ0/eCVgeLTwJcyNvuqkH688CRoxK71AFdC3qYNjThVHEJpZ8n3xrYldDFTwQWT2VsfCjND4eINBtlWW3sOCYCGmmQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=sgnqQgko; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="sgnqQgko" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 650B8C4CEE3; Thu, 24 Apr 2025 10:27:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745490431; bh=J4d+23jK1xcMwImyyVNILtAarSzyfyzelW1CaxCFjwc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=sgnqQgkolXvCAUAVaMDrIlPvEjmlTuL5qCUpb6+DHJOabe51gFynNShfu8X4dEIYf 1iW5OCmBNtzN2u2qpvcQ1e5zwTRcyQMYq6AwWjTOjXw3VolnOP2F6ROc/kjNLeWPdw dlPTfryWu1zzxYyhDaDJfFIq39V23tFhfJ/ZoAkU0mkLSZvCEGlnHujXytPTWwIsjk I4QeH1p3/KzdX+R7Q7VRC39pSk9ROIcF7tlsHNXcwr+B91+5gjGAn1Q8jn3Evmilxt bf7GFWoTyn+EwbqqfP3ELbKO6bYsy19QXHNCHHoWCjOWC0MIPHbfaIvmbwQg0Kt5R6 5DgpNciUSoNOw== From: Lorenzo Pieralisi Date: Thu, 24 Apr 2025 12:25:27 +0200 Subject: [PATCH v2 16/22] arm64: cpucaps: Rename GICv3 CPU interface capability Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-gicv5-host-v2-16-545edcaf012b@kernel.org> References: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> In-Reply-To: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.14.2 In preparation for adding a GICv5 CPU interface capability, rework the existing GICv3 CPUIF capability - change its name and description so that the subsequent GICv5 CPUIF capability can be added with a more consistent naming on top. Suggested-by: Mark Rutland Signed-off-by: Lorenzo Pieralisi Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier --- arch/arm64/kernel/cpufeature.c | 10 +++++----- arch/arm64/tools/cpucaps | 2 +- drivers/irqchip/irq-gic.c | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 9c4d6d552b25cb3a31d1fb267bd73d3f82513e69..cbb49de451f45fbee3100ea01e7= 7b06352bd55ac 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2283,11 +2283,11 @@ static bool can_use_gic_priorities(const struct arm= 64_cpu_capabilities *entry, int scope) { /* - * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU + * ARM64_HAS_GICV3_CPUIF has a lower index, and is a boot CPU * feature, so will be detected earlier. */ - BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <=3D ARM64_HAS_GIC_CPUIF_SYSREGS); - if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS)) + BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <=3D ARM64_HAS_GICV3_CPUIF); + if (!cpus_have_cap(ARM64_HAS_GICV3_CPUIF)) return false; =20 return enable_pseudo_nmi; @@ -2483,8 +2483,8 @@ static const struct arm64_cpu_capabilities arm64_feat= ures[] =3D { .matches =3D has_always, }, { - .desc =3D "GIC system register CPU interface", - .capability =3D ARM64_HAS_GIC_CPUIF_SYSREGS, + .desc =3D "GICv3 CPU interface", + .capability =3D ARM64_HAS_GICV3_CPUIF, .type =3D ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, .matches =3D has_useable_gicv3_cpuif, ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 772c1b008e437ed34cedb1c0f663c4dcea8f6759..860ec49cc0530885c138b7dc7f6= 7d58cd69b2593 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -34,7 +34,7 @@ HAS_GENERIC_AUTH HAS_GENERIC_AUTH_ARCH_QARMA3 HAS_GENERIC_AUTH_ARCH_QARMA5 HAS_GENERIC_AUTH_IMP_DEF -HAS_GIC_CPUIF_SYSREGS +HAS_GICV3_CPUIF HAS_GIC_PRIO_MASKING HAS_GIC_PRIO_RELAXED_SYNC HAS_HCR_NV1 diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 6503573557fdf295bc543b16b64e3e7dd6841321..1269ab8eb726afbb80849fd0626= 12861680cb4d1 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -54,7 +54,7 @@ =20 static void gic_check_cpu_features(void) { - WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_GIC_CPUIF_SYSREGS), + WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_GICV3_CPUIF), TAINT_CPU_OUT_OF_SPEC, "GICv3 system registers enabled, broken firmware!\n"); } --=20 2.48.0