From nobody Sun Feb 8 13:09:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8221C236A88; Thu, 24 Apr 2025 10:25:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490349; cv=none; b=cg07AobY7RzBuHOA5nseZxD5sgzi+JTJgg41DCSCLSjoo9TOFe1vj+2AjVgrq8pWgBA519Fc3uvgAEZYGc+ncnTeCD+S+CyiOJaJi0xyuXdduZNDFusOmpprFTxzEtIBBNItPTR/pe4Evo8rh+Sc44vLGAAjemkduNLabr5BYOA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490349; c=relaxed/simple; bh=KrpKnZNnP5S3kNqOj3SU9Sk96zavEOtbkPyDMRv2nfs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YujizF3ugKXV1yPryan4qFXGgmCpksEdGe3UPks1Sp1xkmUVXckui9brnnUIygJCy46hU7E67xJmGM8SUl9AI1uvhsUDfk3UPzGMdvygT3Cs+36QIvI4UZzDhd+VBoGpc5P2KHOtPlomlzppyZ61+H+k+sIny3awIRk6fOHAaGA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nkKOKn/0; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nkKOKn/0" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 288BFC4CEEB; Thu, 24 Apr 2025 10:25:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745490348; bh=KrpKnZNnP5S3kNqOj3SU9Sk96zavEOtbkPyDMRv2nfs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=nkKOKn/0avpacY5wwrq6VzMcSwrsoupqdHxV/qbsO2pR/SgHQE5vZzpXu/QMjZn7o sd/i9Kpalz6LO32pI34x/pn1u+uAx3tza5CY4Jf+SFLvTH8QpSQKtXwWQ9UYVqDjMj erPFl8jnxFUVCBUlXhYfJSUj3V2V3E50VegBvvsp2+0qB6hwXUiHEB6uQcr+uFBBaP 0WpO/mTzXChVOasiUuVEAkI9o5XR0GXcz9JX/hkVZY/4aI49R2XCfHJT6EL6tUs3Q6 VoOKVaWKqa9/uNbrHv5pAo8fDSKxkQkCMMQVXamjxDM6u0AnlXd397nEAMsngQqFWq cBsFlac01JQVA== From: Lorenzo Pieralisi Date: Thu, 24 Apr 2025 12:25:12 +0200 Subject: [PATCH v2 01/22] dt-bindings: interrupt-controller: Add Arm GICv5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-gicv5-host-v2-1-545edcaf012b@kernel.org> References: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> In-Reply-To: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.14.2 The GICv5 interrupt controller architecture is composed of: - one or more Interrupt Routing Service (IRS) - zero or more Interrupt Translation Service (ITS) - zero or more Interrupt Wire Bridge (IWB) Describe a GICv5 implementation by specifying a top level node corresponding to the GICv5 system component. IRS nodes are added as GICv5 system component children. An ITS is associated with an IRS so ITS nodes are described as IRS children - use the hierarchy explicitly in the device tree to define the association. IWB nodes are described as a separate schema. An IWB is connected to a single ITS, the connection is made explicit through the msi-parent property and therefore is not required to be explicit through a parent-child relationship in the device tree. Signed-off-by: Lorenzo Pieralisi Cc: Conor Dooley Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Marc Zyngier --- .../interrupt-controller/arm,gic-v5-iwb.yaml | 76 ++++++++ .../bindings/interrupt-controller/arm,gic-v5.yaml | 196 +++++++++++++++++= ++++ MAINTAINERS | 7 + 3 files changed, 279 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic= -v5-iwb.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,g= ic-v5-iwb.yaml new file mode 100644 index 0000000000000000000000000000000000000000..b3eb89567b3457e91b93588d7db= 1cef69b6b9813 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5-iwb= .yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5-iwb.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Generic Interrupt Controller, version 5 Interrupt Wire Bridge (= IWB) + +maintainers: + - Lorenzo Pieralisi + - Marc Zyngier + +description: | + The GICv5 architecture defines the guidelines to implement GICv5 + compliant interrupt controllers for AArch64 systems. + + The GICv5 specification can be found at + https://developer.arm.com/documentation/aes0070 + + GICv5 has zero or more Interrupt Wire Bridges (IWB) that are responsible + for translating wire signals into interrupt messages to the GICv5 ITS. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + const: arm,gic-v5-iwb + + interrupt-controller: true + + "#address-cells": + const: 0 + + "#interrupt-cells": + description: | + The 1st cell corresponds to the IWB wire. + + The 2nd cell is the flags, encoded as follows: + bits[3:0] trigger type and level flags. + + 1 =3D low-to-high edge triggered + 2 =3D high-to-low edge triggered + 4 =3D active high level-sensitive + 8 =3D active low level-sensitive + + const: 2 + + reg: + items: + - description: IWB control frame + + msi-parent: + maxItems: 1 + +required: + - compatible + - reg + - msi-parent + +additionalProperties: false + +examples: + - | + interrupt-controller@2f000000 { + compatible =3D "arm,gic-v5-iwb"; + #address-cells =3D <0>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + reg =3D <0x2f000000 0x10000>; + + msi-parent =3D <&its0 64>; + }; +... diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic= -v5.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v= 5.yaml new file mode 100644 index 0000000000000000000000000000000000000000..1ba0a2088e6d15bacae22c9fc9e= ebc4ce5c51b0b --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml @@ -0,0 +1,196 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Generic Interrupt Controller, version 5 + +maintainers: + - Lorenzo Pieralisi + - Marc Zyngier + +description: | + The GICv5 architecture defines the guidelines to implement GICv5 + compliant interrupt controllers for AArch64 systems. + + The GICv5 specification can be found at + https://developer.arm.com/documentation/aes0070 + + The GICv5 architecture is composed of multiple components: + - one or more IRS (Interrupt Routing Service) + - zero or more ITS (Interrupt Translation Service) + + The architecture defines: + - PE-Private Peripheral Interrupts (PPI) + - Shared Peripheral Interrupts (SPI) + - Logical Peripheral Interrupts (LPI) + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + const: arm,gic-v5 + + interrupt-controller: true + + "#address-cells": + enum: [ 1, 2 ] + + "#size-cells": + enum: [ 1, 2 ] + + ranges: true + + "#interrupt-cells": + description: | + The 1st cell corresponds to the INTID.Type field in the INTID; 1 for= PPI, + 3 for SPI. LPI interrupts must not be described in the bindings since + they are allocated dynamically by the software component managing th= em. + + The 2nd cell contains the interrupt INTID.ID field. + + The 3rd cell is the flags, encoded as follows: + bits[3:0] trigger type and level flags. + + 1 =3D low-to-high edge triggered + 2 =3D high-to-low edge triggered + 4 =3D active high level-sensitive + 8 =3D active low level-sensitive + + const: 3 + + interrupts: + description: + The VGIC maintenance interrupt. + maxItems: 1 + +required: + - compatible + +patternProperties: + "^irs@[0-9a-f]+$": + type: object + description: + GICv5 has one or more Interrupt Routing Services (IRS) that are + responsible for handling IRQ state and routing. + + additionalProperties: false + + properties: + compatible: + const: arm,gic-v5-irs + + "#address-cells": + enum: [ 1, 2 ] + + "#size-cells": + enum: [ 1, 2 ] + + ranges: true + + dma-noncoherent: + description: + Present if the GIC IRS permits programming shareability and + cacheability attributes but is connected to a non-coherent + downstream interconnect. + + reg: + minItems: 1 + items: + - description: IRS control frame + - description: IRS setlpi frame + + cpus: + description: + CPUs managed by the IRS. + + arm,iaffids: + $ref: /schemas/types.yaml#/definitions/uint16-array + description: + Interrupt AFFinity ID (IAFFID) associated with the CPU whose + CPU node phandle is at the same index in the cpus array. + + patternProperties: + "^msi-controller@[0-9a-f]+$": + type: object + description: + GICv5 has zero or more Interrupt Translation Services (ITS) that= are + used to route Message Signalled Interrupts (MSI) to the CPUs. Ea= ch + ITS is connected to an IRS. + additionalProperties: false + + properties: + compatible: + const: arm,gic-v5-its + + dma-noncoherent: + description: + Present if the GIC ITS permits programming shareability and + cacheability attributes but is connected to a non-coherent + downstream interconnect. + + msi-controller: true + + "#msi-cells": + description: + The single msi-cell is the DeviceID of the device which will + generate the MSI. + const: 1 + + reg: + items: + - description: ITS control frame + - description: ITS translate frame + + required: + - compatible + - msi-controller + - "#msi-cells" + - reg + + required: + - compatible + - reg + - cpus + - arm,iaffids + +additionalProperties: false + +examples: + - | + interrupt-controller { + compatible =3D "arm,gic-v5"; + #interrupt-cells =3D <3>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + interrupt-controller; + + interrupts =3D <1 25 4>; + + irs@2f1a0000 { + compatible =3D "arm,gic-v5-irs"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + reg =3D <0x2f1a0000 0x10000>; // IRS_CONFIG_FRAME for NS + + arm,iaffids =3D /bits/ 16 <0 1 2 3 4 5 6 7>; + cpus =3D <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>, <&c= pu6>, <&cpu7>; + + msi-controller@2f120000 { + compatible =3D "arm,gic-v5-its"; + + msi-controller; + #msi-cells =3D <1>; + + reg =3D <0x2f120000 0x10000 // ITS_CONFIG_FRAME for NS + 0x2f130000 0x10000>; // ITS_TRANSLATE_FRAME + }; + }; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 96b82704950184bd71623ff41fc4df31e4c7fe87..f3ed84466da19906953b5396a5f= 4b50e878c376e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1901,6 +1901,13 @@ F: drivers/irqchip/irq-gic*.[ch] F: include/linux/irqchip/arm-gic*.h F: include/linux/irqchip/arm-vgic-info.h =20 +ARM GENERIC INTERRUPT CONTROLLER V5 DRIVERS +M: Lorenzo Pieralisi +M: Marc Zyngier +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml + ARM HDLCD DRM DRIVER M: Liviu Dudau S: Supported --=20 2.48.0 From nobody Sun Feb 8 13:09:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB77B221D99; Thu, 24 Apr 2025 10:25:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490355; cv=none; b=T3JkUysXoEZNOybScKIrMiVWAUAx0qGXmbRjHoauRjmiqdE0KlwRz4jXIRBjJcfQtw/9xg6hFL+Q8D7uV5mj+0V1f3xWWPsmO5iUmti1mMQ94MKbd+ixv2xkxz7Cc7RkRPPjqi1qdodlrTzGQ6iNnBX+dlt2S7xTEBkY5BkKJls= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490355; c=relaxed/simple; bh=gXuthZuxBZQLsvBkFkEhlBn3G2hxd3VqLQiwIZeC8vM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Wew9O4awe71akv+7wpeiHeqPy6IfzPCIAo6DQhwRlQwAvW+qpFqltraBYXdGyBG8WJ25JQbxQCL3Cm1XdIYUXwdocrKCi6Sc3hKG+9jrZqnB0KfvnR1729qwNWCEkhlukhKf4H30k+Whgc8kZczZr6Gwd+sV8rrEF4q15LRLDjg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DN/PzKxj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DN/PzKxj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8258BC4CEE4; Thu, 24 Apr 2025 10:25:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745490354; bh=gXuthZuxBZQLsvBkFkEhlBn3G2hxd3VqLQiwIZeC8vM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=DN/PzKxjvI3evpwtZN4r2tZUQEoS/a2Zx/DdzZy7YH0sh0/iWXis7bsoCy09pK4m/ ggaeHfMfW5gljpOg1my/dbM8zKMQLtSyZhAW0YPD+BoRtEmzxoHocArQC7oO1za/BD y883D9Ztguhx7mbShUtMZr0wVP+q9D9nDVs/1yFJ98vGIT3KzZV6PBfQ4TGtbkRm67 OGSr/x8vzXTzEyCUyZ2FY1OcnfbLoLNlLXzGx9Y/xYPutQX1xLZyqQl0OPmMCkkUY/ uvZaYSGZ7XZY0Y8B7vmjsltbyAdOHHjouprr/ZGrdkjxuTU6VD3mdgdBUgr33oGxjb WniyC0bcVCHfg== From: Lorenzo Pieralisi Date: Thu, 24 Apr 2025 12:25:13 +0200 Subject: [PATCH v2 02/22] arm64/sysreg: Add GCIE field to ID_AA64PFR2_EL1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-gicv5-host-v2-2-545edcaf012b@kernel.org> References: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> In-Reply-To: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.14.2 Add field reporting the GCIE feature to ID_AA64PFR2_EL1 sysreg. Signed-off-by: Lorenzo Pieralisi Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier --- arch/arm64/tools/sysreg | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index f9476848a2edfad53bb4af7f68bc05cb2a4af9ce..06e1fb5e126b41b7e41fffa0a00= 553d73197ac3c 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1023,7 +1023,10 @@ UnsignedEnum 19:16 UINJ 0b0000 NI 0b0001 IMP EndEnum -Res0 15:12 +UnsignedEnum 15:12 GCIE + 0b0000 NI + 0b0001 IMP +EndEnum UnsignedEnum 11:8 MTEFAR 0b0000 NI 0b0001 IMP --=20 2.48.0 From nobody Sun Feb 8 13:09:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70E09242D73; Thu, 24 Apr 2025 10:26:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490360; cv=none; b=WVMG9uCh+OsMWSpVVOnKsUUtEwPNs1DeOa4B1MqWiLteDmwp8s0ehbzV+DZVtxxAo9J4COTHNvJD2Jiledxh1ZjVhExi6uaYZhJqRfkBASWzlqObE05CszenXfTe6WyW8BxmaUhI6/B7zXxZ4uHgLIe30IClK4jO6xLHr8AohRI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490360; c=relaxed/simple; bh=TEy69hatB9WvAQZk1Qj5SRXNdR02N3m6osQeJAFrqRk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YqFsrsW/qttHpCdh/vWOcVhlXrMKCk4EMdU8TxkkkgCJ+a4L0z7CEBo5jT55GprAfeS+dSSEwxMku22UOlyJZYQgV/fiPaWMvuAnswCH2KtJ+ifUw5r1fZwAUwTROSFJ7OBHgMFBjHG4dPnzK5Ez/bDCJGpUgekQemXjPU7gpSE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KA15Nqno; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KA15Nqno" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0B441C4CEE3; Thu, 24 Apr 2025 10:25:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745490359; bh=TEy69hatB9WvAQZk1Qj5SRXNdR02N3m6osQeJAFrqRk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=KA15NqnoNNLGZtHty+zT0MAYmtgI5unjRVmOAGYqnksi1yMeeNx9GSiTjCtMn5G+I IRzm7DNRDbqV/Tz6J9SGnym0Sq/979QXWvLieyvMJ51i00iWlo8ngTNg11sLq6SEyO mUhk12TWZPlbTetukKFeD+Rx71DQWTUXqN+VxVqFTV13JJoowCvjjZSBEY8o7j8MmE gVXEkXXKqN8TN8JkNX0+hWfXHSc4TpsmnnfkiszxWTeCx138BdET27Cm6ADlStS9rZ 2GffQxptAbfH2il6DAiH9dxjUEe/tYNB7VXxlGBnAslLhxDyEaOqxFuzE6r+EoWFKW NFbKm3dAcdFrw== From: Lorenzo Pieralisi Date: Thu, 24 Apr 2025 12:25:14 +0200 Subject: [PATCH v2 03/22] arm64/sysreg: Add ICC_PPI_PRIORITY_EL1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-gicv5-host-v2-3-545edcaf012b@kernel.org> References: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> In-Reply-To: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.14.2 Add ICC_PPI_PRIORITY_EL1 sysreg description. Signed-off-by: Lorenzo Pieralisi Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier --- arch/arm64/tools/sysreg | 83 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 83 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 06e1fb5e126b41b7e41fffa0a00553d73197ac3c..0cc1268c0bfad8266da47b441e8= 0c603e46c00ae 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2310,6 +2310,89 @@ Field 31 C Field 30:0 P EndSysreg =20 +SysregFields ICC_PPI_PRIORITYRx_EL1 +Res0 63:61 +Field 60:56 Priority7 +Res0 55:53 +Field 52:48 Priority6 +Res0 47:45 +Field 44:40 Priority5 +Res0 39:37 +Field 36:32 Priority4 +Res0 31:29 +Field 28:24 Priority3 +Res0 23:21 +Field 20:16 Priority2 +Res0 15:13 +Field 12:8 Priority1 +Res0 7:5 +Field 4:0 Priority0 +EndSysregFields + +Sysreg ICC_PPI_PRIORITYR0_EL1 3 0 12 14 0 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR1_EL1 3 0 12 14 1 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR2_EL1 3 0 12 14 2 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR3_EL1 3 0 12 14 3 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR4_EL1 3 0 12 14 4 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR5_EL1 3 0 12 14 5 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR6_EL1 3 0 12 14 6 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR7_EL1 3 0 12 14 7 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR8_EL1 3 0 12 15 0 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR9_EL1 3 0 12 15 1 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR10_EL1 3 0 12 15 2 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR11_EL1 3 0 12 15 3 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR12_EL1 3 0 12 15 4 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR13_EL1 3 0 12 15 5 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR14_EL1 3 0 12 15 6 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR15_EL1 3 0 12 15 7 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + Sysreg PMSELR_EL0 3 3 9 12 5 Res0 63:5 Field 4:0 SEL --=20 2.48.0 From nobody Sun Feb 8 13:09:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B96B1244682; Thu, 24 Apr 2025 10:26:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490365; cv=none; b=u1tZ8DQsvV4+gewypwJHKdv5hNQI2J2Lw1mJLKw2qwXfIHv/VqIQI65Tv9whv8yJzl3rP7V1NM3+HcK58l2/MTcaFR/dIslrQrmI0jwwmI5fCxe8EgXCHD5UIUSWcq/qHQ610eenA/i3Rm0LcOlyDafxBSFMtOGC+OnDfDhE5h8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490365; c=relaxed/simple; bh=Tv02OqEETUJL5RhGfHRLiUOkxm6hkdgtGZBz124yXQU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CeAfTkoiK1vFYn/zsmyEmXUDgvOVLao+6gLoQuJMqy57M7KOx4oImpI3Wj3aq9/5KEr1u7FgP5QJbwf0R/zYjuQ44lI4XA0vZ26+V8NdylTOBs81Vzs1ONrP1VkhL/M7XngdDT3fjvAPMk899LZOYY6JIGAhAa6dW6BAJctuTGM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tCOQHF59; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tCOQHF59" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8C2C4C4CEE4; Thu, 24 Apr 2025 10:26:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745490365; bh=Tv02OqEETUJL5RhGfHRLiUOkxm6hkdgtGZBz124yXQU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=tCOQHF59GpB2B1LJWI0AyNHF1OYdRKMq0qYGT6YcOqJM0NPVvrOGTepWXKnzIz5xg wyYdhY0i7kB9Dbuv7h5my+LJVK5Q38P8neCv3KBEJO2VADJ+4BBL1fuVbL/Mfx9IpD 3e52tQLysUfUIFBWna0G9DGDeKdwsdmyE3Y7l+hkr4KrRdIdXKpbH+FedgHYsN1aHV xAUyZ2d/rwBDtpBJj+834kOWMuB1zORrQlsdgJt6QddCXg4CU3dr829jLsNwyJklcP kSt9vxusDd3FaV1feRWnX1yCSWbXUEZxiHwh9nu9SrXGdcofcqir7zfFyMRYCOzP7O FafIMG/HoUhoA== From: Lorenzo Pieralisi Date: Thu, 24 Apr 2025 12:25:15 +0200 Subject: [PATCH v2 04/22] arm64/sysreg: Add ICC_ICSR_EL1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-gicv5-host-v2-4-545edcaf012b@kernel.org> References: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> In-Reply-To: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.14.2 Add ICC_ICSR_EL1 register sysreg description. Signed-off-by: Lorenzo Pieralisi Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier --- arch/arm64/tools/sysreg | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 0cc1268c0bfad8266da47b441e80c603e46c00ae..985f2cdb67cfec6df335a3951ec= b63f128f6da55 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2310,6 +2310,20 @@ Field 31 C Field 30:0 P EndSysreg =20 +Sysreg ICC_ICSR_EL1 3 0 12 10 4 +Res0 63:48 +Field 47:32 IAFFID +Res0 31:16 +Field 15:11 Priority +Res0 10:6 +Field 5 HM +Field 4 Active +Field 3 IRM +Field 2 Pending +Field 1 Enabled +Field 0 F +EndSysreg + SysregFields ICC_PPI_PRIORITYRx_EL1 Res0 63:61 Field 60:56 Priority7 --=20 2.48.0 From nobody Sun Feb 8 13:09:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 469AE22170B; Thu, 24 Apr 2025 10:26:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490371; cv=none; b=tWVw1zx/q3ZsaYXKAdTYyJPa5x+d0s0rgUy3wAE87EAYZlJ9G+txh8yel1F/wVI7IG0OpcDBC8ARs7aR6K2xeUxdY//V0ix88lR3hbWQJZQWC9JkzLWZaV/J4RtiLlh8m0WNzmFLCshBcV/xN7zhg7N5J43+z94/ElNRfktzcRo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490371; c=relaxed/simple; bh=OznnXe4nZQZT5vM8HP2AP0cBLVxiMADjBCE9cYkRzRc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hxNH2fio6ZengnrwqJ7LU7iUWA8v42H/4AQ3YehW324ow2Zt6Yhbq6QR5kaj6aV2juEg4sfuGKhaayDCozboGhFvqH0SZ92q8unlQ9rxe+pIKv+2oirdznStERwCiGxUBiJvHbfQDdz2y+RVZbcgElg/sHIi63mv0KIm/P0FDVA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GxQLDVSH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GxQLDVSH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D6D14C4CEEE; Thu, 24 Apr 2025 10:26:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745490370; bh=OznnXe4nZQZT5vM8HP2AP0cBLVxiMADjBCE9cYkRzRc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=GxQLDVSHU+hhNkPEXwBopGzxIQSpDaseVr3VyiUsCENfZAr3MJMr4IFBZwSTWfg+3 IX0QSgb35PlnU1zKNLYIAhqshCcAYOD5Q3wVGTwRiimTo23zDdxpwuOkf0x5urJZAM HCQpj/D3J4j2CQuSxrSarhQShBHWGeKSaEGHALce+/ThEl1ysNvWxOoB+sIZ5SuXgR JpZDaAR0wjAZJOOQUrjDtdlfdSt1znnnoLZ1YLLnEPRQqT0epIXtzu1LPCOluKwmON Zr/4Id3qXJVrE7pWHOVE9Gtpd4isDBeJK4MKIkeDtIhhbW8TIXMqRaDdW9MIQG9r24 JCP6MeA5j/hBg== From: Lorenzo Pieralisi Date: Thu, 24 Apr 2025 12:25:16 +0200 Subject: [PATCH v2 05/22] arm64/sysreg: Add ICC_PPI_HMR_EL1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-gicv5-host-v2-5-545edcaf012b@kernel.org> References: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> In-Reply-To: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.14.2 Add ICC_PPI_HMR_EL1 registers sysreg description. Signed-off-by: Lorenzo Pieralisi Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier --- arch/arm64/tools/sysreg | 75 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 985f2cdb67cfec6df335a3951ecb63f128f6da55..d046d719d4f69801aeef51b5b94= 37a0eaa04134e 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2324,6 +2324,81 @@ Field 1 Enabled Field 0 F EndSysreg =20 +SysregFields ICC_PPI_HMRx_EL1 +Field 63 HM63 +Field 62 HM62 +Field 61 HM61 +Field 60 HM60 +Field 59 HM59 +Field 58 HM58 +Field 57 HM57 +Field 56 HM56 +Field 55 HM55 +Field 54 HM54 +Field 53 HM53 +Field 52 HM52 +Field 51 HM51 +Field 50 HM50 +Field 49 HM49 +Field 48 HM48 +Field 47 HM47 +Field 46 HM46 +Field 45 HM45 +Field 44 HM44 +Field 43 HM43 +Field 42 HM42 +Field 41 HM41 +Field 40 HM40 +Field 39 HM39 +Field 38 HM38 +Field 37 HM37 +Field 36 HM36 +Field 35 HM35 +Field 34 HM34 +Field 33 HM33 +Field 32 HM32 +Field 31 HM31 +Field 30 HM30 +Field 29 HM29 +Field 28 HM28 +Field 27 HM27 +Field 26 HM26 +Field 25 HM25 +Field 24 HM24 +Field 23 HM23 +Field 22 HM22 +Field 21 HM21 +Field 20 HM20 +Field 19 HM19 +Field 18 HM18 +Field 17 HM17 +Field 16 HM16 +Field 15 HM15 +Field 14 HM14 +Field 13 HM13 +Field 12 HM12 +Field 11 HM11 +Field 10 HM10 +Field 9 HM9 +Field 8 HM8 +Field 7 HM7 +Field 6 HM6 +Field 5 HM5 +Field 4 HM4 +Field 3 HM3 +Field 2 HM2 +Field 1 HM1 +Field 0 HM0 +EndSysregFields + +Sysreg ICC_PPI_HMR0_EL1 3 0 12 10 0 +Fields ICC_PPI_HMRx_EL1 +EndSysreg + +Sysreg ICC_PPI_HMR1_EL1 3 0 12 10 1 +Fields ICC_PPI_HMRx_EL1 +EndSysreg + SysregFields ICC_PPI_PRIORITYRx_EL1 Res0 63:61 Field 60:56 Priority7 --=20 2.48.0 From nobody Sun Feb 8 13:09:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4586223DCC; Thu, 24 Apr 2025 10:26:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490378; cv=none; b=Ah1+pzwn3222Qeu3O8Q8XyUTnqFxE9gRU7cYIXODvLnLKQEyvIek/cqTFAwRo2sKmYX1xWcQp6rLJ662Q9RI38bopW5Qzpa1wOzDLe935SRf/dH4MduVNyY7jIHgfR0Y/4aLJeHPvEgkaan+A0RDSfhVgD0hj8c+IKzHyIKCwBU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490378; c=relaxed/simple; bh=eUBcCIH4szhTdWT4b2dVdh8O8kcTuP+XkEb7/cO8FcI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bvOq6NusyR9suWmO1rxRuieKfjnhim8xodD4BUItUjARr6jAy3PJjz1uukqVG5lzrZMUP05GHihG80a8opUj8JNToNkiPNO2KxVWXwvCF0bh6GtSeXsfIxOR9xrKJQD2xqZtISMlcKD0oz/T/ALuD6sgMM+tXA2lcdDEC4k6Ht0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=d4pjQcpN; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="d4pjQcpN" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 62609C4CEE3; Thu, 24 Apr 2025 10:26:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745490376; bh=eUBcCIH4szhTdWT4b2dVdh8O8kcTuP+XkEb7/cO8FcI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=d4pjQcpNRKd4CxS/9SC6WbdkMqN+6q0sfs9fWJroK6jX6S7xeHlG/ufkvOEnJprlb fQZKCdGYWdxTL19dxzrGosCYPh3ZIsTuJxYhrPS3lnAQXbsOU0eBUId9qWY7Hkp+PV tj5wLRnDx0I2xQPEOlAYZ2i5E06W1fLsyRArulFFQUyhTB/nipE5YpGDQHb6hrOdJz R27i1l29S0G2FUJMq8o/UoZPQAUvqpJC+vPgq3kczNxNqDAUxp4kw+ER3PPTE5RMjA aha/lVd2ZGc4GwbSRTBQ8N0Th8/QF3NjPFGrUxpEIbT+hiZIW1S/wzc1D0mwiNwV72 /tfAkriS9cr/Q== From: Lorenzo Pieralisi Date: Thu, 24 Apr 2025 12:25:17 +0200 Subject: [PATCH v2 06/22] arm64/sysreg: Add ICC_PPI_ENABLER_EL1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-gicv5-host-v2-6-545edcaf012b@kernel.org> References: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> In-Reply-To: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.14.2 Add ICC_PPI_ENABLER_EL1 registers sysreg description. Signed-off-by: Lorenzo Pieralisi Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier --- arch/arm64/tools/sysreg | 75 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index d046d719d4f69801aeef51b5b9437a0eaa04134e..6c5552707ad88c145adc8b7ceb3= f63da401191ea 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2399,6 +2399,81 @@ Sysreg ICC_PPI_HMR1_EL1 3 0 12 10 1 Fields ICC_PPI_HMRx_EL1 EndSysreg =20 +SysregFields ICC_PPI_ENABLERx_EL1 +Field 63 EN63 +Field 62 EN62 +Field 61 EN61 +Field 60 EN60 +Field 59 EN59 +Field 58 EN58 +Field 57 EN57 +Field 56 EN56 +Field 55 EN55 +Field 54 EN54 +Field 53 EN53 +Field 52 EN52 +Field 51 EN51 +Field 50 EN50 +Field 49 EN49 +Field 48 EN48 +Field 47 EN47 +Field 46 EN46 +Field 45 EN45 +Field 44 EN44 +Field 43 EN43 +Field 42 EN42 +Field 41 EN41 +Field 40 EN40 +Field 39 EN39 +Field 38 EN38 +Field 37 EN37 +Field 36 EN36 +Field 35 EN35 +Field 34 EN34 +Field 33 EN33 +Field 32 EN32 +Field 31 EN31 +Field 30 EN30 +Field 29 EN29 +Field 28 EN28 +Field 27 EN27 +Field 26 EN26 +Field 25 EN25 +Field 24 EN24 +Field 23 EN23 +Field 22 EN22 +Field 21 EN21 +Field 20 EN20 +Field 19 EN19 +Field 18 EN18 +Field 17 EN17 +Field 16 EN16 +Field 15 EN15 +Field 14 EN14 +Field 13 EN13 +Field 12 EN12 +Field 11 EN11 +Field 10 EN10 +Field 9 EN9 +Field 8 EN8 +Field 7 EN7 +Field 6 EN6 +Field 5 EN5 +Field 4 EN4 +Field 3 EN3 +Field 2 EN2 +Field 1 EN1 +Field 0 EN0 +EndSysregFields + +Sysreg ICC_PPI_ENABLER0_EL1 3 0 12 10 6 +Fields ICC_PPI_ENABLERx_EL1 +EndSysreg + +Sysreg ICC_PPI_ENABLER1_EL1 3 0 12 10 7 +Fields ICC_PPI_ENABLERx_EL1 +EndSysreg + SysregFields ICC_PPI_PRIORITYRx_EL1 Res0 63:61 Field 60:56 Priority7 --=20 2.48.0 From nobody Sun Feb 8 13:09:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1755F227EAF; Thu, 24 Apr 2025 10:26:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490383; cv=none; b=H5l7YVsDA0DIyulufx5C8VXjjGwkSTa99Os2xgo5f0u52KNQC2oaWelNnFVTeqYFkCRGVqExQs9F8vbn7JXmv02ktWaYYl0JRawWlwMSoYtgnslCxGUpcDKtWdjrs9ECbtC37sn2IgP7FyM5LsaKS51pVLTbt10XOLkmlCJDmKc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490383; c=relaxed/simple; bh=kr4FIsYzSG8vhPEwCV+efvFDb0h/Nmo/+nvgPyW4hHA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IhIGOO4xcHcvC8IX4cL9kDxmOd6lEp9fmmAQ8c18JaV1Ohb6DURCUIZbz/oBJbkKdwN/QoxpAONdVxnAXaR58Sp0uBQinjS35OYPLYHeOhzopfS9RZZpw+sEfQpLXtbWwYN+TNe+Wuqb2fTGZOASXEUqMMeemGG+R/XyO2Zpd8k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ILKyBt1I; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ILKyBt1I" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CE89EC4CEE4; Thu, 24 Apr 2025 10:26:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745490381; bh=kr4FIsYzSG8vhPEwCV+efvFDb0h/Nmo/+nvgPyW4hHA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ILKyBt1IczSJiTJPvZMBBVo8QwbcOmuh8v5F9KPko4PDKCnBGqFWWEk1Ddo2ZeoSQ FqyVtfMbxxlfMjkEhpnfwtwnPV1Es4iBa9nouBPw/L5881GL5ShkIC3RqCowyIwY30 tfaXfhAqmULzHGW58B7ZHWExlQ5YWq0K/DumgvQJSVaceVzcBpcscPWVbikUAAdMfI 8ecczXF9vlIjnfD91cGAHWIF0q+rGxH8zW2lEvLfWzgWOrfnH3OKWP3S0kfTshUw+6 m2rj+gD+HA54nKPjR067r5S8dJfQa8TUmGdaoNEN9q+tsPS8aXVH1aa6JfpeJgMmCO MjaCdA4Dzn7fg== From: Lorenzo Pieralisi Date: Thu, 24 Apr 2025 12:25:18 +0200 Subject: [PATCH v2 07/22] arm64/sysreg: Add ICC_PPI_{C/S}ACTIVER_EL1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-gicv5-host-v2-7-545edcaf012b@kernel.org> References: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> In-Reply-To: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.14.2 Add ICC_PPI_{C/S}ACTIVER_EL1 registers description. Signed-off-by: Lorenzo Pieralisi Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier --- arch/arm64/tools/sysreg | 83 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 83 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 6c5552707ad88c145adc8b7ceb3f63da401191ea..0485721e1575c9ed158210c6f02= fb9af2828f2d5 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2474,6 +2474,89 @@ Sysreg ICC_PPI_ENABLER1_EL1 3 0 12 10 7 Fields ICC_PPI_ENABLERx_EL1 EndSysreg =20 +SysregFields ICC_PPI_ACTIVERx_EL1 +Field 63 Active63 +Field 62 Active62 +Field 61 Active61 +Field 60 Active60 +Field 59 Active59 +Field 58 Active58 +Field 57 Active57 +Field 56 Active56 +Field 55 Active55 +Field 54 Active54 +Field 53 Active53 +Field 52 Active52 +Field 51 Active51 +Field 50 Active50 +Field 49 Active49 +Field 48 Active48 +Field 47 Active47 +Field 46 Active46 +Field 45 Active45 +Field 44 Active44 +Field 43 Active43 +Field 42 Active42 +Field 41 Active41 +Field 40 Active40 +Field 39 Active39 +Field 38 Active38 +Field 37 Active37 +Field 36 Active36 +Field 35 Active35 +Field 34 Active34 +Field 33 Active33 +Field 32 Active32 +Field 31 Active31 +Field 30 Active30 +Field 29 Active29 +Field 28 Active28 +Field 27 Active27 +Field 26 Active26 +Field 25 Active25 +Field 24 Active24 +Field 23 Active23 +Field 22 Active22 +Field 21 Active21 +Field 20 Active20 +Field 19 Active19 +Field 18 Active18 +Field 17 Active17 +Field 16 Active16 +Field 15 Active15 +Field 14 Active14 +Field 13 Active13 +Field 12 Active12 +Field 11 Active11 +Field 10 Active10 +Field 9 Active9 +Field 8 Active8 +Field 7 Active7 +Field 6 Active6 +Field 5 Active5 +Field 4 Active4 +Field 3 Active3 +Field 2 Active2 +Field 1 Active1 +Field 0 Active0 +EndSysregFields + +Sysreg ICC_PPI_CACTIVER0_EL1 3 0 12 13 0 +Fields ICC_PPI_ACTIVERx_EL1 +EndSysreg + +Sysreg ICC_PPI_CACTIVER1_EL1 3 0 12 13 1 +Fields ICC_PPI_ACTIVERx_EL1 +EndSysreg + +Sysreg ICC_PPI_SACTIVER0_EL1 3 0 12 13 2 +Fields ICC_PPI_ACTIVERx_EL1 +EndSysreg + +Sysreg ICC_PPI_SACTIVER1_EL1 3 0 12 13 3 +Fields ICC_PPI_ACTIVERx_EL1 +EndSysreg + SysregFields ICC_PPI_PRIORITYRx_EL1 Res0 63:61 Field 60:56 Priority7 --=20 2.48.0 From nobody Sun Feb 8 13:09:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58CBD228CB5; Thu, 24 Apr 2025 10:26:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490387; cv=none; b=j3ql0R5imjXFOuifE4oCfy06l1QSo2p1+XAq5kI1zLJijCpHEyNN71dMmRqueu4Yu9PQDwRJn26kQ4WMoAVN7uWg5WKeM9h20xEVFw3bu+PmsYYGR5WJ8f++V8JTSlWzv0v/NCiYJICq1uVtCqSAxsbqvS6AcF6HERUp1CgMwuY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490387; c=relaxed/simple; bh=sQqjxedBfR/x/zpD52PYNFW1off5a3wsTQ0MTvz8038=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CZd6FGXHY2xtcMkHEOXfR0ycxA5atdAQ7mv/DeRh516QH9lS9m1sPC2WRUljpoaAQ/llfyuYxekG7hwDYu15o8uNVy485h6fELp7N3zoc17r/MdwUM/sn5bq9RGxgrIjDvGk1c3fMpOzhR8bllZAbDB/QXf+xtLW8oe2yLJYZu8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TPwwBpri; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TPwwBpri" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2532AC4CEE3; Thu, 24 Apr 2025 10:26:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745490387; bh=sQqjxedBfR/x/zpD52PYNFW1off5a3wsTQ0MTvz8038=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=TPwwBpriNc0+fM5u275PADg2/Z0gkUhlIIelYTmfNYNiby3bhXCPkyPbAkiPxkY4G mh8zqfyF3dj9p7ndfKWQqDJeE6IvWWN5f3BDpp+UiqH+Fy8t42Ao7rQnVWQYbOLnaU jeYphKiDIOZFW/Oy+fubmAPlpqpb4PDt7wWG0k77qySyJoHaHFtqZClW76Abcj4ozl 966A5wnXhD+JMkAOxQE3SQNibeM407N1HiB0hOn1MVIYpes8rlI8SMOAS2I48E7RQ/ mJMdtD0z7206s1TK9kDFr8KTJAlNCgDBOvmiXnSVmSX8nG08Q8bShIkI4UdidL0SEZ dNXTeXz73cVKQ== From: Lorenzo Pieralisi Date: Thu, 24 Apr 2025 12:25:19 +0200 Subject: [PATCH v2 08/22] arm64/sysreg: Add ICC_PPI_{C/S}PENDR_EL1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-gicv5-host-v2-8-545edcaf012b@kernel.org> References: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> In-Reply-To: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.14.2 Add ICC_PPI_{C/S}PENDR_EL1 registers description. Signed-off-by: Lorenzo Pieralisi Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier --- arch/arm64/tools/sysreg | 83 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 83 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 0485721e1575c9ed158210c6f02fb9af2828f2d5..7acad93718c56729ce2a333ed00= 7243ec554dbc9 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2557,6 +2557,89 @@ Sysreg ICC_PPI_SACTIVER1_EL1 3 0 12 13 3 Fields ICC_PPI_ACTIVERx_EL1 EndSysreg =20 +SysregFields ICC_PPI_PENDRx_EL1 +Field 63 Pend63 +Field 62 Pend62 +Field 61 Pend61 +Field 60 Pend60 +Field 59 Pend59 +Field 58 Pend58 +Field 57 Pend57 +Field 56 Pend56 +Field 55 Pend55 +Field 54 Pend54 +Field 53 Pend53 +Field 52 Pend52 +Field 51 Pend51 +Field 50 Pend50 +Field 49 Pend49 +Field 48 Pend48 +Field 47 Pend47 +Field 46 Pend46 +Field 45 Pend45 +Field 44 Pend44 +Field 43 Pend43 +Field 42 Pend42 +Field 41 Pend41 +Field 40 Pend40 +Field 39 Pend39 +Field 38 Pend38 +Field 37 Pend37 +Field 36 Pend36 +Field 35 Pend35 +Field 34 Pend34 +Field 33 Pend33 +Field 32 Pend32 +Field 31 Pend31 +Field 30 Pend30 +Field 29 Pend29 +Field 28 Pend28 +Field 27 Pend27 +Field 26 Pend26 +Field 25 Pend25 +Field 24 Pend24 +Field 23 Pend23 +Field 22 Pend22 +Field 21 Pend21 +Field 20 Pend20 +Field 19 Pend19 +Field 18 Pend18 +Field 17 Pend17 +Field 16 Pend16 +Field 15 Pend15 +Field 14 Pend14 +Field 13 Pend13 +Field 12 Pend12 +Field 11 Pend11 +Field 10 Pend10 +Field 9 Pend9 +Field 8 Pend8 +Field 7 Pend7 +Field 6 Pend6 +Field 5 Pend5 +Field 4 Pend4 +Field 3 Pend3 +Field 2 Pend2 +Field 1 Pend1 +Field 0 Pend0 +EndSysregFields + +Sysreg ICC_PPI_CPENDR0_EL1 3 0 12 13 4 +Fields ICC_PPI_PENDRx_EL1 +EndSysreg + +Sysreg ICC_PPI_CPENDR1_EL1 3 0 12 13 5 +Fields ICC_PPI_PENDRx_EL1 +EndSysreg + +Sysreg ICC_PPI_SPENDR0_EL1 3 0 12 13 6 +Fields ICC_PPI_PENDRx_EL1 +EndSysreg + +Sysreg ICC_PPI_SPENDR1_EL1 3 0 12 13 7 +Fields ICC_PPI_PENDRx_EL1 +EndSysreg + SysregFields ICC_PPI_PRIORITYRx_EL1 Res0 63:61 Field 60:56 Priority7 --=20 2.48.0 From nobody Sun Feb 8 13:09:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33958221F0F; Thu, 24 Apr 2025 10:26:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490393; cv=none; b=tL/5ee5sOLz83n6HBvxEAd6Nx2SwPfF7O9JwoKSGG0uyJEZonkHZaKSWNb76mihnTgLsKP2SbpMNfIyPLXQk8VQTM0+2JwvR+rtyyXHcSoRCgHTsHCkOZwz7khiwiV+E0r0ofKYIdoPfdwHhD7sAZ4kcnX8saj42URMS0C2I2wc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490393; c=relaxed/simple; bh=aABGEIrWEsGcFFHRxubhJftIId76X0k2qcZSdwnplek=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IY2P9f8ejcmltRYLfLUyVo/Ak6QWro6YdEfgvGzbXSvVlLeBK34HyGCxVQg4R4bDtn8XXEXDLcD/h/EzJFhigQQ0LUCTc+x8jLtjLynxJTZD9Ac8BsSItM52mlIWDopUWqrsW57YvP7qV3BmHRCWkbCvNDYsJ3EStLnAGNWyfBo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HBybB16+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HBybB16+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C8ACFC4CEE3; Thu, 24 Apr 2025 10:26:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745490392; bh=aABGEIrWEsGcFFHRxubhJftIId76X0k2qcZSdwnplek=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=HBybB16+fsCutQzZUOtglVtIX3DMjYHUdACgl8SYiD1QHUtJ0GTMgfNb7I0dzQFxZ bPKQxbwQZRHUlf3FzzE/UvhOztI5wfpHNZDtiF85DCpD9iSNVOQTGJFHLmgInFVyj+ cEvSewxpwNtI/1uDJCIm+RGGY0lRjmefMgxBQeaVl8+XWaYZUvLJgTeJqPIQfQ33UZ 8tSKTg5tpnJ0H5PE0+ey+Y4u+uNnmbsFqjSDWEUFaqXnSg//FC6xVUgXvI4ANov0Ac fTpzJT3UXuODx5YDMmbnSuHW4ijpk/62PBLfKcl9qo/8lyQE+cMSelTzMejy3wuiSn ri4E5SO2lHENQ== From: Lorenzo Pieralisi Date: Thu, 24 Apr 2025 12:25:20 +0200 Subject: [PATCH v2 09/22] arm64/sysreg: Add ICC_CR0_EL1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-gicv5-host-v2-9-545edcaf012b@kernel.org> References: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> In-Reply-To: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.14.2 Add ICC_CR0_EL1 register description. Signed-off-by: Lorenzo Pieralisi Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier --- arch/arm64/tools/sysreg | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 7acad93718c56729ce2a333ed007243ec554dbc9..c96243505031ea680c04a693fee= 2c96ad19e30ea 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2798,6 +2798,14 @@ Res0 14:12 Field 11:0 AFFINITY EndSysreg =20 +Sysreg ICC_CR0_EL1 3 1 12 0 1 +Res0 63:39 +Field 38 PID +Field 37:32 IPPT +Res0 31:1 +Field 0 EN +EndSysreg + Sysreg CSSELR_EL1 3 2 0 0 0 Res0 63:5 Field 4 TnD --=20 2.48.0 From nobody Sun Feb 8 13:09:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51282224B10; Thu, 24 Apr 2025 10:26:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490398; cv=none; b=bq7X9R4PxkYfziKGZjVw5GRjiF4MC09ZnJGq7xKarvr87lfp/hga2J89OfIuX8bhm8+RHWFn8ZtH3Taybi7K8zbwW8U0yn1Oti8awf6JeDgUCMM0DLFVPVqquNyR7WtIlWwenRGMQuG7+DNiB8NGSn06+xcAa16Gb1CoUq3rF74= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490398; c=relaxed/simple; bh=IR60XZsATfdTuIxQzwSdrYf53KWRtcmnuEgRG5+wtmQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Ra7mzGK1lGNXIV3OLxFmTZt5l/PzL18XgTmCl/SJ8/ptvT25SyHh8unVZak4LNIa5DUezCJJ25ZVMd/YZg5cQef5IH/xYYbCZYYnQXPNodBneWvGivYoA4/GjSyWuq0VxUUcaxEeu6HkbMhh5ajeJTMuCHEUKJ24g2tbiZD2f18= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CKdSUuDu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CKdSUuDu" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6CD58C4CEE3; Thu, 24 Apr 2025 10:26:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745490398; bh=IR60XZsATfdTuIxQzwSdrYf53KWRtcmnuEgRG5+wtmQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=CKdSUuDu0deDC5a3Tw/7ckqarMXiN7nyUVjfKIUy/0S90tPll39k9AScbNKaoUzSr MwQowBh+FN55aSoCHWF+ZB1MRW6PBjWEkivaX+vg2qkx3XnzAvNeC+/Dq8hKcONo5x a2XyO0WpAIFSxpn7hqPRshTWT2tF14ibjJi+LoSYHyXt0/SJLSf6+8qYdBh37uTRsO /+Xfid4X36zuTZXw3L8K02ZqTRmOunYbytpYfYvR//OwoX3+/eOVQza6I80uI5N628 /Zin9cfTC9JhNJzqctgCD11eI01qsWjreYa23bY3Hd5y9zVTFNMUYaaJyTDk46OkxY OM5Iy+gPz1/kQ== From: Lorenzo Pieralisi Date: Thu, 24 Apr 2025 12:25:21 +0200 Subject: [PATCH v2 10/22] arm64/sysreg: Add ICC_PCR_EL1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-gicv5-host-v2-10-545edcaf012b@kernel.org> References: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> In-Reply-To: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.14.2 Add ICC_PCR_EL1 register description. Signed-off-by: Lorenzo Pieralisi Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier --- arch/arm64/tools/sysreg | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index c96243505031ea680c04a693fee2c96ad19e30ea..9a2ddab8661c85586b0e91f7eaa= bd5a6b3409c67 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2806,6 +2806,11 @@ Res0 31:1 Field 0 EN EndSysreg =20 +Sysreg ICC_PCR_EL1 3 1 12 0 2 +Res0 63:5 +Field 4:0 PRIORITY +EndSysreg + Sysreg CSSELR_EL1 3 2 0 0 0 Res0 63:5 Field 4 TnD --=20 2.48.0 From nobody Sun Feb 8 13:09:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10A9B224B10; Thu, 24 Apr 2025 10:26:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490404; cv=none; b=OqXQxHD40pzY1Wq4Jmgi+V3hkGaeuJOsRS/2gmjxqGG0NlD86M5Mj3QcOyeLs22+Ilu3vaIO6SWxKizV4o2Qgxh9D7RoFkWTBfAe6jqWHls5YsJrSsN0Tj7c3U9DL6f6yqlt2kzA2PPOKnA366OeiD6AjKvhwmES+eaKaV0hVoI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490404; c=relaxed/simple; bh=Dk78WkgkowYSPPndroB+3TTj6jQAcxwQp1XS8EQ5gtg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hlYts+G3u+jlMacFy7gKlKFe/Ps0n6l4AZGTd7Yfel2Lbyk07j2pfCEb+efZAU9YpjNFmesKWIuSnslmaSWEl65uIDRi9H+tlP+r04LRRW2RWq8MwYLLU/7gro0WSkGaKWTCxt0xPAJs9gUVSpvb4I6xSkaCQoueAtCi59iB8NI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PZrHJuOy; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PZrHJuOy" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CE98EC4CEE3; Thu, 24 Apr 2025 10:26:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745490403; bh=Dk78WkgkowYSPPndroB+3TTj6jQAcxwQp1XS8EQ5gtg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=PZrHJuOyOr+DjlEgWYw8lklQLm4mI8ftUNQPhpx6Y4rdrvD0oftIfPXYf48Hbd1hO QMP7tzqYuFKcpKmpkYezNFR1C4l6jryEgzXCWrWAoh1QDCmh1CiuS4B0U2nEQOLEiS HmaTbaCxh8HPByAvi13Pptu+caSAYGBCm69iUBXDAWzhMSaagjRwE4zn/cGg/uiUos nxbhajYZKhBaUpFEK8JJYgSVC3VEJui9KQqmbdfF0WC2Pcn0G8K6T0d1Lz70+qDmGy 9bi/PUoGKLM/SFcgqMxuunSZiOG2H2IbS/Fhu413+NlJsGeByNrgUuzk8e2RfvjF4B 7uUm412twV8gA== From: Lorenzo Pieralisi Date: Thu, 24 Apr 2025 12:25:22 +0200 Subject: [PATCH v2 11/22] arm64/sysreg: Add ICC_IDR0_EL1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-gicv5-host-v2-11-545edcaf012b@kernel.org> References: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> In-Reply-To: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.14.2 Add ICC_IDR0_EL1 register description. Signed-off-by: Lorenzo Pieralisi Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier --- arch/arm64/tools/sysreg | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 9a2ddab8661c85586b0e91f7eaabd5a6b3409c67..1ec8113df713dfea6d38e39c42e= ba1e3dca5eea5 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2399,6 +2399,22 @@ Sysreg ICC_PPI_HMR1_EL1 3 0 12 10 1 Fields ICC_PPI_HMRx_EL1 EndSysreg =20 +Sysreg ICC_IDR0_EL1 3 0 12 10 2 +Res0 63:12 +UnsignedEnum 11:8 GCIE_LEGACY + 0b0000 NI + 0b0001 IMP +EndEnum +UnsignedEnum 7:4 PRI_BITS + 0b0011 4BITS + 0b0100 5BITS +EndEnum +UnsignedEnum 3:0 ID_BITS + 0b0000 16BITS + 0b0001 24BITS +EndEnum +EndSysreg + SysregFields ICC_PPI_ENABLERx_EL1 Field 63 EN63 Field 62 EN62 --=20 2.48.0 From nobody Sun Feb 8 13:09:09 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37C6B22C321; Thu, 24 Apr 2025 10:26:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490410; cv=none; b=JMuYjcY5+x52sOw0LJ/lpeJm983k6URgb+x9V4wLncwwx1IY5DLeIqtYoYV1UoNVJI7Zm1vIjLSzNtKBdvz3yRl13EI7QtBXphqvnIGBGXb95yIT+7cgBB7Yj9lE/Jfubq1m0dFWH5+X1s5JVKV+OCQeK6lPlseMCj2tqUotyts= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490410; c=relaxed/simple; bh=jtBNyXLItJhfIxTK4Pp6vzdTvnQztzIAhQqNSaBxo3Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=A7DVqKeIsRdbzY6emvk1aOoqVxyJ1H5UonvteW/S+JLWITxd8hSY2Nrb+hQNEUBtn5+PQxNzLWoQZGSzvrF3sybNeFXKBQBnAb/P6lFIDFqESGd71xEqtSHUndiEyG8NbhwuN8fFg4leRLD7bIcSTfY7ckXcWUqo4O9AU273aRE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=X0lL+Alh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="X0lL+Alh" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 95E84C4CEE3; Thu, 24 Apr 2025 10:26:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745490409; bh=jtBNyXLItJhfIxTK4Pp6vzdTvnQztzIAhQqNSaBxo3Y=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=X0lL+Alhg7F5HZy+FTpyT9n0TCzhkIOLCSMBG+n0pgEhSuE2cvEyzb0kyM/gj+LTk tdd0Z89BO4OdQKZC9Feg1mrqRZipgSZJ+5hRxyFifVk0Uokd1wT93Our4CiX2SknND 9vD4JprQYgrgaff91AQOSHr6O47gwqlmNpRHrooiMFjKpm9516deNcls/9B2KmsgNn zbjJDQIXj3Fm5xGSZYePfFg+1+le82lrKxN8TKN1BjOcfCQx7MY3gaGfxOToEDG/da FzbKwtwcbx3YHOntrHyy0/sh5RJxYAv+iFnR2u2Y6ddE3LarsjGx4JNGVG0N5F6wiT FDqvDjNs5u6Lg== From: Lorenzo Pieralisi Date: Thu, 24 Apr 2025 12:25:23 +0200 Subject: [PATCH v2 12/22] arm64/sysreg: Add ICH_HFGRTR_EL2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-gicv5-host-v2-12-545edcaf012b@kernel.org> References: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> In-Reply-To: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.14.2 Add ICH_HFGRTR_EL2 register description. Signed-off-by: Lorenzo Pieralisi Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier --- arch/arm64/tools/sysreg | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 1ec8113df713dfea6d38e39c42eba1e3dca5eea5..0c0e805481c84a14ae62d199466= 171d97d54ef90 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -3583,6 +3583,24 @@ Field 31:16 PhyPARTID29 Field 15:0 PhyPARTID28 EndSysreg =20 +Sysreg ICH_HFGRTR_EL2 3 4 12 9 4 +Res0 63:21 +Field 20 ICC_PPI_ACTIVERn_EL1 +Field 19 ICC_PPI_PRIORITYRn_EL1 +Field 18 ICC_PPI_PENDRn_EL1 +Field 17 ICC_PPI_ENABLERn_EL1 +Field 16 ICC_PPI_HMRn_EL1 +Res0 15:8 +Field 7 ICC_IAFFIDR_EL1 +Field 6 ICC_ICSR_EL1 +Field 5 ICC_PCR_EL1 +Field 4 ICC_HPPIR_EL1 +Field 3 ICC_HAPR_EL1 +Field 2 ICC_CR0_EL1 +Field 1 ICC_IDRn_EL1 +Field 0 ICC_APR_EL1 +EndSysreg + Sysreg ICH_HCR_EL2 3 4 12 11 0 Res0 63:32 Field 31:27 EOIcount --=20 2.48.0 From nobody Sun Feb 8 13:09:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9506522CBD8; Thu, 24 Apr 2025 10:26:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490415; cv=none; b=a8MukxooOVPhGZDzNP1cp3siNbBChLibHVPIrfBQ4DIHnMz9qX6TpUcW9grkPpu7lddK4+C1anLRsP1iPNPOh6/taZpJjWTWtdpGnSCc2syJVtEVpZJYs1iExXSq/UbgSyRZtQ0sh1N7/n39qy2WuVo3OrvTaSv4H6dMVkVQc6E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490415; c=relaxed/simple; bh=3IG/dkyf3kNeiDq8iUpch8Bd+BjlFKQ3NbAf5IVjrxM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qB06ui+mRZlRC5TNtQPxnuD8xNB+NOqyOW0IJ+eLHfldVAxtgQoF1TdDTPRj0auk+xIYJ/0+X+jITnaY+A98kv/4WzBt8iDUHbInXWj1HgekRv/r7MCGGAgjhvI+on9H1x5JOJ4hisKThfUe6dj66nOxZ8XtmOZc6yWSivH6ksI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=M28sLNqC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="M28sLNqC" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 46018C4CEE4; Thu, 24 Apr 2025 10:26:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745490415; bh=3IG/dkyf3kNeiDq8iUpch8Bd+BjlFKQ3NbAf5IVjrxM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=M28sLNqC620m8NNrZgATeqJdSe7yKMG2RDnyR6Jf7ZcFygLnMTPr+0Fr7JPr1X0BQ yzOF6EZWn19L9mWBN1MARdfa8p82q9wZy35KNA9tQMu+L3fTf+9tQHgvhKoj+SAu/e 03X6RyLzqpHaOwKbEJ/k5mNH//b79cjCLvs0LVN2kH7KD2helyorXWataIb2bToOe4 DLQJhOpUKAoKLexh2G9NAZa3tRYfcAscu7UlHpOJzEB/5s3fTJ2eHgW355dMhsJxRx BHQcOuL2qxDTD5zwYMB6yl0z0GfY6krxfSB7meTsDmYqODONopxfCSffa632fjkSxx WuwxK3bC/KmJw== From: Lorenzo Pieralisi Date: Thu, 24 Apr 2025 12:25:24 +0200 Subject: [PATCH v2 13/22] arm64/sysreg: Add ICH_HFGWTR_EL2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-gicv5-host-v2-13-545edcaf012b@kernel.org> References: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> In-Reply-To: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.14.2 Add ICH_HFGWTR_EL2 register description to sysreg. Signed-off-by: Lorenzo Pieralisi Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier --- arch/arm64/tools/sysreg | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 0c0e805481c84a14ae62d199466171d97d54ef90..1b519e35000be328acfe26d51e0= 98059f9cf9ef2 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -3601,6 +3601,21 @@ Field 1 ICC_IDRn_EL1 Field 0 ICC_APR_EL1 EndSysreg =20 +Sysreg ICH_HFGWTR_EL2 3 4 12 9 6 +Res0 63:21 +Field 20 ICC_PPI_ACTIVERn_EL1 +Field 19 ICC_PPI_PRIORITYRn_EL1 +Field 18 ICC_PPI_PENDRn_EL1 +Field 17 ICC_PPI_ENABLERn_EL1 +Res0 16:7 +Field 6 ICC_ICSR_EL1 +Field 5 ICC_PCR_EL1 +Res0 4:3 +Field 2 ICC_CR0_EL1 +Res0 1 +Field 0 ICC_APR_EL1 +EndSysreg + Sysreg ICH_HCR_EL2 3 4 12 11 0 Res0 63:32 Field 31:27 EOIcount --=20 2.48.0 From nobody Sun Feb 8 13:09:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06E5E22D790; Thu, 24 Apr 2025 10:27:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490421; cv=none; b=BeWDVTbth6Px80HdgpPCWDR65JcSNutYzixain1BbgIOAINgEfbGxsWa/QpDiN1kY+ybdRD7eaposh1irN0n8VAROzwMuMPN2YSphPgoLao8y8NVVD+OxDbcTpik9d+5UXjpI8lLWBQ4112kKK87TdqMHAN8CYCc31WdI+5zVuc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490421; c=relaxed/simple; bh=9zWp7WGj091+ZG2FSlP0T7J3sn+1tw+UEtNEfbmUjxQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=H4OMAGDggovMc5uMdPnBm4Lmosz+jOsUvwJEwMCbToHvLxSGuQvyjiYGQWm/HRcqoCdY1sMI6365tCog1yvb+qN34CTP+ISlPLFSfCfmloRXTy3ENWvO6SAaH9uiVVWAabbQ4jlT1TZMk32Xvu+Na5u9Wf3xJLKoWmBgW7e2VnU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qu6UUhQJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qu6UUhQJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A5BA1C4CEE3; Thu, 24 Apr 2025 10:26:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745490420; bh=9zWp7WGj091+ZG2FSlP0T7J3sn+1tw+UEtNEfbmUjxQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=qu6UUhQJCxqYrr81iVHhuMy20mqGqJVGW8zuJFIytlavKi7iQx+8yg7t1RAJtkjNu epa1dTe1TlH89+QxPE4kyA5f6+Cd1JwbDbZgAH69e5BfgGi9OcvNamQ/0zxihvopph i8Pdp6H4U6q/b9oDTWJN0PGh5BWMUU4ZlYvmH60jH2z9/96R8inXgyXFfVviEksIiK ZqPUuLPL0GkKiiGHJU+bNKNJUkW4bN90Bgg8vxa1c1YMF2aSqCoEg4U11xu2tR5FF7 GB8q7rJ9JP2R7srQvfsynukmj6W5Zge5asiMBp984NlJuW7HmlS7MMyHBZwJYfBwpk bcSLUsbM7+z+A== From: Lorenzo Pieralisi Date: Thu, 24 Apr 2025 12:25:25 +0200 Subject: [PATCH v2 14/22] arm64/sysreg: Add ICH_HFGITR_EL2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-gicv5-host-v2-14-545edcaf012b@kernel.org> References: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> In-Reply-To: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.14.2 Add ICH_HFGITR_EL2 register description to sysreg. Signed-off-by: Lorenzo Pieralisi Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier --- arch/arm64/tools/sysreg | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 1b519e35000be328acfe26d51e098059f9cf9ef2..5af0dea6e775ea680686dbe4bc8= 36b5f5b69fbc7 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -3616,6 +3616,21 @@ Res0 1 Field 0 ICC_APR_EL1 EndSysreg =20 +Sysreg ICH_HFGITR_EL2 3 4 12 9 7 +Res0 63:11 +Field 10 GICRCDNMIA +Field 9 GICRCDIA +Field 8 GICCDDI +Field 7 GICCDEOI +Field 6 GICCDHM +Field 5 GICCRDRCFG +Field 4 GICCDPEND +Field 3 GICCDAFF +Field 2 GICCDPRI +Field 1 GICCDDIS +Field 0 GICCDEN +EndSysreg + Sysreg ICH_HCR_EL2 3 4 12 11 0 Res0 63:32 Field 31:27 EOIcount --=20 2.48.0 From nobody Sun Feb 8 13:09:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E126D22D7B2; Thu, 24 Apr 2025 10:27:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490426; cv=none; b=ZturyCXCpagB9JEH93aa1oJF/JbpWZvkZBX4xRR97TA01/kTjnKpHQjj3SqcuXr9JpEkbdps2O5B8OdjbmFi165SbjO8QeMtCDWjY7KsO0x6lcm6vBfwV1RWliSuj6olZurj9FwEEQcErDw/09gqC9LPQZxYm0QHw+beqjMZQAE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490426; c=relaxed/simple; bh=sVDAwu7zYs5UYmhKsIqu4Xi0KrfAlQzxvPf603/w1qs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mh1jgE6PtGREoY/OVCiE4xKdm1mtDfZvU8PM4RvT0+Hn4yCquX9s1yqWpZ0kNAdn0edxn0FfqouW6/R3gxUr5NV4yiCNRZvY/YHYAvAEXN+SQxdK4TdhyGo3RxZx3hAUsCEn2t1rp1yvIHEkzZuNex1BmLZxH5Clm8AVuhUapp8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NzM267PE; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NzM267PE" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1D1CCC4CEE4; Thu, 24 Apr 2025 10:27:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745490425; bh=sVDAwu7zYs5UYmhKsIqu4Xi0KrfAlQzxvPf603/w1qs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=NzM267PEMO2IMqbSaEpPxJsVB5eAVB3PjRE0DQnnRhBZcG8xXm+/3b23qQMfoft51 nER8G4hqF7RSDaQCrK4/hrNw+BJfOq7EkV3eCoGJu8yRkgUZktUjbxuYbr/n7hZg9e gBZCjOgZOl4nw/3Cc6Lki0f26Eep81WYh0rWLb5fDbqXatP07v81am6DsBkoXS6aCD ib8suaDHL1/ZeJM6rbgH2HJ3kjPHc1lbkLK4SpGLe0hPNUks7t7a/aJUxj7j+xWWeH JiFJ5ksM7HrgOi2VwUMN7nd3RVKaLlqVPsf/LaTU37pc1b9MluP1C66+X7FSTzePAo VDgLVOYpOmapA== From: Lorenzo Pieralisi Date: Thu, 24 Apr 2025 12:25:26 +0200 Subject: [PATCH v2 15/22] arm64: Disable GICv5 read/write/instruction traps Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-gicv5-host-v2-15-545edcaf012b@kernel.org> References: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> In-Reply-To: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.14.2 GICv5 trap configuration registers value is UNKNOWN at reset. Initialize GICv5 EL2 trap configuration registers to prevent trapping GICv5 instruction/register access upon entering the kernel. Signed-off-by: Lorenzo Pieralisi Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier --- arch/arm64/include/asm/el2_setup.h | 45 ++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el= 2_setup.h index ebceaae3c749b84395c9c5eccf0caf874697ad11..1e362bb3b042d51fff15a7c2abc= 73842930b275a 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -165,6 +165,50 @@ .Lskip_gicv3_\@: .endm =20 +/* GICv5 system register access */ +.macro __init_el2_gicv5 + mrs_s x0, SYS_ID_AA64PFR2_EL1 + ubfx x0, x0, #ID_AA64PFR2_EL1_GCIE_SHIFT, #4 + cbz x0, .Lskip_gicv5_\@ + + mov x0, #(1 << ICH_HFGITR_EL2_GICRCDNMIA_SHIFT | \ + 1 << ICH_HFGITR_EL2_GICRCDIA_SHIFT | \ + 1 << ICH_HFGITR_EL2_GICCDDI_SHIFT | \ + 1 << ICH_HFGITR_EL2_GICCDEOI_SHIFT | \ + 1 << ICH_HFGITR_EL2_GICCDHM_SHIFT | \ + 1 << ICH_HFGITR_EL2_GICCRDRCFG_SHIFT | \ + 1 << ICH_HFGITR_EL2_GICCDPEND_SHIFT | \ + 1 << ICH_HFGITR_EL2_GICCDAFF_SHIFT | \ + 1 << ICH_HFGITR_EL2_GICCDPRI_SHIFT | \ + 1 << ICH_HFGITR_EL2_GICCDDIS_SHIFT | \ + 1 << ICH_HFGITR_EL2_GICCDEN_SHIFT) + msr_s SYS_ICH_HFGITR_EL2, x0 // Disable instruction traps + mov_q x0, (1 << ICH_HFGRTR_EL2_ICC_PPI_ACTIVERn_EL1_SHIFT | \ + 1 << ICH_HFGRTR_EL2_ICC_PPI_PRIORITYRn_EL1_SHIFT | \ + 1 << ICH_HFGRTR_EL2_ICC_PPI_PENDRn_EL1_SHIFT | \ + 1 << ICH_HFGRTR_EL2_ICC_PPI_ENABLERn_EL1_SHIFT | \ + 1 << ICH_HFGRTR_EL2_ICC_PPI_HMRn_EL1_SHIFT | \ + 1 << ICH_HFGRTR_EL2_ICC_IAFFIDR_EL1_SHIFT | \ + 1 << ICH_HFGRTR_EL2_ICC_ICSR_EL1_SHIFT | \ + 1 << ICH_HFGRTR_EL2_ICC_PCR_EL1_SHIFT | \ + 1 << ICH_HFGRTR_EL2_ICC_HPPIR_EL1_SHIFT | \ + 1 << ICH_HFGRTR_EL2_ICC_HAPR_EL1_SHIFT | \ + 1 << ICH_HFGRTR_EL2_ICC_CR0_EL1_SHIFT | \ + 1 << ICH_HFGRTR_EL2_ICC_IDRn_EL1_SHIFT | \ + 1 << ICH_HFGRTR_EL2_ICC_APR_EL1_SHIFT) + msr_s SYS_ICH_HFGRTR_EL2, x0 // Disable reg read traps + mov_q x0, (1 << ICH_HFGWTR_EL2_ICC_PPI_ACTIVERn_EL1_SHIFT | \ + 1 << ICH_HFGWTR_EL2_ICC_PPI_PRIORITYRn_EL1_SHIFT | \ + 1 << ICH_HFGWTR_EL2_ICC_PPI_PENDRn_EL1_SHIFT | \ + 1 << ICH_HFGWTR_EL2_ICC_PPI_ENABLERn_EL1_SHIFT | \ + 1 << ICH_HFGWTR_EL2_ICC_ICSR_EL1_SHIFT | \ + 1 << ICH_HFGWTR_EL2_ICC_PCR_EL1_SHIFT | \ + 1 << ICH_HFGWTR_EL2_ICC_CR0_EL1_SHIFT | \ + 1 << ICH_HFGWTR_EL2_ICC_APR_EL1_SHIFT) + msr_s SYS_ICH_HFGWTR_EL2, x0 // Disable reg write traps +.Lskip_gicv5_\@: +.endm + .macro __init_el2_hstr msr hstr_el2, xzr // Disable CP15 traps to EL2 .endm @@ -323,6 +367,7 @@ __init_el2_lor __init_el2_stage2 __init_el2_gicv3 + __init_el2_gicv5 __init_el2_hstr __init_el2_mpam __init_el2_nvhe_idregs --=20 2.48.0 From nobody Sun Feb 8 13:09:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8C2C22D7B2; Thu, 24 Apr 2025 10:27:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490431; cv=none; b=SX28LkgCT0JXt2CIXTkZoCI73DEXf3nNYwFKFoW1m6GMsCTooQAMpo6sx7u/bhEMp4Yv5MH+QnktD4jBRHmUyh7zszy/y14nnE1nyTSvu/JHQMhmM57gPEwC/4vADf/KVAPDNeWFaTmCugz6jHqisUh0Slh0cYYW7pX5tp/zPiY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490431; c=relaxed/simple; bh=J4d+23jK1xcMwImyyVNILtAarSzyfyzelW1CaxCFjwc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lMxmgH5OZhrXhU0+xFvuWjKSN5ZevUYles/+JV6w7A5MjA0ovqMbjAbe8iwemOZmaN4APtXJoHdLsVGrgqZ0/eCVgeLTwJcyNvuqkH688CRoxK71AFdC3qYNjThVHEJpZ8n3xrYldDFTwQWT2VsfCjND4eINBtlWW3sOCYCGmmQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=sgnqQgko; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="sgnqQgko" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 650B8C4CEE3; Thu, 24 Apr 2025 10:27:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745490431; bh=J4d+23jK1xcMwImyyVNILtAarSzyfyzelW1CaxCFjwc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=sgnqQgkolXvCAUAVaMDrIlPvEjmlTuL5qCUpb6+DHJOabe51gFynNShfu8X4dEIYf 1iW5OCmBNtzN2u2qpvcQ1e5zwTRcyQMYq6AwWjTOjXw3VolnOP2F6ROc/kjNLeWPdw dlPTfryWu1zzxYyhDaDJfFIq39V23tFhfJ/ZoAkU0mkLSZvCEGlnHujXytPTWwIsjk I4QeH1p3/KzdX+R7Q7VRC39pSk9ROIcF7tlsHNXcwr+B91+5gjGAn1Q8jn3Evmilxt bf7GFWoTyn+EwbqqfP3ELbKO6bYsy19QXHNCHHoWCjOWC0MIPHbfaIvmbwQg0Kt5R6 5DgpNciUSoNOw== From: Lorenzo Pieralisi Date: Thu, 24 Apr 2025 12:25:27 +0200 Subject: [PATCH v2 16/22] arm64: cpucaps: Rename GICv3 CPU interface capability Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-gicv5-host-v2-16-545edcaf012b@kernel.org> References: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> In-Reply-To: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.14.2 In preparation for adding a GICv5 CPU interface capability, rework the existing GICv3 CPUIF capability - change its name and description so that the subsequent GICv5 CPUIF capability can be added with a more consistent naming on top. Suggested-by: Mark Rutland Signed-off-by: Lorenzo Pieralisi Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier --- arch/arm64/kernel/cpufeature.c | 10 +++++----- arch/arm64/tools/cpucaps | 2 +- drivers/irqchip/irq-gic.c | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 9c4d6d552b25cb3a31d1fb267bd73d3f82513e69..cbb49de451f45fbee3100ea01e7= 7b06352bd55ac 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2283,11 +2283,11 @@ static bool can_use_gic_priorities(const struct arm= 64_cpu_capabilities *entry, int scope) { /* - * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU + * ARM64_HAS_GICV3_CPUIF has a lower index, and is a boot CPU * feature, so will be detected earlier. */ - BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <=3D ARM64_HAS_GIC_CPUIF_SYSREGS); - if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS)) + BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <=3D ARM64_HAS_GICV3_CPUIF); + if (!cpus_have_cap(ARM64_HAS_GICV3_CPUIF)) return false; =20 return enable_pseudo_nmi; @@ -2483,8 +2483,8 @@ static const struct arm64_cpu_capabilities arm64_feat= ures[] =3D { .matches =3D has_always, }, { - .desc =3D "GIC system register CPU interface", - .capability =3D ARM64_HAS_GIC_CPUIF_SYSREGS, + .desc =3D "GICv3 CPU interface", + .capability =3D ARM64_HAS_GICV3_CPUIF, .type =3D ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, .matches =3D has_useable_gicv3_cpuif, ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 772c1b008e437ed34cedb1c0f663c4dcea8f6759..860ec49cc0530885c138b7dc7f6= 7d58cd69b2593 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -34,7 +34,7 @@ HAS_GENERIC_AUTH HAS_GENERIC_AUTH_ARCH_QARMA3 HAS_GENERIC_AUTH_ARCH_QARMA5 HAS_GENERIC_AUTH_IMP_DEF -HAS_GIC_CPUIF_SYSREGS +HAS_GICV3_CPUIF HAS_GIC_PRIO_MASKING HAS_GIC_PRIO_RELAXED_SYNC HAS_HCR_NV1 diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 6503573557fdf295bc543b16b64e3e7dd6841321..1269ab8eb726afbb80849fd0626= 12861680cb4d1 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -54,7 +54,7 @@ =20 static void gic_check_cpu_features(void) { - WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_GIC_CPUIF_SYSREGS), + WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_GICV3_CPUIF), TAINT_CPU_OUT_OF_SPEC, "GICv3 system registers enabled, broken firmware!\n"); } --=20 2.48.0 From nobody Sun Feb 8 13:09:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D9FF256C71; Thu, 24 Apr 2025 10:27:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490437; cv=none; b=MSLH22CYsegyc2kkMg/4nI9nRE6O1+FkYvJkcN2CQDztJJm0dhML0uLYdP7dDMKMVdm6CJ5uBQnRgrfIV6wqXFBf9YOQYcczDIP98iejraLgUNX1PVfeUmhtexjFqEY7WBHKc7LjZpi8w4ZMDT4dFC/yWMalx0x6lxoJ2clIEBM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490437; c=relaxed/simple; bh=dDrbPic70xFVMnGI2U6eslEy81yc+v4juJuGar89STY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Sa2zD/5mR7TyG/Cp5c1R+7HU/r1Z53LNmL1e5FgIBSBt1hXJfMk1AdAwXm4TgcYOgFKzN1JdSAPQA/iuiiAWLyexhLn3yZpz7hxFpyhcqPZN+JFUsayIV1EiSBwfQesA+9W07/5zqOi7oNyG8gi2SHrGfQYains7IBXOAjxmpqQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=D0pECic4; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="D0pECic4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E2020C4CEEB; Thu, 24 Apr 2025 10:27:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745490437; bh=dDrbPic70xFVMnGI2U6eslEy81yc+v4juJuGar89STY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=D0pECic4PC1ECNiE9KxvONqdcV7iY4sJIJDtHj4rLRslWAbzxGFs1oSYxsOKXkGms gnUL05IYWX76PpfA5m7tbErBTnee48PVME5h2C96Hv5w8XM7orAu5i06X5DCV42pdA 7Ar+43dQ7dwnqFEZfFlrm/0aterhtNk29pEOpy0dq5H4beeh2XwllciYhTvZhqccyh yWP9AHiJdCzt5mKle4W45rOs7rndYEAsLuImHz3XErx6sY8Mm5+pqiHIQ9EIq5OGID u4vDHKRRHcUN72uzu+QVJP3qZkkqMmlhWUGoDstbyXwId/MiPNGOgtomsyJ8RGCAgO jXhRJoznbcp6A== From: Lorenzo Pieralisi Date: Thu, 24 Apr 2025 12:25:28 +0200 Subject: [PATCH v2 17/22] arm64: cpucaps: Add GICv5 CPU interface (GCIE) capability Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-gicv5-host-v2-17-545edcaf012b@kernel.org> References: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> In-Reply-To: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.14.2 Implement the GCIE capability as a strict boot cpu capability to detect whether architectural GICv5 support is available in HW. Plug it in with a naming consistent with the existing GICv3 CPU interface capability. Signed-off-by: Lorenzo Pieralisi Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier --- arch/arm64/kernel/cpufeature.c | 7 +++++++ arch/arm64/tools/cpucaps | 1 + 2 files changed, 8 insertions(+) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index cbb49de451f45fbee3100ea01e77b06352bd55ac..4d5163a20ee0fb09380ea5f1f2d= 37afb7257edfb 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -3041,6 +3041,13 @@ static const struct arm64_cpu_capabilities arm64_fea= tures[] =3D { .matches =3D has_pmuv3, }, #endif + { + .desc =3D "GICv5 CPU interface", + .type =3D ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, + .capability =3D ARM64_HAS_GICV5_CPUIF, + .matches =3D has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, GCIE, IMP) + }, {}, }; =20 diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 860ec49cc0530885c138b7dc7f67d58cd69b2593..c36f4165e2bb460abde81baf453= 199f62dd265b0 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -35,6 +35,7 @@ HAS_GENERIC_AUTH_ARCH_QARMA3 HAS_GENERIC_AUTH_ARCH_QARMA5 HAS_GENERIC_AUTH_IMP_DEF HAS_GICV3_CPUIF +HAS_GICV5_CPUIF HAS_GIC_PRIO_MASKING HAS_GIC_PRIO_RELAXED_SYNC HAS_HCR_NV1 --=20 2.48.0 From nobody Sun Feb 8 13:09:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EF2922F743; Thu, 24 Apr 2025 10:27:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490442; cv=none; b=QkI4tPSXRuaGyrTk1UfG/kCojygbmfMrhwjZBxYYMnKL4ele95V64GXZcAJtDDM4aMajESPDX8V1i7nDLr4uLsstzu6Yyp8A91wKQtFZs0e+wpxDkgFZZqKqhxd66l0WjbZ2Rn1dsUPQsnxrcbQZDrVxGxWgxOFjqN+rmZuisTM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490442; c=relaxed/simple; bh=WxlJpUqowBsQvYZOUMs8IGUAxzbj1n5Ter/RIBHuc/M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZeRW8BF3HpHS9ashVVZUfnv8bmbGyFW7fPrjmA8B85BrQf/2rRWw/oiS7hJ6dN+lj5jq6tzbRTEwHulFt8tH4OjeCA1B/mtuIPiEpyZj4m7xaUKJV/LGgfjCdXrFezw6WkpOZ8oOMIP5EiMJ2ifDlIFGB+0AHH8WqZVVlEGgsKs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XkT7lybK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XkT7lybK" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BD1FEC4CEE3; Thu, 24 Apr 2025 10:27:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745490442; bh=WxlJpUqowBsQvYZOUMs8IGUAxzbj1n5Ter/RIBHuc/M=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=XkT7lybKmy1loRTSYZkzmD1m6qbGObPFYJR/K+VvEkygVUO+oE0BUdnhDKO+qlNsr MhXh3CJatMmiyATJpLey//LlsiXL/RTyKu0ihlodnxaYBXysH5kmp50QvcLbNQR3/U 8xHQpXKCXnfqvNPC5vCXhz6JDTqirLbp9MqF4ycYXhCrtfdcfGJgl4Pnaf4NPV8yii mHMP2dZoPoWp9GUZdvurQ9KiZAQu7GhiJ+i5JjJQyMcNUxBfZ3Z+zoAQ28U4TECVTu 9hynfUNOjg1eSiW6/F803/VZFNz6zt1BCI0q9olJO8eC8N9OXJwlMomup4MsBrjNT/ 4KbnMMdqLRbEw== From: Lorenzo Pieralisi Date: Thu, 24 Apr 2025 12:25:29 +0200 Subject: [PATCH v2 18/22] arm64: smp: Support non-SGIs for IPIs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-gicv5-host-v2-18-545edcaf012b@kernel.org> References: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> In-Reply-To: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.14.2 From: Marc Zyngier The arm64 arch has relied so far on GIC architectural software generated interrupt (SGIs) to handle IPIs. Those are per-cpu software generated interrupts. arm64 architecture code that allocates the IPIs virtual IRQs and IRQ descriptors was written accordingly. On GICv5 systems, IPIs are implemented using LPIs that are not per-cpu interrupts - they are just normal routable IRQs. Add arch code to set-up IPIs on systems where they are handled using normal routable IRQs. For those systems, force the IRQ affinity (and make it immutable) to the cpu a given IRQ was assigned to. Signed-off-by: Marc Zyngier [timothy.hayes@arm.com: fixed ipi/irq conversion, irq flags] Signed-off-by: Timothy Hayes [lpieralisi: changed affinity set-up, log] Signed-off-by: Lorenzo Pieralisi Cc: Will Deacon Cc: Catalin Marinas --- arch/arm64/include/asm/smp.h | 7 ++- arch/arm64/kernel/smp.c | 139 ++++++++++++++++++++++++++++++++-------= ---- 2 files changed, 111 insertions(+), 35 deletions(-) diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h index 2510eec026f7e3d6f0ecf1197c3a81b183ddd216..d6fd6efb66a673ae33825971e4a= a07e791c02ee5 100644 --- a/arch/arm64/include/asm/smp.h +++ b/arch/arm64/include/asm/smp.h @@ -53,7 +53,12 @@ extern void smp_init_cpus(void); /* * Register IPI interrupts with the arch SMP code */ -extern void set_smp_ipi_range(int ipi_base, int nr_ipi); +extern void set_smp_ipi_range_percpu(int ipi_base, int nr_ipi, int ncpus); + +static inline void set_smp_ipi_range(int ipi_base, int n) +{ + set_smp_ipi_range_percpu(ipi_base, n, 0); +} =20 /* * Called from the secondary holding pen, this is the secondary CPU entry = point. diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 3b3f6b56e733039cad7ff5b8995db16a68f3c762..3f3712e47c94c62836fb89cd4bf= b3595fbb41557 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -83,7 +83,26 @@ enum ipi_msg_type { =20 static int ipi_irq_base __ro_after_init; static int nr_ipi __ro_after_init =3D NR_IPI; -static struct irq_desc *ipi_desc[MAX_IPI] __ro_after_init; + +struct ipi_descs { + struct irq_desc *descs[MAX_IPI]; +}; + +static DEFINE_PER_CPU(struct ipi_descs, pcpu_ipi_desc); + +#define get_ipi_desc(__cpu, __ipi) (per_cpu_ptr(&pcpu_ipi_desc, __cpu)->de= scs[__ipi]) + +static bool percpu_ipi_descs __ro_after_init; + +static int ipi_to_irq(int ipi, int cpu) +{ + return ipi_irq_base + (cpu * nr_ipi) + ipi; +} + +static int irq_to_ipi(int irq) +{ + return (irq - ipi_irq_base) % nr_ipi; +} =20 static bool crash_stop; =20 @@ -844,7 +863,7 @@ int arch_show_interrupts(struct seq_file *p, int prec) seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i, prec >=3D 4 ? " " : ""); for_each_online_cpu(cpu) - seq_printf(p, "%10u ", irq_desc_kstat_cpu(ipi_desc[i], cpu)); + seq_printf(p, "%10u ", irq_desc_kstat_cpu(get_ipi_desc(cpu, i), cpu)); seq_printf(p, " %s\n", ipi_types[i]); } =20 @@ -919,7 +938,13 @@ static void __noreturn ipi_cpu_crash_stop(unsigned int= cpu, struct pt_regs *regs =20 static void arm64_backtrace_ipi(cpumask_t *mask) { - __ipi_send_mask(ipi_desc[IPI_CPU_BACKTRACE], mask); + unsigned int cpu; + + if (!percpu_ipi_descs) + __ipi_send_mask(get_ipi_desc(0, IPI_CPU_BACKTRACE), mask); + else + for_each_cpu(cpu, mask) + __ipi_send_single(get_ipi_desc(cpu, IPI_CPU_BACKTRACE), cpu); } =20 void arch_trigger_cpumask_backtrace(const cpumask_t *mask, int exclude_cpu) @@ -944,7 +969,7 @@ void kgdb_roundup_cpus(void) if (cpu =3D=3D this_cpu) continue; =20 - __ipi_send_single(ipi_desc[IPI_KGDB_ROUNDUP], cpu); + __ipi_send_single(get_ipi_desc(cpu, IPI_KGDB_ROUNDUP), cpu); } } #endif @@ -1013,14 +1038,21 @@ static void do_handle_IPI(int ipinr) =20 static irqreturn_t ipi_handler(int irq, void *data) { - do_handle_IPI(irq - ipi_irq_base); + do_handle_IPI(irq_to_ipi(irq)); return IRQ_HANDLED; } =20 static void smp_cross_call(const struct cpumask *target, unsigned int ipin= r) { + unsigned int cpu; + trace_ipi_raise(target, ipi_types[ipinr]); - __ipi_send_mask(ipi_desc[ipinr], target); + + if (!percpu_ipi_descs) + __ipi_send_mask(get_ipi_desc(0, ipinr), target); + else + for_each_cpu(cpu, target) + __ipi_send_single(get_ipi_desc(cpu, ipinr), cpu); } =20 static bool ipi_should_be_nmi(enum ipi_msg_type ipi) @@ -1046,11 +1078,15 @@ static void ipi_setup(int cpu) return; =20 for (i =3D 0; i < nr_ipi; i++) { - if (ipi_should_be_nmi(i)) { - prepare_percpu_nmi(ipi_irq_base + i); - enable_percpu_nmi(ipi_irq_base + i, 0); + if (!percpu_ipi_descs) { + if (ipi_should_be_nmi(i)) { + prepare_percpu_nmi(ipi_irq_base + i); + enable_percpu_nmi(ipi_irq_base + i, 0); + } else { + enable_percpu_irq(ipi_irq_base + i, 0); + } } else { - enable_percpu_irq(ipi_irq_base + i, 0); + enable_irq(irq_desc_get_irq(get_ipi_desc(cpu, i))); } } } @@ -1064,44 +1100,79 @@ static void ipi_teardown(int cpu) return; =20 for (i =3D 0; i < nr_ipi; i++) { - if (ipi_should_be_nmi(i)) { - disable_percpu_nmi(ipi_irq_base + i); - teardown_percpu_nmi(ipi_irq_base + i); + if (!percpu_ipi_descs) { + if (ipi_should_be_nmi(i)) { + disable_percpu_nmi(ipi_irq_base + i); + teardown_percpu_nmi(ipi_irq_base + i); + } else { + disable_percpu_irq(ipi_irq_base + i); + } } else { - disable_percpu_irq(ipi_irq_base + i); + disable_irq(irq_desc_get_irq(get_ipi_desc(cpu, i))); } } } #endif =20 -void __init set_smp_ipi_range(int ipi_base, int n) +static void ipi_setup_ppi(int ipi) +{ + int err, irq, cpu; + + irq =3D ipi_irq_base + ipi; + + if (ipi_should_be_nmi(irq)) { + err =3D request_percpu_nmi(irq, ipi_handler, "IPI", &irq_stat); + WARN(err, "Could not request IRQ %d as NMI, err=3D%d\n", irq, err); + } else { + err =3D request_percpu_irq(irq, ipi_handler, "IPI", &irq_stat); + WARN(err, "Could not request IRQ %d as IRQ, err=3D%d\n", irq, err); + } + + for_each_possible_cpu(cpu) + get_ipi_desc(cpu, ipi) =3D irq_to_desc(irq); + + irq_set_status_flags(irq, IRQ_HIDDEN); +} + +static void ipi_setup_lpi(int ipi, int ncpus) +{ + for (int cpu =3D 0; cpu < ncpus; cpu++) { + int err, irq; + + irq =3D ipi_to_irq(ipi, cpu); + + err =3D irq_force_affinity(irq, cpumask_of(cpu)); + + WARN(err, "Could not force affinity IRQ %d, err=3D%d\n", irq, err); + + err =3D request_irq(irq, ipi_handler, IRQF_NO_AUTOEN, "IPI", + &irq_stat); + + WARN(err, "Could not request IRQ %d, err=3D%d\n", irq, err); + + irq_set_status_flags(irq, (IRQ_HIDDEN | IRQ_NO_BALANCING_MASK)); + + get_ipi_desc(cpu, ipi) =3D irq_to_desc(irq); + } +} + +void __init set_smp_ipi_range_percpu(int ipi_base, int n, int ncpus) { int i; =20 WARN_ON(n < MAX_IPI); nr_ipi =3D min(n, MAX_IPI); =20 - for (i =3D 0; i < nr_ipi; i++) { - int err; - - if (ipi_should_be_nmi(i)) { - err =3D request_percpu_nmi(ipi_base + i, ipi_handler, - "IPI", &irq_stat); - WARN(err, "Could not request IPI %d as NMI, err=3D%d\n", - i, err); - } else { - err =3D request_percpu_irq(ipi_base + i, ipi_handler, - "IPI", &irq_stat); - WARN(err, "Could not request IPI %d as IRQ, err=3D%d\n", - i, err); - } - - ipi_desc[i] =3D irq_to_desc(ipi_base + i); - irq_set_status_flags(ipi_base + i, IRQ_HIDDEN); - } - + percpu_ipi_descs =3D !!ncpus; ipi_irq_base =3D ipi_base; =20 + for (i =3D 0; i < nr_ipi; i++) { + if (!percpu_ipi_descs) + ipi_setup_ppi(i); + else + ipi_setup_lpi(i, ncpus); + } + /* Setup the boot CPU immediately */ ipi_setup(smp_processor_id()); } --=20 2.48.0 From nobody Sun Feb 8 13:09:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60F24225785; Thu, 24 Apr 2025 10:27:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490448; cv=none; b=UEDoTryDjVAZabIutP7VCEfRzu7agTAgsnmpE3I7xjyUCz5wO7rreceRQ2PZQpH+spJLquG2Q4phjW/MZuslz1JFsH5tdPVIuEbzrzxU0p6CXZaRiRM1mIcDQs150kK9KjernbB+jjI0PcDwkEFGlGEl5tdeqIcnK94EuWmcVvc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490448; c=relaxed/simple; bh=kVmUOsoYAffCkj0BDSiaisYdEeHtGHN8RCJylQNCwn4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NWWXEblyVSkdtLRhrT/3Jcuo1cXTt0lQDNc2Al6HI6he8i4q9QZjas7+yhc5+h8bk0oPxSGU5PXyv5R7pcF/ZqIzRVJF1VHhS5P7b44I2BNBz7u4XJGzSRBi1f6hUYnvbEaZsXBUuYONYIE9YbZWm/e5kF9w+9h3tQVOwjsusHY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SlZh337e; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SlZh337e" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 14F70C4CEE3; Thu, 24 Apr 2025 10:27:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745490448; bh=kVmUOsoYAffCkj0BDSiaisYdEeHtGHN8RCJylQNCwn4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=SlZh337ecGjw8IRclRHeDtqsRimlYJMsnwvRBsiJNO96jqJTjgHs1NEMQmYriU4xU VCufKcQHVPCoKjuF5hW1Qivq43kNsJlCBXPuawfk+v2eZWwcqnOJvNkEH1mVRjYdVj Yboz+QCFINhh7js9m73ijcM0kUBe9SuZQ8tz7Xtehj0ZkRE0LMYmnyQsWn29/q1cx2 uqPvr3EVmyebcapyvCES4aGk+Tebh8s70INmolZjPhLDImqmqdXmb2Qk6/dB6pzJRi XjdvgQoigQ0r4nDllnRKzrccrodTsvQQ4paIy6zY2YJtqmrZptgBk7zzzpScwbyOZg uSaBJDuQ33ZSw== From: Lorenzo Pieralisi Date: Thu, 24 Apr 2025 12:25:30 +0200 Subject: [PATCH v2 19/22] irqchip/gic-v5: Add GICv5 CPU interface/IRS support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-gicv5-host-v2-19-545edcaf012b@kernel.org> References: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> In-Reply-To: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.14.2 Implement GICv5 CPU interface and IRS support, to manage interrupt state, priority and routing for all GICv5 interrupt types. The GICv5 CPU interface implements support for PE-Private Peripheral Interrupts (PPI), that are handled (enabled/prioritized/delivered) entirely within the CPU interface hardware. To enable PPI interrupts, implement the baseline GICv5 host kernel driver infrastructure required to handle interrupts on a GICv5 system. Add the exception handling code path and definitions for GICv5 instructions. Add GICv5 PPI handling code as a specific IRQ domain to: - Set-up PPI priority - Manage PPI configuration and state - Manage IRQ flow handler - IRQs allocation/free - Hook-up a PPI specific IRQchip to provide the relevant methods PPI IRQ priority is chosen as the minimum allowed priority by the system design (after probing the number of priority bits implemented by the CPU interface). The GICv5 Interrupt Routing Service (IRS) component implements interrupt management and routing in the GICv5 architecture. A GICv5 system comprises one or more IRSes, that together handle the interrupt routing and state for the system. An IRS supports Shared Peripheral Interrupts (SPIs), that are interrupt sources directly connected to the IRS; they do not rely on memory for storage. The number of supported SPIs is fixed for a given implementation and can be probed through IRS IDR registers. SPI interrupt state and routing are managed through GICv5 instructions. Each core (PE in GICv5 terms) in a GICv5 system is identified with an Interrupt AFFinity ID (IAFFID). An IRS manages a set of cores that are connected to it. Firmware provides a topology description that the driver uses to detect to which IRS a CPU (ie an IAFFID) is associated with. Use probeable information and firmware description to initialize the IRSes and implement GICv5 IRS SPIs support through an SPI-specific IRQ domain. The GICv5 IRS driver: - Probes IRSes in the system to detect SPI ranges - Associates an IRS with a set of cores connected to it - Adds an IRQchip structure for SPI handling SPIs priority is set to a value corresponding to the lowest permissible priority in the system (taking into account the implemented priority bits of the IRS and CPU interface). Since all IRQs are set to the same priority value, the value itself does not matter as long as it is a valid one. An IRS supports Logical Peripheral Interrupts (LPIs) and implement Linux IPIs on top of it. LPIs are used for interrupt signals that are translated by a GICv5 ITS (Interrupt Translation Service) but also for software generated IRQs - namely interrupts that are not driven by a HW signal, ie IPIs. LPIs rely on memory storage for interrupt routing and state. Memory storage is handled by the IRS - that is configured at probe time by the driver with the required memory. LPIs state and routing information is kept in the Interrupt State Table (IST). IRSes provide support for 1- or 2-level IST tables configured to support a maximum number of interrupts that depend on the OS configuration and the HW capabilities. On systems that provide 2-level IST support, always allow the maximum number of LPIs; On systems with only 1-level support, limit the number of LPIs to 2^12 to prevent wasting memory (presumably a system that supports a 1-level only IST is not expecting a large number of interrupts). On a 2-level IST system, L2 entries are allocated on demand. The IST table memory is allocated using the kmalloc() interface; the allocation required may be smaller than a page and must be made up of contiguous physical pages if larger than a page. On systems where the IRS is not cache-coherent with the CPUs, cache mainteinance operations are executed to clean and invalidate the allocated memory to the point of coherency making it visible to the IRS components. Add an LPI IRQ domain to: - Manage LPI state and routing - Add LPI IRQchip structure and callbacks - LPI domain allocation/de-allocation On GICv5 systems, IPIs are implemented using LPIs. Implement an IPI-specific IRQ domain created as a child/subdomain of the LPI domain to allocate the required number of LPIs needed to implement the IPIs. Move the arm64 IPI enum declaration to a header file so that the GICv5 driver code can detect how many IPIs are required by arch code. IPIs are backed by LPIs, add LPIs allocation/de-allocation functions. The LPI INTID namespace is managed using an IDA to alloc/free LPI INTIDs. Associate an IPI irqchip with IPI IRQ descriptors to provide core code with the irqchip.ipi_send_single() method required to raise an IPI. Co-developed-by: Sascha Bischoff Signed-off-by: Sascha Bischoff Co-developed-by: Timothy Hayes Signed-off-by: Timothy Hayes Signed-off-by: Lorenzo Pieralisi Cc: Will Deacon Cc: Thomas Gleixner Cc: Catalin Marinas Cc: Marc Zyngier --- MAINTAINERS | 2 + arch/arm64/include/asm/arch_gicv5.h | 91 +++ arch/arm64/include/asm/smp.h | 17 + arch/arm64/kernel/smp.c | 17 - drivers/irqchip/Kconfig | 5 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-gic-v5-irs.c | 841 ++++++++++++++++++++++++++++ drivers/irqchip/irq-gic-v5.c | 1058 +++++++++++++++++++++++++++++++= ++++ drivers/irqchip/irq-gic-v5.h | 184 ++++++ 9 files changed, 2199 insertions(+), 17 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index f3ed84466da19906953b5396a5f4b50e878c376e..cdeceb6782355a4a18609135bf7= f03249d8b0bb5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1907,6 +1907,8 @@ M: Marc Zyngier L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml +F: arch/arm64/include/asm/arch_gicv5.h +F: drivers/irqchip/irq-gic-v5*.[ch] =20 ARM HDLCD DRM DRIVER M: Liviu Dudau diff --git a/arch/arm64/include/asm/arch_gicv5.h b/arch/arm64/include/asm/a= rch_gicv5.h new file mode 100644 index 0000000000000000000000000000000000000000..75557fdad611fa51d7136126eb8= 0cb861be98a8d --- /dev/null +++ b/arch/arm64/include/asm/arch_gicv5.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 ARM Ltd. + */ +#ifndef __ASM_ARCH_GICV5_H +#define __ASM_ARCH_GICV5_H + +#include +#include + +#ifndef __ASSEMBLY__ + +#define GICV5_OP_GIC_CDAFF sys_insn(1, 0, 12, 1, 3) +#define GICV5_OP_GIC_CDDI sys_insn(1, 0, 12, 2, 0) +#define GICV5_OP_GIC_CDDIS sys_insn(1, 0, 12, 1, 0) +#define GICV5_OP_GIC_CDEN sys_insn(1, 0, 12, 1, 1) +#define GICV5_OP_GIC_CDEOI sys_insn(1, 0, 12, 1, 7) +#define GICV5_OP_GIC_CDPEND sys_insn(1, 0, 12, 1, 4) +#define GICV5_OP_GIC_CDPRI sys_insn(1, 0, 12, 1, 2) +#define GICV5_OP_GIC_CDRCFG sys_insn(1, 0, 12, 1, 5) +#define GICV5_OP_GICR_CDIA sys_insn(1, 0, 12, 3, 0) + +#define gicr_insn(insn) read_sysreg_s(insn) +#define gic_insn(v, insn) write_sysreg_s(v, insn) + +#define GSB_ACK __emit_inst(0xd5000000 | sys_insn(1, 0, 12, 0, 1) | 31) +#define GSB_SYS __emit_inst(0xd5000000 | sys_insn(1, 0, 12, 0, 0) | 31) + +#define gsb_ack() asm volatile(GSB_ACK : : : "memory") +#define gsb_sys() asm volatile(GSB_SYS : : : "memory") + +/* Shift and mask definitions for GIC CDAFF */ +#define GICV5_GIC_CDAFF_IAFFID_MASK GENMASK_ULL(47, 32) +#define GICV5_GIC_CDAFF_IAFFID(r) FIELD_GET(GICV5_GIC_CDAFF_IAFFID_MASK, r) +#define GICV5_GIC_CDAFF_TYPE_MASK GENMASK_ULL(31, 29) +#define GICV5_GIC_CDAFF_TYPE(r) FIELD_GET(GICV5_GIC_CDAFF_TYPE_MASK, r) +#define GICV5_GIC_CDAFF_IRM_MASK BIT_ULL(28) +#define GICV5_GIC_CDAFF_IRM(r) FIELD_GET(GICV5_GIC_CDAFF_IRM_MASK, r) +#define GICV5_GIC_CDAFF_ID_MASK GENMASK_ULL(23, 0) +#define GICV5_GIC_CDAFF_ID(r) FIELD_GET(GICV5_GIC_CDAFF_ID_MASK, r) + +/* Shift and mask definitions for GIC CDDI */ +#define GICV5_GIC_CDDI_TYPE_MASK GENMASK_ULL(31, 29) +#define GICV5_GIC_CDDI_TYPE(r) FIELD_GET(GICV5_GIC_CDDI_TYPE_MASK, r) +#define GICV5_GIC_CDDI_ID_MASK GENMASK_ULL(23, 0) +#define GICV5_GIC_CDDI_ID(r) FIELD_GET(GICV5_GIC_CDDI_ID_MASK, r) + +/* Shift and mask definitions for GIC CDDIS */ +#define GICV5_GIC_CDDIS_TYPE_MASK GENMASK_ULL(31, 29) +#define GICV5_GIC_CDDIS_TYPE(r) FIELD_GET(GICV5_GIC_CDDIS_TYPE_MASK, r) +#define GICV5_GIC_CDDIS_ID_MASK GENMASK_ULL(23, 0) +#define GICV5_GIC_CDDIS_ID(r) FIELD_GET(GICV5_GIC_CDDIS_ID_MASK, r) + +/* Shift and mask definitions for GIC CDEN */ +#define GICV5_GIC_CDEN_TYPE_MASK GENMASK_ULL(31, 29) +#define GICV5_GIC_CDEN_TYPE(r) FIELD_GET(GICV5_GIC_CDEN_TYPE_MASK, r) +#define GICV5_GIC_CDEN_ID_MASK GENMASK_ULL(23, 0) +#define GICV5_GIC_CDEN_ID(r) FIELD_GET(GICV5_GIC_CDEN_ID_MASK, r) + +/* Shift and mask definitions for GIC CDPEND */ +#define GICV5_GIC_CDPEND_PENDING_MASK BIT_ULL(32) +#define GICV5_GIC_CDPEND_PENDING(r) FIELD_GET(GICV5_GIC_CDPEND_PENDING_MAS= K, r) +#define GICV5_GIC_CDPEND_TYPE_MASK GENMASK_ULL(31, 29) +#define GICV5_GIC_CDPEND_TYPE(r) FIELD_GET(GICV5_GIC_CDPEND_TYPE_MASK, r) +#define GICV5_GIC_CDPEND_ID_MASK GENMASK_ULL(23, 0) +#define GICV5_GIC_CDPEND_ID(r) FIELD_GET(GICV5_GIC_CDPEND_ID_MASK, r) + +/* Shift and mask definitions for GIC CDPRI */ +#define GICV5_GIC_CDPRI_PRIORITY_MASK GENMASK_ULL(39, 35) +#define GICV5_GIC_CDPRI_PRIORITY(r) FIELD_GET(GICV5_GIC_CDPRI_PRIORITY_MAS= K, r) +#define GICV5_GIC_CDPRI_TYPE_MASK GENMASK_ULL(31, 29) +#define GICV5_GIC_CDPRI_TYPE(r) FIELD_GET(GICV5_GIC_CDPRI_TYPE_MASK, r) +#define GICV5_GIC_CDPRI_ID_MASK GENMASK_ULL(23, 0) +#define GICV5_GIC_CDPRI_ID(r) FIELD_GET(GICV5_GIC_CDPRI_ID_MASK, r) + +/* Shift and mask definitions for GIC CDRCFG */ +#define GICV5_GIC_CDRCFG_TYPE_MASK GENMASK_ULL(31, 29) +#define GICV5_GIC_CDRCFG_TYPE(r) FIELD_GET(GICV5_GIC_CDRCFG_TYPE_MASK, r) +#define GICV5_GIC_CDRCFG_ID_MASK GENMASK_ULL(23, 0) +#define GICV5_GIC_CDRCFG_ID(r) FIELD_GET(GICV5_GIC_CDRCFG_ID_MASK, r) + +/* Shift and mask definitions for GICR CDIA */ +#define GICV5_GIC_CDIA_VALID_MASK BIT_ULL(32) +#define GICV5_GIC_CDIA_VALID(r) FIELD_GET(GICV5_GIC_CDIA_VALID_MASK, r) +#define GICV5_GIC_CDIA_TYPE_MASK GENMASK_ULL(31, 29) +#define GICV5_GIC_CDIA_TYPE(r) FIELD_GET(GICV5_GIC_CDIA_TYPE_MASK, r) +#define GICV5_GIC_CDIA_ID_MASK GENMASK_ULL(23, 0) +#define GICV5_GIC_CDIA_ID(r) FIELD_GET(GICV5_GIC_CDIA_ID_MASK, r) + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARCH_GICV5_H */ diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h index d6fd6efb66a673ae33825971e4aa07e791c02ee5..d48ef6d5abcc77d1c06ad8e91e7= 2006acf662078 100644 --- a/arch/arm64/include/asm/smp.h +++ b/arch/arm64/include/asm/smp.h @@ -50,6 +50,23 @@ struct seq_file; */ extern void smp_init_cpus(void); =20 +enum ipi_msg_type { + IPI_RESCHEDULE, + IPI_CALL_FUNC, + IPI_CPU_STOP, + IPI_CPU_STOP_NMI, + IPI_TIMER, + IPI_IRQ_WORK, + NR_IPI, + /* + * Any enum >=3D NR_IPI and < MAX_IPI is special and not tracable + * with trace_ipi_* + */ + IPI_CPU_BACKTRACE =3D NR_IPI, + IPI_KGDB_ROUNDUP, + MAX_IPI +}; + /* * Register IPI interrupts with the arch SMP code */ diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 3f3712e47c94c62836fb89cd4bfb3595fbb41557..148145979d83f67469075df1c8b= 5e366ffe9d907 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -64,23 +64,6 @@ struct secondary_data secondary_data; /* Number of CPUs which aren't online, but looping in kernel text. */ static int cpus_stuck_in_kernel; =20 -enum ipi_msg_type { - IPI_RESCHEDULE, - IPI_CALL_FUNC, - IPI_CPU_STOP, - IPI_CPU_STOP_NMI, - IPI_TIMER, - IPI_IRQ_WORK, - NR_IPI, - /* - * Any enum >=3D NR_IPI and < MAX_IPI is special and not tracable - * with trace_ipi_* - */ - IPI_CPU_BACKTRACE =3D NR_IPI, - IPI_KGDB_ROUNDUP, - MAX_IPI -}; - static int ipi_irq_base __ro_after_init; static int nr_ipi __ro_after_init =3D NR_IPI; =20 diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index cec05e443083b8982b3e72f4212d808a22883914..160a4761d5d85f6dbf36f3142fd= 619c114733e36 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -54,6 +54,11 @@ config ARM_GIC_V3_ITS_FSL_MC depends on FSL_MC_BUS default ARM_GIC_V3_ITS =20 +config ARM_GIC_V5 + bool + select IRQ_DOMAIN_HIERARCHY + select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP + config ARM_NVIC bool select IRQ_DOMAIN_HIERARCHY diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 365bcea9a61ff89e2cb41034125b3fc8cd494d81..3d9c47fa3fdf40b7452c059d84f= e8ac24c91bc0f 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_ARM_GIC_V3) +=3D irq-gic-v3.o irq-gic-v3-mb= i.o irq-gic-common.o obj-$(CONFIG_ARM_GIC_V3_ITS) +=3D irq-gic-v3-its.o irq-gic-v4.o irq-gic-v= 3-its-msi-parent.o obj-$(CONFIG_ARM_GIC_V3_ITS_FSL_MC) +=3D irq-gic-v3-its-fsl-mc-msi.o obj-$(CONFIG_PARTITION_PERCPU) +=3D irq-partition-percpu.o +obj-$(CONFIG_ARM_GIC_V5) +=3D irq-gic-v5.o irq-gic-v5-irs.o obj-$(CONFIG_HISILICON_IRQ_MBIGEN) +=3D irq-mbigen.o obj-$(CONFIG_ARM_NVIC) +=3D irq-nvic.o obj-$(CONFIG_ARM_VIC) +=3D irq-vic.o diff --git a/drivers/irqchip/irq-gic-v5-irs.c b/drivers/irqchip/irq-gic-v5-= irs.c new file mode 100644 index 0000000000000000000000000000000000000000..7bd60e6d56b77c0c19a1bd9bee9= 685d9b6ffc959 --- /dev/null +++ b/drivers/irqchip/irq-gic-v5-irs.c @@ -0,0 +1,841 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024-2025 ARM Limited, All Rights Reserved. + */ + +#define pr_fmt(fmt) "GICv5 IRS: " fmt + +#include +#include +#include +#include +#include + +#include "irq-gic-v5.h" + +#define LPI_ID_BITS_LINEAR 12 + +#define IRS_FLAGS_NON_COHERENT BIT(0) + +static DEFINE_PER_CPU(struct gicv5_irs_chip_data *, per_cpu_irs_data); +static LIST_HEAD(irs_nodes); + +static u32 irs_readl_relaxed(struct gicv5_irs_chip_data *irs_data, + const u64 reg_offset) +{ + return readl_relaxed(irs_data->irs_base + reg_offset); +} + +static void irs_writel_relaxed(struct gicv5_irs_chip_data *irs_data, + const u32 val, const u64 reg_offset) +{ + writel_relaxed(val, irs_data->irs_base + reg_offset); +} + +static u64 irs_readq_relaxed(struct gicv5_irs_chip_data *irs_data, + const u64 reg_offset) +{ + return readq_relaxed(irs_data->irs_base + reg_offset); +} + +static void irs_writeq_relaxed(struct gicv5_irs_chip_data *irs_data, + const u64 val, const u64 reg_offset) +{ + writeq_relaxed(val, irs_data->irs_base + reg_offset); +} + +static int gicv5_wait_for_op(void __iomem *addr, u32 offset, u32 mask, u32= *val) +{ + void __iomem *reg =3D addr + offset; + u32 tmp; + int ret; + + ret =3D readl_poll_timeout_atomic(reg, tmp, tmp & mask, 1, 10 * USEC_PER_= MSEC); + + if (val) + *val =3D tmp; + + return ret; +} + +#define gicv5_irs_wait_for_op(base, reg, mask) \ + ({ \ + int ret; \ + \ + ret =3D gicv5_wait_for_op(base, reg, mask, NULL); \ + if (unlikely(ret =3D=3D -ETIMEDOUT)) \ + pr_err_ratelimited(#reg" timeout...\n"); \ + ret; \ + }) + +/* Wait for completion of an IST change */ +static int gicv5_irs_ist_wait_for_idle(struct gicv5_irs_chip_data *irs_dat= a) +{ + return gicv5_irs_wait_for_op(irs_data->irs_base, GICV5_IRS_IST_STATUSR, + GICV5_IRS_IST_STATUSR_IDLE); +} + +static int __init gicv5_irs_init_ist_linear(struct gicv5_irs_chip_data *ir= s_data, + unsigned int lpi_id_bits, + unsigned int istsz) +{ + size_t l2istsz; + u32 n, cfgr; + void *ist; + u64 baser; + int ret; + + /* Taken from GICv5 specifications 10.2.1.13 IRS_IST_BASER */ + n =3D max(5, lpi_id_bits + 1 + istsz); + + l2istsz =3D BIT(n + 1); + /* + * Check memory requirements. For a linear IST we cap the + * number of ID bits to a value that should never exceed + * kmalloc interface memory allocation limits, so this + * check is really belt and braces. + */ + if (l2istsz > KMALLOC_MAX_SIZE) { + u8 lpi_id_cap =3D ilog2(KMALLOC_MAX_SIZE) - 2 + istsz; + + pr_warn("Limiting LPI ID bits from %u to %u\n", + lpi_id_bits, lpi_id_cap); + lpi_id_bits =3D lpi_id_cap; + l2istsz =3D KMALLOC_MAX_SIZE; + } + + ist =3D kzalloc(l2istsz, GFP_KERNEL); + if (!ist) + return -ENOMEM; + + if (irs_data->flags & IRS_FLAGS_NON_COHERENT) + dcache_clean_inval_poc((unsigned long)ist, + (unsigned long)ist + l2istsz); + else + dsb(ishst); + + cfgr =3D FIELD_PREP(GICV5_IRS_IST_CFGR_STRUCTURE, + GICV5_IRS_IST_CFGR_STRUCTURE_LINEAR) | + FIELD_PREP(GICV5_IRS_IST_CFGR_ISTSZ, istsz) | + FIELD_PREP(GICV5_IRS_IST_CFGR_L2SZ, + GICV5_IRS_IST_CFGR_L2SZ_4K) | + FIELD_PREP(GICV5_IRS_IST_CFGR_LPI_ID_BITS, lpi_id_bits); + irs_writel_relaxed(irs_data, cfgr, GICV5_IRS_IST_CFGR); + + gicv5_global_data.ist.l2 =3D false; + + baser =3D (virt_to_phys(ist) & GICV5_IRS_IST_BASER_ADDR_MASK) | + FIELD_PREP(GICV5_IRS_IST_BASER_VALID, 0x1); + irs_writeq_relaxed(irs_data, baser, GICV5_IRS_IST_BASER); + + /* + * The polling wait (in gicv5_wait_for_op()) on a GIC register + * provides the memory barriers (through MMIO accessors) + * required to synchronize CPU and GIC access to IST memory. + */ + ret =3D gicv5_irs_ist_wait_for_idle(irs_data); + if (ret) { + kfree(ist); + return ret; + } + + return 0; +} + +static int __init gicv5_irs_init_ist_two_level(struct gicv5_irs_chip_data = *irs_data, + unsigned int lpi_id_bits, + unsigned int istsz, + unsigned int l2sz) +{ + __le64 *l1ist; + u32 cfgr, n; + size_t l1sz; + u64 baser; + int ret; + + /* Taken from GICv5 specifications 10.2.1.13 IRS_IST_BASER */ + n =3D max(5, lpi_id_bits - ((10 - istsz) + (2 * l2sz)) + 2); + + l1sz =3D BIT(n + 1); + + l1ist =3D kzalloc(l1sz, GFP_KERNEL); + if (!l1ist) + return -ENOMEM; + + if (irs_data->flags & IRS_FLAGS_NON_COHERENT) + dcache_clean_inval_poc((unsigned long)l1ist, + (unsigned long)l1ist + l1sz); + else + dsb(ishst); + + cfgr =3D FIELD_PREP(GICV5_IRS_IST_CFGR_STRUCTURE, + GICV5_IRS_IST_CFGR_STRUCTURE_TWO_LEVEL) | + FIELD_PREP(GICV5_IRS_IST_CFGR_ISTSZ, istsz) | + FIELD_PREP(GICV5_IRS_IST_CFGR_L2SZ, l2sz) | + FIELD_PREP(GICV5_IRS_IST_CFGR_LPI_ID_BITS, lpi_id_bits); + irs_writel_relaxed(irs_data, cfgr, GICV5_IRS_IST_CFGR); + + /* + * The L2SZ determine bits required at L2 level. Number of bytes + * required by metadata is reported through istsz - the number of bits + * covered by L2 entries scales accordingly. + */ + gicv5_global_data.ist.l2_size =3D BIT(11 + (2 * l2sz) + 1); + gicv5_global_data.ist.l2_bits =3D (10 - istsz) + (2 * l2sz); + gicv5_global_data.ist.l1ist_addr =3D l1ist; + gicv5_global_data.ist.l2 =3D true; + + baser =3D (virt_to_phys(l1ist) & GICV5_IRS_IST_BASER_ADDR_MASK) | + FIELD_PREP(GICV5_IRS_IST_BASER_VALID, 0x1); + irs_writeq_relaxed(irs_data, baser, GICV5_IRS_IST_BASER); + + /* + * The polling wait (in gicv5_wait_for_op()) on a GIC register + * provides the memory barriers (through MMIO accessors) + * required to synchronize CPU and GIC access to IST memory. + */ + ret =3D gicv5_irs_ist_wait_for_idle(irs_data); + if (ret) { + kfree(l1ist); + return ret; + } + + return 0; +} + +/* + * Alloc L2 IST entries on demand. + * + * Locking/serialization is guaranteed by irqdomain core code by + * taking the hierarchical domain struct irq_domain.root->mutex. + */ +int gicv5_irs_iste_alloc(const u32 lpi) +{ + struct gicv5_irs_chip_data *irs_data; + unsigned int index; + u32 l2istr, l2bits; + __le64 *l1ist; + size_t l2size; + void *l2ist; + int ret; + + if (!gicv5_global_data.ist.l2) + return 0; + + irs_data =3D per_cpu(per_cpu_irs_data, smp_processor_id()); + if (!irs_data) + return -ENOENT; + + l2size =3D gicv5_global_data.ist.l2_size; + l2bits =3D gicv5_global_data.ist.l2_bits; + + l1ist =3D gicv5_global_data.ist.l1ist_addr; + + index =3D lpi >> l2bits; + + if (FIELD_GET(GICV5_ISTL1E_VALID, le64_to_cpu(l1ist[index]))) + return 0; + + l2ist =3D kzalloc(l2size, GFP_KERNEL); + if (!l2ist) + return -ENOMEM; + + l1ist[index] =3D cpu_to_le64(virt_to_phys(l2ist) & GICV5_ISTL1E_L2_ADDR_M= ASK); + + if (irs_data->flags & IRS_FLAGS_NON_COHERENT) { + dcache_clean_inval_poc((unsigned long)l2ist, + (unsigned long)l2ist + l2size); + dcache_clean_poc((unsigned long)(l1ist + index), + (unsigned long)(l1ist + index) + sizeof(*l1ist)); + } else { + dsb(ishst); + } + + l2istr =3D FIELD_PREP(GICV5_IRS_MAP_L2_ISTR_ID, lpi); + irs_writel_relaxed(irs_data, l2istr, GICV5_IRS_MAP_L2_ISTR); + + /* + * The polling wait (in gicv5_wait_for_op()) on a GIC register + * provides the memory barriers (through MMIO accessors) + * required to synchronize CPU and GIC access to IST memory. + */ + ret =3D gicv5_irs_ist_wait_for_idle(irs_data); + if (ret) { + l1ist[index] =3D 0; + kfree(l2ist); + return ret; + } + + /* + * Make sure we invalidate the cache line pulled before the IRS + * had a chance to update the L1 entry and mark it valid. + */ + if (irs_data->flags & IRS_FLAGS_NON_COHERENT) { + /* + * gicv5_irs_ist_wait_for_idle() includes memory + * barriers (MMIO accessors) required to guarantee that the + * following dcache invalidation is not executed before the + * IST mapping operation has completed. + */ + dcache_inval_poc((unsigned long)(l1ist + index), + (unsigned long)(l1ist + index) + sizeof(*l1ist)); + } + + return 0; +} + +/* + * Try to match the L2 IST size to the pagesize, and if this is not possib= le + * pick the smallest supported L2 size in order to minimise the requiremen= t for + * physically contiguous blocks of memory as page-sized allocations are + * guaranteed to be physically contiguous, and are by definition the easie= st to + * find. + * + * Fall back to the smallest supported size (in the event that the pagesize + * itself is not supported) again serves to make it easier to find physica= lly + * contiguous blocks of memory. + */ +static int gicv5_irs_l2_sz(u32 idr2) +{ + switch (PAGE_SIZE) { + case SZ_64K: + if (GICV5_IRS_IST_L2SZ_SUPPORT_64KB(idr2)) + return GICV5_IRS_IST_CFGR_L2SZ_64K; + fallthrough; + case SZ_16K: + if (GICV5_IRS_IST_L2SZ_SUPPORT_16KB(idr2)) + return GICV5_IRS_IST_CFGR_L2SZ_16K; + fallthrough; + case SZ_4K: + if (GICV5_IRS_IST_L2SZ_SUPPORT_4KB(idr2)) + return GICV5_IRS_IST_CFGR_L2SZ_4K; + if (GICV5_IRS_IST_L2SZ_SUPPORT_16KB(idr2)) + return GICV5_IRS_IST_CFGR_L2SZ_16K; + if (GICV5_IRS_IST_L2SZ_SUPPORT_64KB(idr2)) + return GICV5_IRS_IST_CFGR_L2SZ_64K; + break; + } + + return -ENODEV; +} + +static int __init gicv5_irs_init_ist(struct gicv5_irs_chip_data *irs_data) +{ + u32 lpi_id_bits, idr2_id_bits, idr2_min_lpi_id_bits, + l2_iste_sz, l2sz, l2_iste_sz_split, idr2; + bool two_levels, istmd; + u64 baser; + int ret; + + baser =3D irs_readq_relaxed(irs_data, GICV5_IRS_IST_BASER); + if (FIELD_GET(GICV5_IRS_IST_BASER_VALID, baser)) { + pr_err("IST is marked as valid already; cannot allocate\n"); + return -EPERM; + } + + idr2 =3D irs_readl_relaxed(irs_data, GICV5_IRS_IDR2); + + two_levels =3D !!FIELD_GET(GICV5_IRS_IDR2_IST_LEVELS, idr2); + + idr2_id_bits =3D FIELD_GET(GICV5_IRS_IDR2_ID_BITS, idr2); + idr2_min_lpi_id_bits =3D FIELD_GET(GICV5_IRS_IDR2_MIN_LPI_ID_BITS, idr2); + + /* + * For two level tables we are always allocating the maximum allowed + * number of IDs. + * + * For 1-level tables, we should allocate a number of bits that + * is >=3D min_lpi_id_bits but cap it to LPI_ID_BITS_LINEAR lest + * the level 1-table gets too large and its memory allocation + * may fail. + */ + if (two_levels) { + lpi_id_bits =3D idr2_id_bits; + } else { + lpi_id_bits =3D max(LPI_ID_BITS_LINEAR, idr2_min_lpi_id_bits); + lpi_id_bits =3D min(lpi_id_bits, idr2_id_bits); + } + + /* + * Cap the ID bits according to the CPUIF supported ID bits + */ + lpi_id_bits =3D min(lpi_id_bits, gicv5_global_data.cpuif_id_bits); + + if (two_levels) { + l2sz =3D gicv5_irs_l2_sz(idr2); + if (l2sz < 0) + return l2sz; + } + + istmd =3D !!FIELD_GET(GICV5_IRS_IDR2_ISTMD, idr2); + + l2_iste_sz =3D GICV5_IRS_IST_CFGR_ISTSZ_4; + + // Only supported if IRS_IDR2.ISTMD is 1 + if (istmd) { + l2_iste_sz_split =3D FIELD_GET(GICV5_IRS_IDR2_ISTMD_SZ, idr2); + + if (lpi_id_bits < l2_iste_sz_split) + l2_iste_sz =3D GICV5_IRS_IST_CFGR_ISTSZ_8; + else + l2_iste_sz =3D GICV5_IRS_IST_CFGR_ISTSZ_16; + } + + /* + * Follow GICv5 specification recommendation to opt in for two + * level tables + */ + two_levels =3D two_levels && (lpi_id_bits > ((10 - l2_iste_sz) + (2 * l2s= z))); + + if (two_levels) + ret =3D gicv5_irs_init_ist_two_level(irs_data, lpi_id_bits, + l2_iste_sz, l2sz); + else + ret =3D gicv5_irs_init_ist_linear(irs_data, lpi_id_bits, + l2_iste_sz); + if (ret) + return ret; + + gicv5_init_lpis(BIT(lpi_id_bits)); + + return 0; +} + +struct iaffid_entry { + u16 iaffid; + bool valid; +}; + +static DEFINE_PER_CPU(struct iaffid_entry, cpu_iaffid); + +int gicv5_irs_cpu_to_iaffid(int cpuid, u16 *iaffid) +{ + if (!per_cpu(cpu_iaffid, cpuid).valid) { + pr_err("IAFFID for CPU %d has not been initialised\n", cpuid); + return -ENODEV; + } + + *iaffid =3D per_cpu(cpu_iaffid, cpuid).iaffid; + + return 0; +} + +struct gicv5_irs_chip_data *gicv5_irs_lookup_by_spi_id(u32 spi_id) +{ + struct gicv5_irs_chip_data *irs_data; + u32 min, max; + + list_for_each_entry(irs_data, &irs_nodes, entry) { + if (!irs_data->spi_range) + continue; + + min =3D irs_data->spi_min; + max =3D irs_data->spi_min + irs_data->spi_range - 1; + if (spi_id >=3D min && spi_id <=3D max) + return irs_data; + } + + return NULL; +} + +static int gicv5_irs_wait_for_spi_op(struct gicv5_irs_chip_data *irs_data) +{ + u32 statusr; + int ret; + + ret =3D gicv5_wait_for_op(irs_data->irs_base, GICV5_IRS_SPI_STATUSR, + GICV5_IRS_SPI_STATUSR_IDLE, &statusr); + if (unlikely(ret =3D=3D -ETIMEDOUT)) { + pr_err_ratelimited("IRS_SPI_STATUSR timeout\n"); + return ret; + } + + return !!FIELD_GET(GICV5_IRS_SPI_STATUSR_V, statusr) ? 0 : -ENXIO; +} + +static int gicv5_irs_wait_for_irs_pe(struct gicv5_irs_chip_data *irs_data, + bool selr) +{ + u32 statusr; + bool valid; + int ret; + + ret =3D gicv5_wait_for_op(irs_data->irs_base, GICV5_IRS_PE_STATUSR, + GICV5_IRS_PE_STATUSR_IDLE, &statusr); + + if (unlikely(ret =3D=3D -ETIMEDOUT)) { + pr_err_ratelimited("IRS_PE_STATUSR timeout after %s\n", + selr ? "IRS_PE_SELR" : "IRS_PE_CR0"); + return ret; + } + + if (selr) { + valid =3D !!FIELD_GET(GICV5_IRS_PE_STATUSR_V, statusr); + return valid ? 0 : -ENXIO; + } + + return 0; +} + +static int gicv5_irs_wait_for_pe_selr(struct gicv5_irs_chip_data *irs_data) +{ + return gicv5_irs_wait_for_irs_pe(irs_data, true); +} + +static int gicv5_irs_wait_for_pe_cr0(struct gicv5_irs_chip_data *irs_data) +{ + return gicv5_irs_wait_for_irs_pe(irs_data, false); +} + +int gicv5_spi_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct gicv5_irs_chip_data *irs_data =3D d->chip_data; + u32 selr, cfgr; + bool level; + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + case IRQ_TYPE_EDGE_FALLING: + level =3D false; + break; + case IRQ_TYPE_LEVEL_HIGH: + case IRQ_TYPE_LEVEL_LOW: + level =3D true; + break; + default: + return -EINVAL; + } + + guard(raw_spinlock)(&irs_data->spi_config_lock); + + selr =3D FIELD_PREP(GICV5_IRS_SPI_SELR_ID, d->hwirq); + irs_writel_relaxed(irs_data, selr, GICV5_IRS_SPI_SELR); + if (gicv5_irs_wait_for_spi_op(irs_data)) + return -EIO; + + cfgr =3D FIELD_PREP(GICV5_IRS_SPI_CFGR_TM, level); + + irs_writel_relaxed(irs_data, cfgr, GICV5_IRS_SPI_CFGR); + if (gicv5_irs_wait_for_spi_op(irs_data)) + return -EPERM; + + return 0; +} + +static int gicv5_irs_wait_for_idle(struct gicv5_irs_chip_data *irs_data) +{ + return gicv5_irs_wait_for_op(irs_data->irs_base, GICV5_IRS_CR0, + GICV5_IRS_CR0_IDLE); +} + +int gicv5_irs_register_cpu(int cpuid) +{ + struct gicv5_irs_chip_data *irs_data; + u32 selr, cr0; + u16 iaffid; + int ret; + + ret =3D gicv5_irs_cpu_to_iaffid(cpuid, &iaffid); + if (ret) { + pr_err("IAFFID for CPU %d has not been initialised\n", cpuid); + return ret; + } + + irs_data =3D per_cpu(per_cpu_irs_data, cpuid); + if (!irs_data) { + pr_err("No IRS associated with CPU %u\n", cpuid); + return -ENXIO; + } + + selr =3D FIELD_PREP(GICV5_IRS_PE_SELR_IAFFID, iaffid); + irs_writel_relaxed(irs_data, selr, GICV5_IRS_PE_SELR); + + ret =3D gicv5_irs_wait_for_pe_selr(irs_data); + if (ret) { + pr_err("IAFFID 0x%x used in IRS_PE_SELR is invalid\n", iaffid); + return -ENXIO; + } + + cr0 =3D FIELD_PREP(GICV5_IRS_PE_CR0_DPS, 0x1); + irs_writel_relaxed(irs_data, cr0, GICV5_IRS_PE_CR0); + + ret =3D gicv5_irs_wait_for_pe_cr0(irs_data); + if (ret) + return ret; + + pr_debug("CPU%d enabled PE IAFFID 0x%x\n", cpuid, iaffid); + + return 0; +} + +static int __init gicv5_irs_init_bases(struct gicv5_irs_chip_data *irs_dat= a, + void __iomem *irs_base, + struct fwnode_handle *handle) +{ + struct device_node *np =3D to_of_node(handle); + u32 cr0, cr1; + + irs_data->fwnode =3D handle; + irs_data->irs_base =3D irs_base; + + if (of_property_read_bool(np, "dma-noncoherent")) { + /* + * A non-coherent IRS implies that some cache levels cannot be + * used coherently by the cores and GIC. Our only option is to mark + * memory attributes for the GIC as non-cacheable; by default, + * non-cacheable memory attributes imply outer-shareable + * shareability, the value written into IRS_CR1_SH is ignored. + */ + cr1 =3D FIELD_PREP(GICV5_IRS_CR1_VPED_WA, GICV5_NO_WRITE_ALLOC) | + FIELD_PREP(GICV5_IRS_CR1_VPED_RA, GICV5_NO_READ_ALLOC) | + FIELD_PREP(GICV5_IRS_CR1_VMD_WA, GICV5_NO_WRITE_ALLOC) | + FIELD_PREP(GICV5_IRS_CR1_VMD_RA, GICV5_NO_READ_ALLOC) | + FIELD_PREP(GICV5_IRS_CR1_VPET_RA, GICV5_NO_READ_ALLOC) | + FIELD_PREP(GICV5_IRS_CR1_VMT_RA, GICV5_NO_READ_ALLOC) | + FIELD_PREP(GICV5_IRS_CR1_IST_WA, GICV5_NO_WRITE_ALLOC) | + FIELD_PREP(GICV5_IRS_CR1_IST_RA, GICV5_NO_READ_ALLOC) | + FIELD_PREP(GICV5_IRS_CR1_IC, GICV5_NON_CACHE) | + FIELD_PREP(GICV5_IRS_CR1_OC, GICV5_NON_CACHE); + irs_data->flags |=3D IRS_FLAGS_NON_COHERENT; + } else { + cr1 =3D FIELD_PREP(GICV5_IRS_CR1_VPED_WA, GICV5_WRITE_ALLOC) | + FIELD_PREP(GICV5_IRS_CR1_VPED_RA, GICV5_READ_ALLOC) | + FIELD_PREP(GICV5_IRS_CR1_VMD_WA, GICV5_WRITE_ALLOC) | + FIELD_PREP(GICV5_IRS_CR1_VMD_RA, GICV5_READ_ALLOC) | + FIELD_PREP(GICV5_IRS_CR1_VPET_RA, GICV5_READ_ALLOC) | + FIELD_PREP(GICV5_IRS_CR1_VMT_RA, GICV5_READ_ALLOC) | + FIELD_PREP(GICV5_IRS_CR1_IST_WA, GICV5_WRITE_ALLOC) | + FIELD_PREP(GICV5_IRS_CR1_IST_RA, GICV5_READ_ALLOC) | + FIELD_PREP(GICV5_IRS_CR1_IC, GICV5_WB_CACHE) | + FIELD_PREP(GICV5_IRS_CR1_OC, GICV5_WB_CACHE) | + FIELD_PREP(GICV5_IRS_CR1_SH, GICV5_INNER_SHARE); + } + + irs_writel_relaxed(irs_data, cr1, GICV5_IRS_CR1); + + cr0 =3D FIELD_PREP(GICV5_IRS_CR0_IRSEN, 0x1); + irs_writel_relaxed(irs_data, cr0, GICV5_IRS_CR0); + gicv5_irs_wait_for_idle(irs_data); + + return 0; +} + +static int __init gicv5_irs_of_init_affinity(struct device_node *node, + struct gicv5_irs_chip_data *irs_data, + u8 iaffid_bits) +{ + /* + * Detect IAFFID<->CPU mappings from the device tree and + * record IRS<->CPU topology information. + */ + u16 iaffid_mask =3D GENMASK(iaffid_bits - 1, 0); + u16 *iaffids __free(kfree) =3D NULL; + int ret, i, ncpus, niaffids; + + ncpus =3D of_property_count_elems_of_size(node, "cpus", sizeof(u32)); + if (ncpus < 0) + return -EINVAL; + + niaffids =3D of_property_count_elems_of_size(node, "arm,iaffids", + sizeof(u16)); + if (niaffids !=3D ncpus) + return -EINVAL; + + iaffids =3D kcalloc(niaffids, sizeof(*iaffids), GFP_KERNEL); + if (!iaffids) + return -ENOMEM; + + ret =3D of_property_read_u16_array(node, "arm,iaffids", iaffids, niaffids= ); + if (ret) + return ret; + + for (i =3D 0; i < ncpus; i++) { + struct device_node *cpu_node; + u32 cpu_phandle; + int cpu; + + if (of_property_read_u32_index(node, "cpus", i, &cpu_phandle)) + continue; + + cpu_node =3D of_find_node_by_phandle(cpu_phandle); + if (WARN_ON(!cpu_node)) + continue; + + cpu =3D of_cpu_node_to_id(cpu_node); + of_node_put(cpu_node); + if (WARN_ON(cpu < 0)) + continue; + + if (iaffids[i] & ~iaffid_mask) { + pr_warn("CPU %d iaffid 0x%x exceeds IRS iaffid bits\n", + cpu, iaffids[i]); + continue; + } + + per_cpu(cpu_iaffid, cpu).iaffid =3D iaffids[i]; + per_cpu(cpu_iaffid, cpu).valid =3D true; + + // We also know that the CPU is connected to this IRS + per_cpu(per_cpu_irs_data, cpu) =3D irs_data; + } + + return ret; +} + +static void irs_setup_pri_bits(u32 idr1) +{ + switch (FIELD_GET(GICV5_IRS_IDR1_PRIORITY_BITS, idr1)) { + case GICV5_IRS_IDR1_PRIORITY_BITS_1BITS: + gicv5_global_data.irs_pri_bits =3D 1; + break; + case GICV5_IRS_IDR1_PRIORITY_BITS_2BITS: + gicv5_global_data.irs_pri_bits =3D 2; + break; + case GICV5_IRS_IDR1_PRIORITY_BITS_3BITS: + gicv5_global_data.irs_pri_bits =3D 3; + break; + case GICV5_IRS_IDR1_PRIORITY_BITS_4BITS: + gicv5_global_data.irs_pri_bits =3D 4; + break; + case GICV5_IRS_IDR1_PRIORITY_BITS_5BITS: + gicv5_global_data.irs_pri_bits =3D 5; + break; + default: + pr_warn("Detected wrong IDR priority bits value 0x%lx\n", + FIELD_GET(GICV5_IRS_IDR1_PRIORITY_BITS, idr1)); + break; + } +} + +static int __init gicv5_irs_init(struct device_node *node) +{ + struct gicv5_irs_chip_data *irs_data; + void __iomem *irs_base; + u8 iaffid_bits; + int ret; + u32 idr; + + irs_data =3D kzalloc(sizeof(*irs_data), GFP_KERNEL); + if (!irs_data) + return -ENOMEM; + + raw_spin_lock_init(&irs_data->spi_config_lock); + + irs_base =3D of_io_request_and_map(node, 0, "IRS"); + if (IS_ERR(irs_base)) { + pr_err("%pOF: unable to map GICv5 IRS registers\n", node); + ret =3D PTR_ERR(irs_base); + goto out_err; + } + + gicv5_irs_init_bases(irs_data, irs_base, &node->fwnode); + + idr =3D irs_readl_relaxed(irs_data, GICV5_IRS_IDR1); + iaffid_bits =3D FIELD_GET(GICV5_IRS_IDR1_IAFFID_BITS, idr) + 1; + + ret =3D gicv5_irs_of_init_affinity(node, irs_data, iaffid_bits); + if (ret) { + pr_err("Failed to parse CPU IAFFIDs from the device tree!\n"); + goto out_iomem; + } + + idr =3D irs_readl_relaxed(irs_data, GICV5_IRS_IDR2); + if (WARN(!FIELD_GET(GICV5_IRS_IDR2_LPI, idr), + "LPI support not available - no IPIs, can't proceed\n")) { + ret =3D -ENODEV; + goto out_iomem; + } + + idr =3D irs_readl_relaxed(irs_data, GICV5_IRS_IDR7); + irs_data->spi_min =3D FIELD_GET(GICV5_IRS_IDR7_SPI_BASE, idr); + + idr =3D irs_readl_relaxed(irs_data, GICV5_IRS_IDR6); + irs_data->spi_range =3D FIELD_GET(GICV5_IRS_IDR6_SPI_IRS_RANGE, idr); + + if (irs_data->spi_range) { + pr_info("%s detected SPI range [%u-%u]\n", + of_node_full_name(node), + irs_data->spi_min, + irs_data->spi_min + + irs_data->spi_range - 1); + } + + /* + * Do the global setting only on the first IRS. + * Global properties (iaffid_bits, global spi count) are guaranteed to + * be consistent across IRSes by the architecture. + */ + if (list_empty(&irs_nodes)) { + + idr =3D irs_readl_relaxed(irs_data, GICV5_IRS_IDR1); + irs_setup_pri_bits(idr); + + idr =3D irs_readl_relaxed(irs_data, GICV5_IRS_IDR5); + gicv5_global_data.global_spi_count =3D + FIELD_GET(GICV5_IRS_IDR5_SPI_RANGE, idr); + + gicv5_init_lpi_domain(); + + pr_debug("Detected %u SPIs globally\n", + gicv5_global_data.global_spi_count); + } + + list_add_tail(&irs_data->entry, &irs_nodes); + + return 0; +out_iomem: + iounmap(irs_base); +out_err: + kfree(irs_data); + return ret; +} + +void __init gicv5_irs_remove(void) +{ + struct gicv5_irs_chip_data *irs_data, *tmp_data; + + gicv5_free_lpi_domain(); + gicv5_deinit_lpis(); + + list_for_each_entry_safe(irs_data, tmp_data, &irs_nodes, entry) { + iounmap(irs_data->irs_base); + list_del(&irs_data->entry); + kfree(irs_data); + } +} + +int __init gicv5_irs_enable(void) +{ + struct gicv5_irs_chip_data *irs_data; + int ret; + + irs_data =3D list_first_entry_or_null(&irs_nodes, + struct gicv5_irs_chip_data, entry); + if (!irs_data) + return -ENODEV; + + ret =3D gicv5_irs_init_ist(irs_data); + if (ret) { + pr_err("Failed to init IST\n"); + return ret; + } + + return 0; +} + +int __init gicv5_irs_of_probe(struct device_node *parent) +{ + struct device_node *np; + int ret; + + for_each_available_child_of_node(parent, np) { + if (!of_device_is_compatible(np, "arm,gic-v5-irs")) + continue; + + ret =3D gicv5_irs_init(np); + if (ret) + pr_err("Failed to init IRS %s\n", np->full_name); + } + + return list_empty(&irs_nodes) ? -ENODEV : 0; +} diff --git a/drivers/irqchip/irq-gic-v5.c b/drivers/irqchip/irq-gic-v5.c new file mode 100644 index 0000000000000000000000000000000000000000..c4d4e85382f672fa4ae334db1a4= e4c7c4f46b9fe --- /dev/null +++ b/drivers/irqchip/irq-gic-v5.c @@ -0,0 +1,1058 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024-2025 ARM Limited, All Rights Reserved. + */ + +#define pr_fmt(fmt) "GICv5: " fmt + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "irq-gic-v5.h" + +static u8 pri_bits =3D 5; +#define GICV5_IRQ_PRI_MASK 0x1f +#define GICV5_IRQ_PRI_MI \ + (GICV5_IRQ_PRI_MASK & GENMASK(4, 5 - pri_bits)) + +static bool gicv5_cpuif_has_gcie(void) +{ + return this_cpu_has_cap(ARM64_HAS_GICV5_CPUIF); +} + +struct gicv5_chip_data gicv5_global_data __read_mostly; + +static DEFINE_IDA(lpi_ida); +static u32 num_lpis; + +void __init gicv5_init_lpis(u32 lpis) +{ + num_lpis =3D lpis; +} + +void __init gicv5_deinit_lpis(void) +{ + num_lpis =3D 0; +} + +static int alloc_lpi(void) +{ + if (!num_lpis) + return -ENOSPC; + + return ida_alloc_max(&lpi_ida, num_lpis - 1, GFP_KERNEL); +} + +static void release_lpi(u32 lpi) +{ + ida_free(&lpi_ida, lpi); +} + +static int gicv5_alloc_lpi(void) +{ + return alloc_lpi(); +} + +static void gicv5_free_lpi(u32 lpi) +{ + release_lpi(lpi); +} + +static void gicv5_ppi_priority_init(void) +{ + write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR0_EL1); + write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR1_EL1); + write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR2_EL1); + write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR3_EL1); + write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR4_EL1); + write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR5_EL1); + write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR6_EL1); + write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR7_EL1); + write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR8_EL1); + write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR9_EL1); + write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR10_EL1= ); + write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR11_EL1= ); + write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR12_EL1= ); + write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR13_EL1= ); + write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR14_EL1= ); + write_sysreg_s(REPEAT_BYTE(GICV5_IRQ_PRI_MI), SYS_ICC_PPI_PRIORITYR15_EL1= ); + + /* + * Context syncronization required to mare system + * register writes effects are synchronized + */ + isb(); +} + +static void gicv5_hwirq_init(irq_hw_number_t hwirq, u8 priority, u8 hwirq_= type) +{ + u64 cdpri, cdaff; + u16 iaffid; + int ret; + + if (hwirq_type =3D=3D GICV5_HWIRQ_TYPE_LPI || hwirq_type =3D=3D GICV5_HWI= RQ_TYPE_SPI) { + cdpri =3D FIELD_PREP(GICV5_GIC_CDPRI_PRIORITY_MASK, priority) | + FIELD_PREP(GICV5_GIC_CDPRI_TYPE_MASK, hwirq_type) | + FIELD_PREP(GICV5_GIC_CDPRI_ID_MASK, hwirq); + gic_insn(cdpri, GICV5_OP_GIC_CDPRI); + + ret =3D gicv5_irs_cpu_to_iaffid(smp_processor_id(), &iaffid); + + if (WARN_ON_ONCE(ret)) + return; + + cdaff =3D FIELD_PREP(GICV5_GIC_CDAFF_IAFFID_MASK, iaffid) | + FIELD_PREP(GICV5_GIC_CDAFF_TYPE_MASK, hwirq_type) | + FIELD_PREP(GICV5_GIC_CDAFF_ID_MASK, hwirq); + gic_insn(cdaff, GICV5_OP_GIC_CDAFF); + } +} + +static void gicv5_ppi_irq_mask(struct irq_data *d) +{ + u64 hwirq_id_bit =3D BIT_ULL(d->hwirq % 64); + + if (d->hwirq < 64) + sysreg_clear_set_s(SYS_ICC_PPI_ENABLER0_EL1, hwirq_id_bit, 0); + else + sysreg_clear_set_s(SYS_ICC_PPI_ENABLER1_EL1, hwirq_id_bit, 0); + + /* + * Ensure that the disable takes effect + */ + isb(); +} + +static void gicv5_iri_irq_mask(struct irq_data *d, u8 hwirq_type) +{ + u64 cddis =3D d->hwirq | FIELD_PREP(GICV5_GIC_CDDIS_TYPE_MASK, hwirq_type= ); + + gic_insn(cddis, GICV5_OP_GIC_CDDIS); + /* + * We must make sure that GIC CDDIS write effects are propagated + */ + gsb_sys(); +} + +static void gicv5_spi_irq_mask(struct irq_data *d) +{ + gicv5_iri_irq_mask(d, GICV5_HWIRQ_TYPE_SPI); +} + +static void gicv5_lpi_irq_mask(struct irq_data *d) +{ + gicv5_iri_irq_mask(d, GICV5_HWIRQ_TYPE_LPI); +} + +static void gicv5_ppi_irq_unmask(struct irq_data *d) +{ + u64 hwirq_id_bit =3D BIT_ULL(d->hwirq % 64); + + if (d->hwirq < 64) + sysreg_clear_set_s(SYS_ICC_PPI_ENABLER0_EL1, 0, hwirq_id_bit); + else + sysreg_clear_set_s(SYS_ICC_PPI_ENABLER1_EL1, 0, hwirq_id_bit); +} + +static void gicv5_iri_irq_unmask(struct irq_data *d, u8 hwirq_type) +{ + u64 cden =3D d->hwirq | FIELD_PREP(GICV5_GIC_CDEN_TYPE_MASK, hwirq_type); + + gic_insn(cden, GICV5_OP_GIC_CDEN); +} + +static void gicv5_spi_irq_unmask(struct irq_data *d) +{ + gicv5_iri_irq_unmask(d, GICV5_HWIRQ_TYPE_SPI); +} + +static void gicv5_lpi_irq_unmask(struct irq_data *d) +{ + gicv5_iri_irq_unmask(d, GICV5_HWIRQ_TYPE_LPI); +} + +static void gicv5_hwirq_eoi(u32 hwirq_id, u8 hwirq_type) +{ + u64 cddi =3D hwirq_id | FIELD_PREP(GICV5_GIC_CDDI_TYPE_MASK, hwirq_type); + + gic_insn(cddi, GICV5_OP_GIC_CDDI); + + gic_insn(0, GICV5_OP_GIC_CDEOI); +} + +static void gicv5_ppi_irq_eoi(struct irq_data *d) +{ + gicv5_hwirq_eoi(d->hwirq, GICV5_HWIRQ_TYPE_PPI); +} + +static void gicv5_spi_irq_eoi(struct irq_data *d) +{ + gicv5_hwirq_eoi(d->hwirq, GICV5_HWIRQ_TYPE_SPI); +} + +static void gicv5_lpi_irq_eoi(struct irq_data *d) +{ + gicv5_hwirq_eoi(d->hwirq, GICV5_HWIRQ_TYPE_LPI); +} + +static int gicv5_iri_irq_set_affinity(struct irq_data *d, + const struct cpumask *mask_val, + bool force, u8 hwirq_type) +{ + int ret, cpuid; + u16 iaffid; + u64 cdaff; + + if (force) + cpuid =3D cpumask_first(mask_val); + else + cpuid =3D cpumask_any_and(mask_val, cpu_online_mask); + + ret =3D gicv5_irs_cpu_to_iaffid(cpuid, &iaffid); + if (ret) + return ret; + + cdaff =3D FIELD_PREP(GICV5_GIC_CDAFF_IAFFID_MASK, iaffid) | + FIELD_PREP(GICV5_GIC_CDAFF_TYPE_MASK, hwirq_type) | + FIELD_PREP(GICV5_GIC_CDAFF_ID_MASK, d->hwirq); + gic_insn(cdaff, GICV5_OP_GIC_CDAFF); + + irq_data_update_effective_affinity(d, cpumask_of(cpuid)); + + return IRQ_SET_MASK_OK_DONE; +} + +static int gicv5_spi_irq_set_affinity(struct irq_data *d, + const struct cpumask *mask_val, + bool force) +{ + return gicv5_iri_irq_set_affinity(d, mask_val, force, + GICV5_HWIRQ_TYPE_SPI); +} + +static int gicv5_lpi_irq_set_affinity(struct irq_data *d, + const struct cpumask *mask_val, + bool force) +{ + return gicv5_iri_irq_set_affinity(d, mask_val, force, + GICV5_HWIRQ_TYPE_LPI); +} + +#define READ_PPI_REG(irq, reg) \ + ({ \ + u64 val; \ + \ + if (irq < 64) \ + val =3D read_sysreg_s(SYS_ICC_PPI_##reg##R0_EL1); \ + else \ + val =3D read_sysreg_s(SYS_ICC_PPI_##reg##R1_EL1); \ + val; \ + }) + +#define WRITE_PPI_REG(set, irq, bit, reg) \ + do { \ + if (set) { \ + if (irq < 64) \ + write_sysreg_s(bit, SYS_ICC_PPI_S##reg##R0_EL1);\ + else \ + write_sysreg_s(bit, SYS_ICC_PPI_S##reg##R1_EL1);\ + } else { \ + if (irq < 64) \ + write_sysreg_s(bit, SYS_ICC_PPI_C##reg##R0_EL1);\ + else \ + write_sysreg_s(bit, SYS_ICC_PPI_C##reg##R1_EL1);\ + } \ + } while (0) + +static int gicv5_ppi_set_type(struct irq_data *d, unsigned int type) +{ + /* + * The PPI trigger mode is not configurable at runtime, + * therefore this function simply confirms that the `type` + * parameter matches what is present. + */ + u64 hmr =3D READ_PPI_REG(d->hwirq, HM); + + switch (type) { + case IRQ_TYPE_LEVEL_HIGH: + case IRQ_TYPE_LEVEL_LOW: + if (((hmr >> (d->hwirq % 64)) & 0x1) !=3D GICV5_PPI_HM_LEVEL) + return -EINVAL; + break; + case IRQ_TYPE_EDGE_RISING: + case IRQ_TYPE_EDGE_FALLING: + if (((hmr >> (d->hwirq % 64)) & 0x1) !=3D GICV5_PPI_HM_EDGE) + return -EINVAL; + break; + default: + pr_debug("Unexpected PPI trigger mode"); + return -EINVAL; + } + + return 0; +} + +static int gicv5_ppi_irq_get_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, + bool *val) +{ + u64 pendr, activer, enabler, hwirq_id_bit =3D BIT_ULL(d->hwirq % 64); + + switch (which) { + case IRQCHIP_STATE_PENDING: + pendr =3D READ_PPI_REG(d->hwirq, SPEND); + + *val =3D !!(pendr & hwirq_id_bit); + + return 0; + case IRQCHIP_STATE_ACTIVE: + activer =3D READ_PPI_REG(d->hwirq, SACTIVE); + + *val =3D !!(activer & hwirq_id_bit); + + return 0; + case IRQCHIP_STATE_MASKED: + enabler =3D READ_PPI_REG(d->hwirq, ENABLE); + + *val =3D !(enabler & hwirq_id_bit); + + return 0; + default: + pr_debug("Unexpected PPI irqchip state\n"); + return -EINVAL; + } + + return -EINVAL; +} + +static int gicv5_iri_irq_get_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, + bool *val, u8 hwirq_type) +{ + u64 icsr, cdrcfg; + + cdrcfg =3D d->hwirq | FIELD_PREP(GICV5_GIC_CDRCFG_TYPE_MASK, hwirq_type); + + gic_insn(cdrcfg, GICV5_OP_GIC_CDRCFG); + isb(); + icsr =3D read_sysreg_s(SYS_ICC_ICSR_EL1); + + if (FIELD_GET(ICC_ICSR_EL1_F, icsr)) { + pr_err("ICSR_EL1 is invalid\n"); + return -EINVAL; + } + + switch (which) { + case IRQCHIP_STATE_PENDING: + *val =3D !!(FIELD_GET(ICC_ICSR_EL1_Pending, icsr)); + return 0; + + case IRQCHIP_STATE_ACTIVE: + *val =3D !!(FIELD_GET(ICC_ICSR_EL1_Active, icsr)); + return 0; + + case IRQCHIP_STATE_MASKED: + *val =3D !(FIELD_GET(ICC_ICSR_EL1_Enabled, icsr)); + return 0; + + default: + pr_debug("Unexpected irqchip_irq_state\n"); + return -EINVAL; + } + + return -EINVAL; +} + +static int gicv5_spi_irq_get_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, + bool *val) +{ + return gicv5_iri_irq_get_irqchip_state(d, which, val, + GICV5_HWIRQ_TYPE_SPI); +} + +static int gicv5_lpi_irq_get_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, + bool *val) +{ + return gicv5_iri_irq_get_irqchip_state(d, which, val, + GICV5_HWIRQ_TYPE_LPI); +} + +static int gicv5_ppi_irq_set_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, + bool val) +{ + u64 hwirq_id_bit =3D BIT_ULL(d->hwirq % 64); + + switch (which) { + case IRQCHIP_STATE_PENDING: + WRITE_PPI_REG(val, d->hwirq, hwirq_id_bit, PEND); + return 0; + case IRQCHIP_STATE_ACTIVE: + WRITE_PPI_REG(val, d->hwirq, hwirq_id_bit, ACTIVE); + return 0; + case IRQCHIP_STATE_MASKED: + if (val) + gicv5_ppi_irq_mask(d); + else + gicv5_ppi_irq_unmask(d); + return 0; + default: + pr_debug("Unexpected PPI irqchip state\n"); + return -EINVAL; + } + + return -EINVAL; +} + +static void gicv5_iri_irq_write_pending_state(struct irq_data *d, bool val, + u8 hwirq_type) +{ + u64 cdpend; + + cdpend =3D FIELD_PREP(GICV5_GIC_CDPEND_TYPE_MASK, hwirq_type) | + FIELD_PREP(GICV5_GIC_CDPEND_ID_MASK, d->hwirq) | + FIELD_PREP(GICV5_GIC_CDPEND_PENDING_MASK, val); + + gic_insn(cdpend, GICV5_OP_GIC_CDPEND); +} + +static void gicv5_spi_irq_write_pending_state(struct irq_data *d, bool val) +{ + gicv5_iri_irq_write_pending_state(d, val, GICV5_HWIRQ_TYPE_SPI); +} + +static void gicv5_lpi_irq_write_pending_state(struct irq_data *d, bool val) +{ + gicv5_iri_irq_write_pending_state(d, val, GICV5_HWIRQ_TYPE_LPI); +} + +static int gicv5_spi_irq_set_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, + bool val) +{ + switch (which) { + case IRQCHIP_STATE_PENDING: + gicv5_spi_irq_write_pending_state(d, val); + break; + case IRQCHIP_STATE_MASKED: + if (val) + gicv5_spi_irq_mask(d); + else + gicv5_spi_irq_unmask(d); + break; + default: + pr_debug("Unexpected irqchip_irq_state\n"); + return -EINVAL; + } + + return 0; +} + +static int gicv5_lpi_irq_set_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, + bool val) +{ + switch (which) { + case IRQCHIP_STATE_PENDING: + gicv5_lpi_irq_write_pending_state(d, val); + break; + case IRQCHIP_STATE_MASKED: + if (val) + gicv5_lpi_irq_mask(d); + else + gicv5_lpi_irq_unmask(d); + break; + + default: + pr_debug("Unexpected irqchip_irq_state\n"); + return -EINVAL; + } + + return 0; +} + +static int gicv5_spi_irq_retrigger(struct irq_data *data) +{ + return !gicv5_spi_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, + true); +} + +static int gicv5_lpi_irq_retrigger(struct irq_data *data) +{ + return !gicv5_lpi_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, + true); +} + +static void gicv5_ipi_send_single(struct irq_data *d, unsigned int cpu) +{ + /* Mark the LPI pending */ + irq_chip_retrigger_hierarchy(d); +} + +static const struct irq_chip gicv5_ppi_irq_chip =3D { + .name =3D "GICv5-PPI", + .irq_mask =3D gicv5_ppi_irq_mask, + .irq_unmask =3D gicv5_ppi_irq_unmask, + .irq_eoi =3D gicv5_ppi_irq_eoi, + .irq_set_type =3D gicv5_ppi_set_type, + .irq_get_irqchip_state =3D gicv5_ppi_irq_get_irqchip_state, + .irq_set_irqchip_state =3D gicv5_ppi_irq_set_irqchip_state, + .flags =3D IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_MASK_ON_SUSPEND +}; + +static const struct irq_chip gicv5_spi_irq_chip =3D { + .name =3D "GICv5-SPI", + .irq_mask =3D gicv5_spi_irq_mask, + .irq_unmask =3D gicv5_spi_irq_unmask, + .irq_eoi =3D gicv5_spi_irq_eoi, + .irq_set_type =3D gicv5_spi_irq_set_type, + .irq_set_affinity =3D gicv5_spi_irq_set_affinity, + .irq_retrigger =3D gicv5_spi_irq_retrigger, + .irq_get_irqchip_state =3D gicv5_spi_irq_get_irqchip_state, + .irq_set_irqchip_state =3D gicv5_spi_irq_set_irqchip_state, + .flags =3D IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_MASK_ON_SUSPEND +}; + +static int gicv5_irq_domain_translate(struct irq_domain *d, + struct irq_fwspec *fwspec, + irq_hw_number_t *hwirq, + unsigned int *type, + u8 hwirq_type) +{ + if (!is_of_node(fwspec->fwnode)) + return -EINVAL; + + if (fwspec->param_count < 3) + return -EINVAL; + + if (fwspec->param[0] !=3D hwirq_type) + return -EINVAL; + + *hwirq =3D fwspec->param[1]; + *type =3D fwspec->param[2] & IRQ_TYPE_SENSE_MASK; + + return 0; +} + +static int gicv5_irq_ppi_domain_translate(struct irq_domain *d, + struct irq_fwspec *fwspec, + irq_hw_number_t *hwirq, + unsigned int *type) +{ + return gicv5_irq_domain_translate(d, fwspec, hwirq, type, + GICV5_HWIRQ_TYPE_PPI); +} + +static int gicv5_irq_ppi_domain_alloc(struct irq_domain *domain, unsigned = int virq, + unsigned int nr_irqs, void *arg) +{ + unsigned int type =3D IRQ_TYPE_NONE; + struct irq_fwspec *fwspec =3D arg; + irq_hw_number_t hwirq; + int ret; + + if (WARN_ON_ONCE(nr_irqs !=3D 1)) + return -EINVAL; + + ret =3D gicv5_irq_ppi_domain_translate(domain, fwspec, &hwirq, &type); + if (ret) + return ret; + + irq_set_percpu_devid(virq); + irq_domain_set_info(domain, virq, hwirq, &gicv5_ppi_irq_chip, NULL, + handle_percpu_devid_irq, NULL, NULL); + + return 0; +} + +static void gicv5_irq_domain_free(struct irq_domain *domain, unsigned int = virq, + unsigned int nr_irqs) +{ + struct irq_data *d; + + if (WARN_ON_ONCE(nr_irqs !=3D 1)) + return; + + d =3D irq_domain_get_irq_data(domain, virq); + + irq_set_handler(virq, NULL); + irq_domain_reset_irq_data(d); +} + +static int gicv5_irq_ppi_domain_select(struct irq_domain *d, struct irq_fw= spec *fwspec, + enum irq_domain_bus_token bus_token) +{ + if (fwspec->fwnode !=3D d->fwnode) + return 0; + + if (fwspec->param[0] !=3D GICV5_HWIRQ_TYPE_PPI) + return 0; + + return (d =3D=3D gicv5_global_data.ppi_domain); +} + +static const struct irq_domain_ops gicv5_irq_ppi_domain_ops =3D { + .translate =3D gicv5_irq_ppi_domain_translate, + .alloc =3D gicv5_irq_ppi_domain_alloc, + .free =3D gicv5_irq_domain_free, + .select =3D gicv5_irq_ppi_domain_select +}; + +static int gicv5_irq_spi_domain_translate(struct irq_domain *d, + struct irq_fwspec *fwspec, + irq_hw_number_t *hwirq, + unsigned int *type) +{ + return gicv5_irq_domain_translate(d, fwspec, hwirq, type, + GICV5_HWIRQ_TYPE_SPI); +} + +static int gicv5_irq_spi_domain_alloc(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs, + void *arg) +{ + struct gicv5_irs_chip_data *chip_data; + unsigned int type =3D IRQ_TYPE_NONE; + struct irq_fwspec *fwspec =3D arg; + struct irq_data *irqd; + irq_hw_number_t hwirq; + int ret; + + if (WARN_ON_ONCE(nr_irqs !=3D 1)) + return -EINVAL; + + ret =3D gicv5_irq_spi_domain_translate(domain, fwspec, &hwirq, &type); + if (ret) + return ret; + + irqd =3D irq_desc_get_irq_data(irq_to_desc(virq)); + chip_data =3D gicv5_irs_lookup_by_spi_id(hwirq); + + irq_domain_set_info(domain, virq, hwirq, &gicv5_spi_irq_chip, chip_data, + handle_fasteoi_irq, NULL, NULL); + irq_set_probe(virq); + irqd_set_single_target(irqd); + + gicv5_hwirq_init(hwirq, GICV5_IRQ_PRI_MI, GICV5_HWIRQ_TYPE_SPI); + + return 0; +} + +static int gicv5_irq_spi_domain_select(struct irq_domain *d, + struct irq_fwspec *fwspec, + enum irq_domain_bus_token bus_token) +{ + if (fwspec->fwnode !=3D d->fwnode) + return 0; + + if (fwspec->param[0] !=3D GICV5_HWIRQ_TYPE_SPI) + return 0; + + return (d =3D=3D gicv5_global_data.spi_domain); +} + +static const struct irq_domain_ops gicv5_irq_spi_domain_ops =3D { + .translate =3D gicv5_irq_spi_domain_translate, + .alloc =3D gicv5_irq_spi_domain_alloc, + .free =3D gicv5_irq_domain_free, + .select =3D gicv5_irq_spi_domain_select +}; + +static const struct irq_chip gicv5_lpi_irq_chip =3D { + .name =3D "GICv5-LPI", + .irq_mask =3D gicv5_lpi_irq_mask, + .irq_unmask =3D gicv5_lpi_irq_unmask, + .irq_eoi =3D gicv5_lpi_irq_eoi, + .irq_set_affinity =3D gicv5_lpi_irq_set_affinity, + .irq_retrigger =3D gicv5_lpi_irq_retrigger, + .irq_get_irqchip_state =3D gicv5_lpi_irq_get_irqchip_state, + .irq_set_irqchip_state =3D gicv5_lpi_irq_set_irqchip_state, + .flags =3D IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_MASK_ON_SUSPEND +}; + +static const struct irq_chip gicv5_ipi_irq_chip =3D { + .name =3D "GICv5-IPI", + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_eoi =3D irq_chip_eoi_parent, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D irq_chip_set_parent_state, + // We only handle this one in the IPI domain - the rest go to parent + .ipi_send_single =3D gicv5_ipi_send_single, + .flags =3D IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_MASK_ON_SUSPEND +}; + +static int gicv5_irq_lpi_domain_alloc(struct irq_domain *domain, unsigned = int virq, + unsigned int nr_irqs, void *arg) +{ + irq_hw_number_t hwirq; + struct irq_data *irqd; + u32 *lpi =3D arg; + int ret; + + if (WARN_ON_ONCE(nr_irqs !=3D 1)) + return -EINVAL; + + hwirq =3D *lpi; + + irqd =3D irq_domain_get_irq_data(domain, virq); + + irq_domain_set_info(domain, virq, hwirq, &gicv5_lpi_irq_chip, NULL, + handle_fasteoi_irq, NULL, NULL); + irqd_set_single_target(irqd); + + ret =3D gicv5_irs_iste_alloc(hwirq); + if (ret < 0) + return ret; + + gicv5_hwirq_init(hwirq, GICV5_IRQ_PRI_MI, GICV5_HWIRQ_TYPE_LPI); + + return 0; +} + +static void gicv5_irq_lpi_domain_free(struct irq_domain *domain, unsigned = int virq, + unsigned int nr_irqs) +{ + struct irq_data *d; + int i; + + WARN_ON_ONCE(nr_irqs !=3D 1); + + for (i =3D 0; i < nr_irqs; i++) { + d =3D irq_domain_get_irq_data(domain, virq + i); + + irq_set_handler(virq + i, NULL); + irq_domain_reset_irq_data(d); + } +} + +static const struct irq_domain_ops gicv5_irq_lpi_domain_ops =3D { + .alloc =3D gicv5_irq_lpi_domain_alloc, + .free =3D gicv5_irq_lpi_domain_free, +}; + +void __init gicv5_init_lpi_domain(void) +{ + struct irq_domain *d; + + d =3D irq_domain_create_tree(NULL, &gicv5_irq_lpi_domain_ops, NULL); + gicv5_global_data.lpi_domain =3D d; +} + +void __init gicv5_free_lpi_domain(void) +{ + irq_domain_remove(gicv5_global_data.lpi_domain); +} + +static int gicv5_irq_ipi_domain_alloc(struct irq_domain *domain, unsigned = int virq, + unsigned int nr_irqs, void *arg) +{ + struct irq_data *irqd; + int ret, i; + u32 lpi; + + for (i =3D 0; i < nr_irqs; i++) { + ret =3D gicv5_alloc_lpi(); + if (ret < 0) + return ret; + + lpi =3D ret; + + ret =3D irq_domain_alloc_irqs_parent(domain, virq + i, 1, &lpi); + if (ret) { + gicv5_free_lpi(lpi); + return ret; + } + + irqd =3D irq_domain_get_irq_data(domain, virq + i); + + irq_domain_set_hwirq_and_chip(domain, virq + i, i, + &gicv5_ipi_irq_chip, NULL); + + irqd_set_single_target(irqd); + + irq_set_handler(virq + i, handle_percpu_irq); + } + + return 0; +} + +static void gicv5_irq_ipi_domain_free(struct irq_domain *domain, unsigned = int virq, + unsigned int nr_irqs) +{ + struct irq_data *d; + unsigned int i; + + for (i =3D 0; i < nr_irqs; i++) { + d =3D irq_domain_get_irq_data(domain, virq + i); + + if (!d) + return; + + gicv5_free_lpi(d->parent_data->hwirq); + + irq_set_handler(virq + i, NULL); + irq_domain_reset_irq_data(d); + irq_domain_free_irqs_parent(domain, virq + i, 1); + } +} + +static const struct irq_domain_ops gicv5_irq_ipi_domain_ops =3D { + .alloc =3D gicv5_irq_ipi_domain_alloc, + .free =3D gicv5_irq_ipi_domain_free, +}; + +static inline void handle_irq_per_domain(u32 hwirq) +{ + u8 hwirq_type =3D FIELD_GET(GICV5_HWIRQ_TYPE, hwirq); + u32 hwirq_id =3D FIELD_GET(GICV5_HWIRQ_ID, hwirq); + struct irq_domain *domain =3D NULL; + + if (hwirq_type =3D=3D GICV5_HWIRQ_TYPE_PPI) + domain =3D gicv5_global_data.ppi_domain; + else if (hwirq_type =3D=3D GICV5_HWIRQ_TYPE_SPI) + domain =3D gicv5_global_data.spi_domain; + else if (hwirq_type =3D=3D GICV5_HWIRQ_TYPE_LPI) + domain =3D gicv5_global_data.lpi_domain; + + if (generic_handle_domain_irq(domain, hwirq_id)) { + pr_err_once("Could not handle, hwirq =3D 0x%x", hwirq_id); + gicv5_hwirq_eoi(hwirq_id, hwirq_type); + } +} + +static void __exception_irq_entry gicv5_handle_irq(struct pt_regs *regs) +{ + bool valid; + u32 hwirq; + u64 ia; + + ia =3D gicr_insn(GICV5_OP_GICR_CDIA); + valid =3D GICV5_GIC_CDIA_VALID(ia); + + if (!valid) + return; + + /* + * Ensure that the CDIA instruction effects (ie IRQ activation) are + * completed before handling the interrupt. + */ + gsb_ack(); + + /* + * Ensure instruction ordering between an acknowledgment and subsequent + * instructions in the IRQ handler using an ISB. + */ + isb(); + + hwirq =3D FIELD_GET(GICV5_HWIRQ_INTID, ia); + + handle_irq_per_domain(hwirq); +} + +static void gicv5_cpu_disable_interrupts(void) +{ + u64 cr0; + + cr0 =3D FIELD_PREP(ICC_CR0_EL1_EN, 0); + write_sysreg_s(cr0, SYS_ICC_CR0_EL1); +} + +static void gicv5_cpu_enable_interrupts(void) +{ + u64 cr0, pcr; + + write_sysreg_s(0, SYS_ICC_PPI_ENABLER0_EL1); + write_sysreg_s(0, SYS_ICC_PPI_ENABLER1_EL1); + + gicv5_ppi_priority_init(); + + pcr =3D FIELD_PREP(ICC_PCR_EL1_PRIORITY, GICV5_IRQ_PRI_MI); + write_sysreg_s(pcr, SYS_ICC_PCR_EL1); + + cr0 =3D FIELD_PREP(ICC_CR0_EL1_EN, 1); + write_sysreg_s(cr0, SYS_ICC_CR0_EL1); +} + +static int base_ipi_virq; + +static int gicv5_starting_cpu(unsigned int cpu) +{ + if (WARN(!gicv5_cpuif_has_gcie(), + "GICv5 system components present but CPU does not have FEAT_GCIE")) + return -ENODEV; + + gicv5_cpu_enable_interrupts(); + + return gicv5_irs_register_cpu(cpu); +} + +static void __init gicv5_smp_init(void) +{ + unsigned int num_ipis =3D GICV5_IPIS_PER_CPU * nr_cpu_ids; + + cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, + "irqchip/arm/gicv5:starting", + gicv5_starting_cpu, NULL); + + base_ipi_virq =3D irq_domain_alloc_irqs(gicv5_global_data.ipi_domain, + num_ipis, NUMA_NO_NODE, NULL); + if (WARN(base_ipi_virq <=3D 0, "IPI IRQ allocation was not successful")) + return; + + set_smp_ipi_range_percpu(base_ipi_virq, GICV5_IPIS_PER_CPU, nr_cpu_ids); +} + +static void __init gicv5_free_domains(void) +{ + if (gicv5_global_data.ppi_domain) + irq_domain_remove(gicv5_global_data.ppi_domain); + if (gicv5_global_data.spi_domain) + irq_domain_remove(gicv5_global_data.spi_domain); + if (gicv5_global_data.ipi_domain) + irq_domain_remove(gicv5_global_data.ipi_domain); +} + +static int __init gicv5_init_domains(struct fwnode_handle *handle) +{ + u32 spi_count =3D gicv5_global_data.global_spi_count; + struct irq_domain *d; + + d =3D irq_domain_create_linear(handle, 128, &gicv5_irq_ppi_domain_ops, + NULL); + if (!d) + return -ENOMEM; + + irq_domain_update_bus_token(d, DOMAIN_BUS_WIRED); + gicv5_global_data.ppi_domain =3D d; + + if (spi_count) { + d =3D irq_domain_create_linear(handle, spi_count, + &gicv5_irq_spi_domain_ops, NULL); + + if (!d) { + gicv5_free_domains(); + return -ENOMEM; + } + + gicv5_global_data.spi_domain =3D d; + irq_domain_update_bus_token(d, DOMAIN_BUS_WIRED); + } + + if (!WARN(!gicv5_global_data.lpi_domain, + "LPI domain uninitialized, can't set up IPIs")) { + d =3D irq_domain_create_hierarchy(gicv5_global_data.lpi_domain, + 0, GICV5_IPIS_PER_CPU * nr_cpu_ids, + NULL, &gicv5_irq_ipi_domain_ops, + NULL); + + if (!d) { + gicv5_free_domains(); + return -ENOMEM; + } + gicv5_global_data.ipi_domain =3D d; + } + gicv5_global_data.fwnode =3D handle; + + return 0; +} + +static void gicv5_set_cpuif_pribits(void) +{ + u64 icc_idr0 =3D read_sysreg_s(SYS_ICC_IDR0_EL1); + + switch (FIELD_GET(ICC_IDR0_EL1_PRI_BITS, icc_idr0)) { + case ICC_IDR0_EL1_PRI_BITS_4BITS: + gicv5_global_data.cpuif_pri_bits =3D 4; + break; + case ICC_IDR0_EL1_PRI_BITS_5BITS: + gicv5_global_data.cpuif_pri_bits =3D 5; + break; + default: + pr_err("Unexpected ICC_IDR0_EL1_PRI_BITS value, default to 4"); + gicv5_global_data.cpuif_pri_bits =3D 4; + break; + } +} + +static void gicv5_set_cpuif_idbits(void) +{ + u32 icc_idr0 =3D read_sysreg_s(SYS_ICC_IDR0_EL1); + + switch (FIELD_GET(ICC_IDR0_EL1_ID_BITS, icc_idr0)) { + case ICC_IDR0_EL1_ID_BITS_16BITS: + gicv5_global_data.cpuif_id_bits =3D 16; + break; + case ICC_IDR0_EL1_ID_BITS_24BITS: + gicv5_global_data.cpuif_id_bits =3D 24; + break; + default: + pr_err("Unexpected ICC_IDR0_EL1_ID_BITS value, default to 16"); + gicv5_global_data.cpuif_id_bits =3D 16; + break; + } +} + + +static int __init gicv5_of_init(struct device_node *node, + struct device_node *parent) +{ + int ret; + + ret =3D gicv5_irs_of_probe(node); + if (ret) + return ret; + + ret =3D gicv5_init_domains(&node->fwnode); + if (ret) + goto out_irs; + + gicv5_set_cpuif_pribits(); + gicv5_set_cpuif_idbits(); + + pri_bits =3D min_not_zero(gicv5_global_data.cpuif_pri_bits, + gicv5_global_data.irs_pri_bits); + + ret =3D gicv5_starting_cpu(smp_processor_id()); + if (ret) + goto out_dom; + + ret =3D set_handle_irq(gicv5_handle_irq); + if (ret) + goto out_int; + + ret =3D gicv5_irs_enable(); + if (ret) + goto out_int; + + gicv5_smp_init(); + + return 0; +out_int: + gicv5_cpu_disable_interrupts(); +out_dom: + gicv5_free_domains(); +out_irs: + gicv5_irs_remove(); + + return ret; +} +IRQCHIP_DECLARE(gic_v5, "arm,gic-v5", gicv5_of_init); diff --git a/drivers/irqchip/irq-gic-v5.h b/drivers/irqchip/irq-gic-v5.h new file mode 100644 index 0000000000000000000000000000000000000000..19569639153a084760c3b5b7f0f= a84791ba0195c --- /dev/null +++ b/drivers/irqchip/irq-gic-v5.h @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 ARM Limited, All Rights Reserved. + */ +#ifndef __LINUX_IRQCHIP_GIC_V5_H +#define __LINUX_IRQCHIP_GIC_V5_H + +#include +#include + +#define GICV5_IPIS_PER_CPU MAX_IPI + +#define GICV5_HWIRQ_ID GENMASK(23, 0) +#define GICV5_HWIRQ_TYPE GENMASK(31, 29) +#define GICV5_HWIRQ_INTID GENMASK_ULL(31, 0) + +#define GICV5_HWIRQ_TYPE_PPI UL(0x1) +#define GICV5_HWIRQ_TYPE_LPI UL(0x2) +#define GICV5_HWIRQ_TYPE_SPI UL(0x3) + +#define GICV5_PPI_HM_EDGE UL(0x0) +#define GICV5_PPI_HM_LEVEL UL(0x1) + +#define GICV5_NO_READ_ALLOC 0b0 +#define GICV5_READ_ALLOC 0b1 +#define GICV5_NO_WRITE_ALLOC 0b0 +#define GICV5_WRITE_ALLOC 0b1 + +#define GICV5_NON_CACHE 0b00 +#define GICV5_WB_CACHE 0b01 +#define GICV5_WT_CACHE 0b10 + +#define GICV5_NON_SHARE 0b00 +#define GICV5_OUTER_SHARE 0b10 +#define GICV5_INNER_SHARE 0b11 + +#define GICV5_IRS_IDR1 0x0004 +#define GICV5_IRS_IDR2 0x0008 +#define GICV5_IRS_IDR5 0x0014 +#define GICV5_IRS_IDR6 0x0018 +#define GICV5_IRS_IDR7 0x001c +#define GICV5_IRS_CR0 0x0080 +#define GICV5_IRS_CR1 0x0084 +#define GICV5_IRS_SPI_SELR 0x0108 +#define GICV5_IRS_SPI_CFGR 0x0114 +#define GICV5_IRS_SPI_STATUSR 0x0118 +#define GICV5_IRS_PE_SELR 0x0140 +#define GICV5_IRS_PE_STATUSR 0x0144 +#define GICV5_IRS_PE_CR0 0x0148 +#define GICV5_IRS_IST_BASER 0x0180 +#define GICV5_IRS_IST_CFGR 0x0190 +#define GICV5_IRS_IST_STATUSR 0x0194 +#define GICV5_IRS_MAP_L2_ISTR 0x01c0 + +#define GICV5_IRS_IDR1_PRIORITY_BITS GENMASK(22, 20) +#define GICV5_IRS_IDR1_IAFFID_BITS GENMASK(19, 16) + +#define GICV5_IRS_IDR1_PRIORITY_BITS_1BITS 0b000 +#define GICV5_IRS_IDR1_PRIORITY_BITS_2BITS 0b001 +#define GICV5_IRS_IDR1_PRIORITY_BITS_3BITS 0b010 +#define GICV5_IRS_IDR1_PRIORITY_BITS_4BITS 0b011 +#define GICV5_IRS_IDR1_PRIORITY_BITS_5BITS 0b100 + +#define GICV5_IRS_IDR2_ISTMD_SZ GENMASK(19, 15) +#define GICV5_IRS_IDR2_ISTMD BIT(14) +#define GICV5_IRS_IDR2_IST_L2SZ GENMASK(13, 11) +#define GICV5_IRS_IDR2_IST_LEVELS BIT(10) +#define GICV5_IRS_IDR2_MIN_LPI_ID_BITS GENMASK(9, 6) +#define GICV5_IRS_IDR2_LPI BIT(5) +#define GICV5_IRS_IDR2_ID_BITS GENMASK(4, 0) + +#define GICV5_IRS_IDR5_SPI_RANGE GENMASK(24, 0) +#define GICV5_IRS_IDR6_SPI_IRS_RANGE GENMASK(24, 0) +#define GICV5_IRS_IDR7_SPI_BASE GENMASK(23, 0) + +#define GICV5_IRS_IST_L2SZ_SUPPORT_4KB(r) FIELD_GET(BIT(11), (r)) +#define GICV5_IRS_IST_L2SZ_SUPPORT_16KB(r) FIELD_GET(BIT(12), (r)) +#define GICV5_IRS_IST_L2SZ_SUPPORT_64KB(r) FIELD_GET(BIT(13), (r)) + +#define GICV5_IRS_CR0_IDLE BIT(1) +#define GICV5_IRS_CR0_IRSEN BIT(0) + +#define GICV5_IRS_CR1_VPED_WA BIT(15) +#define GICV5_IRS_CR1_VPED_RA BIT(14) +#define GICV5_IRS_CR1_VMD_WA BIT(13) +#define GICV5_IRS_CR1_VMD_RA BIT(12) +#define GICV5_IRS_CR1_VPET_WA BIT(11) +#define GICV5_IRS_CR1_VPET_RA BIT(10) +#define GICV5_IRS_CR1_VMT_WA BIT(9) +#define GICV5_IRS_CR1_VMT_RA BIT(8) +#define GICV5_IRS_CR1_IST_WA BIT(7) +#define GICV5_IRS_CR1_IST_RA BIT(6) +#define GICV5_IRS_CR1_IC GENMASK(5, 4) +#define GICV5_IRS_CR1_OC GENMASK(3, 2) +#define GICV5_IRS_CR1_SH GENMASK(1, 0) + +#define GICV5_IRS_SPI_STATUSR_V BIT(1) +#define GICV5_IRS_SPI_STATUSR_IDLE BIT(0) + +#define GICV5_IRS_SPI_SELR_ID GENMASK(23, 0) + +#define GICV5_IRS_SPI_CFGR_TM BIT(0) + +#define GICV5_IRS_PE_SELR_IAFFID GENMASK(15, 0) + +#define GICV5_IRS_PE_STATUSR_V BIT(1) +#define GICV5_IRS_PE_STATUSR_IDLE BIT(0) + +#define GICV5_IRS_PE_CR0_DPS BIT(0) + +#define GICV5_IRS_IST_STATUSR_IDLE BIT(0) + +#define GICV5_IRS_IST_CFGR_STRUCTURE BIT(16) +#define GICV5_IRS_IST_CFGR_ISTSZ GENMASK(8, 7) +#define GICV5_IRS_IST_CFGR_L2SZ GENMASK(6, 5) +#define GICV5_IRS_IST_CFGR_LPI_ID_BITS GENMASK(4, 0) + +#define GICV5_IRS_IST_CFGR_STRUCTURE_LINEAR 0b0 +#define GICV5_IRS_IST_CFGR_STRUCTURE_TWO_LEVEL 0b1 + +#define GICV5_IRS_IST_CFGR_ISTSZ_4 0b00 +#define GICV5_IRS_IST_CFGR_ISTSZ_8 0b01 +#define GICV5_IRS_IST_CFGR_ISTSZ_16 0b10 + +#define GICV5_IRS_IST_CFGR_L2SZ_4K 0b00 +#define GICV5_IRS_IST_CFGR_L2SZ_16K 0b01 +#define GICV5_IRS_IST_CFGR_L2SZ_64K 0b10 + +#define GICV5_IRS_IST_BASER_ADDR_MASK GENMASK_ULL(55, 6) +#define GICV5_IRS_IST_BASER_VALID BIT_ULL(0) + +#define GICV5_IRS_MAP_L2_ISTR_ID GENMASK(23, 0) + +#define GICV5_ISTL1E_VALID BIT_ULL(0) + +#define GICV5_ISTL1E_L2_ADDR_MASK GENMASK_ULL(55, 12) + +struct gicv5_chip_data { + struct fwnode_handle *fwnode; + struct irq_domain *ppi_domain; + struct irq_domain *spi_domain; + struct irq_domain *lpi_domain; + struct irq_domain *ipi_domain; + u32 global_spi_count; + u8 cpuif_pri_bits; + u8 cpuif_id_bits; + u8 irs_pri_bits; + u8 irs_iaffid_bits; + struct { + __le64 *l1ist_addr; + u32 l2_size; + u8 l2_bits; + bool l2; + } ist; +}; + +extern struct gicv5_chip_data gicv5_global_data __read_mostly; + +struct gicv5_irs_chip_data { + struct list_head entry; + struct fwnode_handle *fwnode; + void __iomem *irs_base; + u32 flags; + u32 spi_min; + u32 spi_range; + raw_spinlock_t spi_config_lock; +}; + +void __init gicv5_init_lpi_domain(void); +void __init gicv5_free_lpi_domain(void); + +int gicv5_irs_of_probe(struct device_node *parent); +void gicv5_irs_remove(void); +int gicv5_irs_enable(void); +int gicv5_irs_register_cpu(int cpuid); +int gicv5_irs_cpu_to_iaffid(int cpu_id, u16 *iaffid); +struct gicv5_irs_chip_data *gicv5_irs_lookup_by_spi_id(u32 spi_id); +int gicv5_spi_irq_set_type(struct irq_data *d, unsigned int type); +int gicv5_spi_set_type(struct irq_data *d, unsigned int type); +int gicv5_irs_iste_alloc(u32 lpi); + +void gicv5_init_lpis(u32 max); +void gicv5_deinit_lpis(void); +#endif --=20 2.48.0 From nobody Sun Feb 8 13:09:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8824A22FF55; Thu, 24 Apr 2025 10:27:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490454; cv=none; b=kMDGtCml+uL/+38zFf6o2b5/Fc26BKhSofPKCabBj81/+iSp82pJRLAJwU7iWmbP0bh7VotQjd5UaJpUUPEfKpaVqfjlNbnccKBcy8NGdBA/77oFXe/hn2yRx/CslxY2dxbhltGNFJ/rQIs/y4LC6WsalJNly2S6JCcLMPX86OY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490454; c=relaxed/simple; bh=wtRCpNR7+FNMQRJBvxqrjW+9t2Xp8F5h3uGBdnds4Dk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=f+8niALENPXroVsEpz8s1T7SSB913DxS9h99+IenDaiptQfbTFuzGM7iuiWLPuC82CY0kIssn/4mbuo6pLrn64e9w/hZaRbalS9GAPeK/OGHwKF3Pr+WYdOP49ESl2tIQx6/X3hTwDuB8T+M7P6vzaHgXNAV8HVEoi2k/niTWrI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SuqC4fLf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SuqC4fLf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E2093C4CEE3; Thu, 24 Apr 2025 10:27:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745490454; bh=wtRCpNR7+FNMQRJBvxqrjW+9t2Xp8F5h3uGBdnds4Dk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=SuqC4fLfv5uS/+qD2PqVl6e6ShlZGT+Gh+6PkOBmzAAUlnvI6xqNl5o/AtjlBj/DN DASFRy1WveSz/jNueA5GGoEKKGb6/JFx8i8tvEKf/KiS+wV+6BHUMTl+il0rzLfLqt 3n4RfRcFdEbxIr7Qxy2hzDp3OVIungmbRRbhbS9oWIK374eMxMNDcr89Sr0nm77wWS l9aTFHFKF7ICcAiOhm8MliPjSEV75l8TXjteCSzOo0IHD9RzNLI7yeDnc/q1a9fzv6 nQI5cFuUtz8WbJpb6Ls8cO3kJzvjE0bB56yitVE6vtIwZ9h8kokzQW884uA1DhAcl9 bewFTUuBYlmZg== From: Lorenzo Pieralisi Date: Thu, 24 Apr 2025 12:25:31 +0200 Subject: [PATCH v2 20/22] irqchip/gic-v5: Add GICv5 ITS support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-gicv5-host-v2-20-545edcaf012b@kernel.org> References: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> In-Reply-To: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.14.2 The GICv5 architecture implements Interrupt Translation Service (ITS) components in order to translate events coming from peripherals into interrupt events delivered to the connected IRSes. Events (ie MSI memory writes to ITS translate frame), are translated by the ITS using tables kept in memory. ITS translation tables for peripherals is kept in memory storage (device table [DT] and Interrupt Translation Table [ITT]) that is allocated by the driver on boot. Both tables can be 1- or 2-level; the structure is chosen by the driver after probing the ITS HW parameters and checking the allowed table splits and supported {device/event}_IDbits. DT table entries are allocated on demand (ie when a device is probed); the DT table is sized using the number of supported deviceID bits in that that's a system design decision (ie the number of deviceID bits implemented should reflect the number of devices expected in a system) therefore it makes sense to allocate a DT table that can cater for the maximum number of devices. DT and ITT tables are allocated using the kmalloc interface; the allocation size may be smaller than a page or larger, and must provide contiguous memory pages. LPIs INTIDs backing the device events are allocated one-by-one and only upon Linux IRQ allocation; this to avoid preallocating a large number of LPIs to cover the HW device MSI vector size whereas few MSI entries are actually enabled by a device. ITS cacheability/shareability attributes are programmed according to the provided firmware ITS description. The GICv5 ITS reuses the GICv3 MSI parent infrastructure, there is no need to duplicate it, make it common. Co-developed-by: Sascha Bischoff Signed-off-by: Sascha Bischoff Co-developed-by: Timothy Hayes Signed-off-by: Timothy Hayes Signed-off-by: Lorenzo Pieralisi Cc: Thomas Gleixner Cc: Marc Zyngier --- MAINTAINERS | 1 + drivers/irqchip/Kconfig | 11 + drivers/irqchip/Makefile | 4 +- drivers/irqchip/irq-gic-common.h | 2 - ...3-its-msi-parent.c =3D> irq-gic-its-msi-parent.c} | 3 +- drivers/irqchip/irq-gic-its-msi-parent.h | 13 + drivers/irqchip/irq-gic-v3-its.c | 3 +- drivers/irqchip/irq-gic-v5-irs.c | 40 +- drivers/irqchip/irq-gic-v5-its.c | 1293 ++++++++++++++++= ++++ drivers/irqchip/irq-gic-v5.c | 6 +- drivers/irqchip/irq-gic-v5.h | 176 +++ 11 files changed, 1529 insertions(+), 23 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index cdeceb6782355a4a18609135bf7f03249d8b0bb5..d231077c024deba42153663ac66= b6c05f7673f03 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1908,6 +1908,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated fo= r non-subscribers) S: Maintained F: Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml F: arch/arm64/include/asm/arch_gicv5.h +F: drivers/irqchip/irq-gic-its-msi-parent.[ch] F: drivers/irqchip/irq-gic-v5*.[ch] =20 ARM HDLCD DRM DRIVER diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 160a4761d5d85f6dbf36f3142fd619c114733e36..6c348d421b05af0e4f4909877e0= 2ac8ef19178ff 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -41,10 +41,14 @@ config ARM_GIC_V3 select HAVE_ARM_SMCCC_DISCOVERY select IRQ_MSI_IOMMU =20 +config ARM_GIC_ITS_PARENT + bool + config ARM_GIC_V3_ITS bool select GENERIC_MSI_IRQ select IRQ_MSI_LIB + select ARM_GIC_ITS_PARENT default ARM_GIC_V3 select IRQ_MSI_IOMMU =20 @@ -59,6 +63,13 @@ config ARM_GIC_V5 select IRQ_DOMAIN_HIERARCHY select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP =20 +config ARM_GIC_V5_ITS + bool + select GENERIC_MSI_IRQ + select IRQ_MSI_LIB + select ARM_GIC_ITS_PARENT + default ARM_GIC_V5 + config ARM_NVIC bool select IRQ_DOMAIN_HIERARCHY diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 3d9c47fa3fdf40b7452c059d84fe8ac24c91bc0f..4280395e3bdff7858102f0b4eaa= ea1121cace52f 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -32,10 +32,12 @@ obj-$(CONFIG_ARCH_REALVIEW) +=3D irq-gic-realview.o obj-$(CONFIG_IRQ_MSI_LIB) +=3D irq-msi-lib.o obj-$(CONFIG_ARM_GIC_V2M) +=3D irq-gic-v2m.o obj-$(CONFIG_ARM_GIC_V3) +=3D irq-gic-v3.o irq-gic-v3-mbi.o irq-gic-commo= n.o -obj-$(CONFIG_ARM_GIC_V3_ITS) +=3D irq-gic-v3-its.o irq-gic-v4.o irq-gic-v= 3-its-msi-parent.o +obj-$(CONFIG_ARM_GIC_ITS_PARENT) +=3D irq-gic-its-msi-parent.o +obj-$(CONFIG_ARM_GIC_V3_ITS) +=3D irq-gic-v3-its.o irq-gic-v4.o obj-$(CONFIG_ARM_GIC_V3_ITS_FSL_MC) +=3D irq-gic-v3-its-fsl-mc-msi.o obj-$(CONFIG_PARTITION_PERCPU) +=3D irq-partition-percpu.o obj-$(CONFIG_ARM_GIC_V5) +=3D irq-gic-v5.o irq-gic-v5-irs.o +obj-$(CONFIG_ARM_GIC_V5_ITS) +=3D irq-gic-v5-its.o obj-$(CONFIG_HISILICON_IRQ_MBIGEN) +=3D irq-mbigen.o obj-$(CONFIG_ARM_NVIC) +=3D irq-nvic.o obj-$(CONFIG_ARM_VIC) +=3D irq-vic.o diff --git a/drivers/irqchip/irq-gic-common.h b/drivers/irqchip/irq-gic-com= mon.h index 020ecdf16901c9720e5746aec4d0b5b39d3625ed..710cab61d9195a0bd64d57e03c6= 0852c4cd6ff8e 100644 --- a/drivers/irqchip/irq-gic-common.h +++ b/drivers/irqchip/irq-gic-common.h @@ -29,8 +29,6 @@ void gic_enable_quirks(u32 iidr, const struct gic_quirk *= quirks, void gic_enable_of_quirks(const struct device_node *np, const struct gic_quirk *quirks, void *data); =20 -extern const struct msi_parent_ops gic_v3_its_msi_parent_ops; - #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) #define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1) #define RDIST_FLAGS_FORCE_NON_SHAREABLE (1 << 2) diff --git a/drivers/irqchip/irq-gic-v3-its-msi-parent.c b/drivers/irqchip/= irq-gic-its-msi-parent.c similarity index 98% rename from drivers/irqchip/irq-gic-v3-its-msi-parent.c rename to drivers/irqchip/irq-gic-its-msi-parent.c index bdb04c8081480de468fb217b68c6933a8e1e2bd7..71edcdb2defdfd5b892d8635403= 9d2e46b832ea5 100644 --- a/drivers/irqchip/irq-gic-v3-its-msi-parent.c +++ b/drivers/irqchip/irq-gic-its-msi-parent.c @@ -7,7 +7,6 @@ #include #include =20 -#include "irq-gic-common.h" #include "irq-msi-lib.h" =20 #define ITS_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ @@ -200,7 +199,7 @@ static bool its_init_dev_msi_info(struct device *dev, s= truct irq_domain *domain, return true; } =20 -const struct msi_parent_ops gic_v3_its_msi_parent_ops =3D { +const struct msi_parent_ops gic_its_msi_parent_ops =3D { .supported_flags =3D ITS_MSI_FLAGS_SUPPORTED, .required_flags =3D ITS_MSI_FLAGS_REQUIRED, .chip_flags =3D MSI_CHIP_FLAG_SET_EOI | MSI_CHIP_FLAG_SET_ACK, diff --git a/drivers/irqchip/irq-gic-its-msi-parent.h b/drivers/irqchip/irq= -gic-its-msi-parent.h new file mode 100644 index 0000000000000000000000000000000000000000..e7bb7f3862eef379e5b85fe7bd5= eb72f3586d3b7 --- /dev/null +++ b/drivers/irqchip/irq-gic-its-msi-parent.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2024 ARM Limited, All Rights Reserved. + */ + +#ifndef _IRQ_GIC_ITS_MSI_PARENT_H +#define _IRQ_GIC_ITS_MSI_PARENT_H + +#include + +extern const struct msi_parent_ops gic_its_msi_parent_ops; + +#endif /* _IRQ_GIC_ITS_MSI_PARENT_H */ diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-= its.c index 0115ad6c82593de511c285d99437996919bfa308..6c51bf4e34a38103d612c74476d= 640cd4126e8b6 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -41,6 +41,7 @@ #include =20 #include "irq-gic-common.h" +#include "irq-gic-its-msi-parent.h" #include "irq-msi-lib.h" =20 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) @@ -5139,7 +5140,7 @@ static int its_init_domain(struct its_node *its) =20 irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS); =20 - inner_domain->msi_parent_ops =3D &gic_v3_its_msi_parent_ops; + inner_domain->msi_parent_ops =3D &gic_its_msi_parent_ops; inner_domain->flags |=3D IRQ_DOMAIN_FLAG_MSI_PARENT; =20 return 0; diff --git a/drivers/irqchip/irq-gic-v5-irs.c b/drivers/irqchip/irq-gic-v5-= irs.c index 7bd60e6d56b77c0c19a1bd9bee9685d9b6ffc959..ff9de8fe175f511b2e81f712fa2= e69b96f3e66fb 100644 --- a/drivers/irqchip/irq-gic-v5-irs.c +++ b/drivers/irqchip/irq-gic-v5-irs.c @@ -5,7 +5,6 @@ =20 #define pr_fmt(fmt) "GICv5 IRS: " fmt =20 -#include #include #include #include @@ -44,20 +43,6 @@ static void irs_writeq_relaxed(struct gicv5_irs_chip_dat= a *irs_data, writeq_relaxed(val, irs_data->irs_base + reg_offset); } =20 -static int gicv5_wait_for_op(void __iomem *addr, u32 offset, u32 mask, u32= *val) -{ - void __iomem *reg =3D addr + offset; - u32 tmp; - int ret; - - ret =3D readl_poll_timeout_atomic(reg, tmp, tmp & mask, 1, 10 * USEC_PER_= MSEC); - - if (val) - *val =3D tmp; - - return ret; -} - #define gicv5_irs_wait_for_op(base, reg, mask) \ ({ \ int ret; \ @@ -528,6 +513,23 @@ static int gicv5_irs_wait_for_idle(struct gicv5_irs_ch= ip_data *irs_data) GICV5_IRS_CR0_IDLE); } =20 +void gicv5_irs_syncr(void) +{ + struct gicv5_irs_chip_data *irs_data; + u32 syncr; + + irs_data =3D list_first_entry_or_null(&irs_nodes, + struct gicv5_irs_chip_data, entry); + if (WARN_ON(!irs_data)) + return; + + syncr =3D FIELD_PREP(GICV5_IRS_SYNCR_SYNC, 1); + irs_writel_relaxed(irs_data, syncr, GICV5_IRS_SYNCR); + + gicv5_irs_wait_for_op(irs_data->irs_base, GICV5_IRS_SYNC_STATUSR, + GICV5_IRS_SYNC_STATUSR_IDLE); +} + int gicv5_irs_register_cpu(int cpuid) { struct gicv5_irs_chip_data *irs_data; @@ -823,6 +825,14 @@ int __init gicv5_irs_enable(void) return 0; } =20 +void __init gicv5_irs_its_probe(void) +{ + struct gicv5_irs_chip_data *irs_data; + + list_for_each_entry(irs_data, &irs_nodes, entry) + gicv5_its_of_probe(to_of_node(irs_data->fwnode)); +} + int __init gicv5_irs_of_probe(struct device_node *parent) { struct device_node *np; diff --git a/drivers/irqchip/irq-gic-v5-its.c b/drivers/irqchip/irq-gic-v5-= its.c new file mode 100644 index 0000000000000000000000000000000000000000..da349b4709cc5ec897885923783= 8f039389ca4a1 --- /dev/null +++ b/drivers/irqchip/irq-gic-v5-its.c @@ -0,0 +1,1293 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024-2025 ARM Limited, All Rights Reserved. + */ + +#define pr_fmt(fmt) "GICv5 ITS: " fmt + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "irq-gic-v5.h" +#include "irq-gic-its-msi-parent.h" +#include "irq-msi-lib.h" + +#define ITS_FLAGS_NON_COHERENT BIT(0) + +static LIST_HEAD(its_nodes); + +static u32 its_readl_relaxed(struct gicv5_its_chip_data *its_node, + const u64 reg_offset) +{ + return readl_relaxed(its_node->its_base + reg_offset); +} + +static void its_writel_relaxed(struct gicv5_its_chip_data *its_node, + const u32 val, const u64 reg_offset) +{ + writel_relaxed(val, its_node->its_base + reg_offset); +} + +static void its_writeq_relaxed(struct gicv5_its_chip_data *its_node, + const u64 val, const u64 reg_offset) +{ + writeq_relaxed(val, its_node->its_base + reg_offset); +} + +static void its_write_table_entry(struct gicv5_its_chip_data *its, + __le64 *entry, u64 val) +{ + WRITE_ONCE(*entry, val); + if (its->flags & ITS_FLAGS_NON_COHERENT) + dcache_clean_inval_poc((unsigned long)entry, + (unsigned long)entry + sizeof(*entry)); + else + dsb(ishst); +} + +#define gicv5_its_wait_for_op(base, reg, mask) \ + ({ \ + int ret; \ + \ + ret =3D gicv5_wait_for_op(base, reg, mask, NULL); \ + if (unlikely(ret =3D=3D -ETIMEDOUT)) \ + pr_err_ratelimited(#reg" timeout...\n"); \ + ret; \ + }) + +static int gicv5_its_wait_for_invalidation(struct gicv5_its_chip_data *its) +{ + return gicv5_its_wait_for_op(its->its_base, GICV5_ITS_STATUSR, + GICV5_ITS_STATUSR_IDLE); +} + +static void gicv5_its_syncr(struct gicv5_its_chip_data *its, + struct gicv5_its_dev *its_dev) +{ + u64 syncr; + + syncr =3D FIELD_PREP(GICV5_ITS_SYNCR_SYNC, 1) | + FIELD_PREP(GICV5_ITS_SYNCR_DEVICEID, its_dev->device_id); + + its_writeq_relaxed(its, syncr, GICV5_ITS_SYNCR); + + gicv5_its_wait_for_op(its->its_base, GICV5_ITS_SYNC_STATUSR, + GICV5_ITS_SYNC_STATUSR_IDLE); +} + +static int gicv5_its_l2sz_to_l2_bits(unsigned int sz) +{ + switch (sz) { + case GICV5_ITS_DT_ITT_CFGR_L2SZ_4k: + return 9; + case GICV5_ITS_DT_ITT_CFGR_L2SZ_16k: + return 11; + case GICV5_ITS_DT_ITT_CFGR_L2SZ_64k: + return 13; + default: + return -EINVAL; + } +} + +static int gicv5_its_itt_cache_inv(struct gicv5_its_chip_data *its, + u32 device_id, u16 event_id) +{ + u32 eventr, eidr; + u64 didr; + + didr =3D FIELD_PREP(GICV5_ITS_DIDR_DEVICEID, device_id); + eidr =3D FIELD_PREP(GICV5_ITS_EIDR_EVENTID, event_id); + eventr =3D FIELD_PREP(GICV5_ITS_INV_EVENTR_I, 0x1); + + its_writeq_relaxed(its, didr, GICV5_ITS_DIDR); + its_writel_relaxed(its, eidr, GICV5_ITS_EIDR); + its_writel_relaxed(its, eventr, GICV5_ITS_INV_EVENTR); + + return gicv5_its_wait_for_invalidation(its); +} + +static void gicv5_its_free_itt_linear(struct gicv5_its_dev *its_dev) +{ + kfree(its_dev->itt_cfg.linear.itt); +} + +static void gicv5_its_free_itt_two_level(struct gicv5_its_dev *its_dev) +{ + unsigned int i, num_ents =3D its_dev->itt_cfg.l2.num_l1_ents; + + for (i =3D 0; i < num_ents; i++) + kfree(its_dev->itt_cfg.l2.l2ptrs[i]); + + kfree(its_dev->itt_cfg.l2.l2ptrs); + kfree(its_dev->itt_cfg.l2.l1itt); +} + +static void gicv5_its_free_itt(struct gicv5_its_dev *its_dev) +{ + if (!its_dev->itt_cfg.l2itt) + gicv5_its_free_itt_linear(its_dev); + else + gicv5_its_free_itt_two_level(its_dev); +} + +static int gicv5_its_create_itt_linear(struct gicv5_its_chip_data *its, + struct gicv5_its_dev *its_dev, + unsigned int event_id_bits) +{ + unsigned int num_ents =3D BIT(event_id_bits); + __le64 *itt; + + itt =3D kcalloc(num_ents, sizeof(*itt), GFP_KERNEL); + if (!itt) + return -ENOMEM; + + its_dev->itt_cfg.linear.itt =3D itt; + its_dev->itt_cfg.linear.num_ents =3D num_ents; + its_dev->itt_cfg.l2itt =3D false; + its_dev->itt_cfg.event_id_bits =3D event_id_bits; + + if (its->flags & ITS_FLAGS_NON_COHERENT) + dcache_clean_inval_poc((unsigned long)itt, + (unsigned long)itt + num_ents * sizeof(*itt)); + else + dsb(ishst); + + return 0; +} + +/* + * Allocate a two-level ITT. All ITT entries are allocated in one go, unli= ke + * with the device table. Span may be used to limit the second level table + * size, where possible. + */ +static int gicv5_its_create_itt_two_level(struct gicv5_its_chip_data *its, + struct gicv5_its_dev *its_dev, + unsigned int event_id_bits, + unsigned int itt_l2sz, + unsigned int num_events) +{ + unsigned int l1_bits, l2_bits, span, events_per_l2_table, + complete_tables, final_span, num_ents; + __le64 *itt_l1, *itt_l2, **l2ptrs; + size_t l1sz; + int ret, i; + u64 val; + + ret =3D gicv5_its_l2sz_to_l2_bits(itt_l2sz); + if (ret < 0 || ret >=3D event_id_bits) { + pr_debug("Incorrect l2sz (0x%x) for %u EventID bits. Cannot allocate ITT= \n", + itt_l2sz, event_id_bits); + return -EINVAL; + } + + l2_bits =3D ret; + + l1_bits =3D event_id_bits - l2_bits; + + num_ents =3D BIT(l1_bits); + + itt_l1 =3D kcalloc(num_ents, sizeof(*itt_l1), GFP_KERNEL); + if (!itt_l1) + return -ENOMEM; + + l2ptrs =3D kcalloc(num_ents, sizeof(*l2ptrs), GFP_KERNEL); + if (!l2ptrs) { + kfree(itt_l1); + return -ENOMEM; + } + + its_dev->itt_cfg.l2.l2ptrs =3D l2ptrs; + + its_dev->itt_cfg.l2.l2sz =3D itt_l2sz; + its_dev->itt_cfg.l2.l1itt =3D itt_l1; + its_dev->itt_cfg.l2.num_l1_ents =3D num_ents; + its_dev->itt_cfg.l2itt =3D true; + its_dev->itt_cfg.event_id_bits =3D event_id_bits; + + /* + * Need to determine how many entries there are per L2 - this is based + * on the number of bits in the table. + */ + events_per_l2_table =3D BIT(l2_bits); + complete_tables =3D num_events / events_per_l2_table; + final_span =3D order_base_2(num_events % events_per_l2_table); + + for (i =3D 0; i < num_ents; i++) { + size_t l2sz; + + span =3D i =3D=3D complete_tables ? final_span : l2_bits; + + itt_l2 =3D kcalloc(BIT(span), sizeof(*itt_l2), GFP_KERNEL); + if (!itt_l2) { + ret =3D -ENOMEM; + goto out_free; + } + + its_dev->itt_cfg.l2.l2ptrs[i] =3D itt_l2; + + l2sz =3D BIT(span) * sizeof(*itt_l2); + + if (its->flags & ITS_FLAGS_NON_COHERENT) + dcache_clean_inval_poc((unsigned long)itt_l2, + (unsigned long)itt_l2 + l2sz); + + val =3D (virt_to_phys(itt_l2) & GICV5_ITTL1E_L2_ADDR_MASK) | + FIELD_PREP(GICV5_ITTL1E_SPAN, span) | + FIELD_PREP(GICV5_ITTL1E_VALID, 0x1); + + WRITE_ONCE(itt_l1[i], cpu_to_le64(val)); + } + + if (its->flags & ITS_FLAGS_NON_COHERENT) { + l1sz =3D num_ents * sizeof(*itt_l1); + dcache_clean_inval_poc((unsigned long)itt_l1, + (unsigned long)itt_l1 + l1sz); + } else { + dsb(ishst); + } + + return 0; +out_free: + for (i =3D i - 1; i >=3D 0; i--) + kfree(its_dev->itt_cfg.l2.l2ptrs[i]); + + kfree(its_dev->itt_cfg.l2.l2ptrs); + kfree(itt_l1); + return ret; +} + +/* + * Function to check whether the device table or ITT table support + * a two-level table and if so depending on the number of id_bits + * requested, determine whether a two-level table is required. + * + * Return the 2-level size value if a two level table is deemed + * necessary. + */ +static bool gicv5_its_l2sz_two_level(bool devtab, u32 its_idr1, u8 id_bits, + u8 *sz) +{ + int l2_bits, l2_sz =3D -EINVAL; + + if (devtab && !FIELD_GET(GICV5_ITS_IDR1_DT_LEVELS, its_idr1)) + return false; + + if (!devtab && !FIELD_GET(GICV5_ITS_IDR1_ITT_LEVELS, its_idr1)) + return false; + + /* + * Pick an L2 size that matches the pagesize; if a match + * is not found, go for the smallest supported l2 size granule. + * + * This ensures that we will always be able to allocate + * contiguous memory at L2. + */ + switch (PAGE_SIZE) { + case SZ_64K: + if (GICV5_ITS_IDR1_L2SZ_SUPPORT_64KB(its_idr1)) { + l2_sz =3D GICV5_ITS_DT_ITT_CFGR_L2SZ_64k; + break; + } + fallthrough; + case SZ_16K: + if (GICV5_ITS_IDR1_L2SZ_SUPPORT_16KB(its_idr1)) { + l2_sz =3D GICV5_ITS_DT_ITT_CFGR_L2SZ_16k; + break; + } + fallthrough; + case SZ_4K: + if (GICV5_ITS_IDR1_L2SZ_SUPPORT_4KB(its_idr1)) { + l2_sz =3D GICV5_ITS_DT_ITT_CFGR_L2SZ_4k; + break; + } + if (GICV5_ITS_IDR1_L2SZ_SUPPORT_16KB(its_idr1)) { + l2_sz =3D GICV5_ITS_DT_ITT_CFGR_L2SZ_16k; + break; + } + if (GICV5_ITS_IDR1_L2SZ_SUPPORT_64KB(its_idr1)) { + l2_sz =3D GICV5_ITS_DT_ITT_CFGR_L2SZ_64k; + break; + } + break; + } + + l2_bits =3D gicv5_its_l2sz_to_l2_bits(l2_sz); + + if (l2_bits < 0 || l2_bits > id_bits) + return false; + + *sz =3D l2_sz; + + return true; +} + +static int gicv5_its_device_get_itte_ref(struct gicv5_its_dev *its_dev, + __le64 **itte, u16 event_id) +{ + if (!its_dev->itt_cfg.l2itt) { + __le64 *itt =3D its_dev->itt_cfg.linear.itt; + *itte =3D &itt[event_id]; + } else { + __le64 *l2_itt, *l1_itt =3D its_dev->itt_cfg.l2.l1itt; + unsigned int l1_idx, l2_idx, l2_size, l2_bits; + int ret; + + ret =3D gicv5_its_l2sz_to_l2_bits(its_dev->itt_cfg.l2.l2sz); + if (ret < 0) + return ret; + l2_bits =3D ret; + + l1_idx =3D event_id >> l2_bits; + + if (!FIELD_GET(GICV5_ITTL1E_VALID, + le64_to_cpu(l1_itt[l1_idx]))) { + pr_debug("L1 ITT entry is not valid.\n"); + return -EINVAL; + } + + l2_idx =3D event_id & GENMASK(l2_bits - 1, 0); + + l2_size =3D BIT(FIELD_GET(GICV5_ITTL1E_SPAN, + le64_to_cpu(l1_itt[l1_idx]))); + + // Sanity check our indexing + if (l2_idx >=3D l2_size) { + pr_debug("L2 ITT index (%u) exceeds L2 table size (%u)!\n", + l2_idx, l2_size); + return -EINVAL; + } + l2_itt =3D its_dev->itt_cfg.l2.l2ptrs[l1_idx]; + *itte =3D &l2_itt[l2_idx]; + } + + return 0; +} + +static int gicv5_its_device_cache_inv(struct gicv5_its_chip_data *its, + struct gicv5_its_dev *its_dev) +{ + u32 devicer; + u64 didr; + + didr =3D FIELD_PREP(GICV5_ITS_DIDR_DEVICEID, its_dev->device_id); + devicer =3D FIELD_PREP(GICV5_ITS_INV_DEVICER_I, 0x1) | + FIELD_PREP(GICV5_ITS_INV_DEVICER_EVENTID_BITS, + its_dev->itt_cfg.event_id_bits) | + FIELD_PREP(GICV5_ITS_INV_DEVICER_L1, 0x0); + its_writeq_relaxed(its, didr, GICV5_ITS_DIDR); + its_writel_relaxed(its, devicer, GICV5_ITS_INV_DEVICER); + + return gicv5_its_wait_for_invalidation(its); +} + +/* + * Allocate a level 2 device table entry, update L1 parent to reference it. + * Only used for 2-level device tables, and it is called on demand. + */ +static int gicv5_its_alloc_l2_devtab(struct gicv5_its_chip_data *its, + unsigned int l1_index) +{ + __le64 *l2devtab, *l1devtab =3D its->devtab_cfgr.l2.l1devtab; + u8 span, l2sz, l2_bits; + u64 l1dte; + int ret; + + if (FIELD_GET(GICV5_DTL1E_VALID, le64_to_cpu(l1devtab[l1_index]))) + return 0; + + span =3D FIELD_GET(GICV5_DTL1E_SPAN, le64_to_cpu(l1devtab[l1_index])); + l2sz =3D FIELD_GET(GICV5_ITS_DT_CFGR_L2SZ, its->devtab_cfgr.cfgr); + + ret =3D gicv5_its_l2sz_to_l2_bits(l2sz); + if (ret < 0) + return ret; + + l2_bits =3D ret; + + /* + * Span allows us to create a smaller L2 device table. + * If it is too large, use the number of allowed L2 bits. + */ + if (span > l2_bits) + span =3D l2_bits; + + l2devtab =3D kcalloc(BIT(span), sizeof(*l2devtab), GFP_KERNEL); + if (!l2devtab) + return -ENOMEM; + + its->devtab_cfgr.l2.l2ptrs[l1_index] =3D l2devtab; + + l1dte =3D FIELD_PREP(GICV5_DTL1E_SPAN, span) | + (virt_to_phys(l2devtab) & GICV5_DTL1E_L2_ADDR_MASK) | + FIELD_PREP(GICV5_DTL1E_VALID, 0x1); + its_write_table_entry(its, &l1devtab[l1_index], cpu_to_le64(l1dte)); + + return 0; +} + +static int gicv5_its_devtab_get_dte_ref(struct gicv5_its_chip_data *its, + __le64 **dte, u32 device_id, + bool alloc) +{ + u8 str =3D FIELD_GET(GICV5_ITS_DT_CFGR_STRUCTURE, its->devtab_cfgr.cfgr); + unsigned int l2sz, l2_bits, l1_idx, l2_idx; + __le64 *l1devtab, *l2devtab; + int ret; + + if (str =3D=3D GICV5_ITS_DT_ITT_CFGR_STRUCTURE_LINEAR) { + l2devtab =3D its->devtab_cfgr.linear.devtab; + *dte =3D &l2devtab[device_id]; + } else { + l2sz =3D FIELD_GET(GICV5_ITS_DT_CFGR_L2SZ, its->devtab_cfgr.cfgr); + l1devtab =3D its->devtab_cfgr.l2.l1devtab; + + ret =3D gicv5_its_l2sz_to_l2_bits(l2sz); + if (ret < 0) + return -EINVAL; + + l2_bits =3D ret; + l1_idx =3D device_id >> l2_bits; + l2_idx =3D device_id & GENMASK(l2_bits - 1, 0); + + if (alloc) { + /* + * Allocate a new L2 device table here before + * continuing. We make the assumption that the span in + * the L1 table has been set correctly, and blindly use + * that value. + */ + ret =3D gicv5_its_alloc_l2_devtab(its, l1_idx); + if (ret) + return ret; + } else { + if (!FIELD_GET(GICV5_DTL1E_VALID, + le64_to_cpu(l1devtab[l1_idx]))) + return -EINVAL; + } + + l2devtab =3D its->devtab_cfgr.l2.l2ptrs[l1_idx]; + *dte =3D &l2devtab[l2_idx]; + } + + return 0; +} + +/* + * Register a new device in the device table. Allocate an ITT and + * program the L2DTE entry according to the ITT structure that + * was chosen. + */ +static int gicv5_its_device_register(struct gicv5_its_chip_data *its, + struct gicv5_its_dev *its_dev) +{ + u8 event_id_bits, device_id_bits, itt_struct, itt_l2sz; + phys_addr_t itt_phys_base; + bool two_level_itt; + u32 idr1, idr2; + __le64 *dte; + u64 val; + int ret; + + device_id_bits =3D FIELD_GET(GICV5_ITS_DT_CFGR_DEVICEID_BITS, + its->devtab_cfgr.cfgr); + + if (its_dev->device_id >=3D BIT(device_id_bits)) { + pr_err("Supplied DeviceID (%u) outside of Device Table range (%u)!", + its_dev->device_id, (u32)GENMASK(device_id_bits - 1, 0)); + return -EINVAL; + } + + ret =3D gicv5_its_devtab_get_dte_ref(its, &dte, its_dev->device_id, true); + if (ret) + return ret; + + if (FIELD_GET(GICV5_DTL2E_VALID, le64_to_cpu(*dte))) + return -EBUSY; + + /* + * Determine how many bits we need, validate those against the max. + * Based on these, determine if we should go for a 1- or 2-level ITT. + */ + event_id_bits =3D order_base_2(its_dev->num_events); + + idr2 =3D its_readl_relaxed(its, GICV5_ITS_IDR2); + + if (event_id_bits > FIELD_GET(GICV5_ITS_IDR2_EVENTID_BITS, idr2)) { + pr_err("Required EventID bits (%u) larger than supported bits (%u)!", + event_id_bits, + (u8)FIELD_GET(GICV5_ITS_IDR2_EVENTID_BITS, idr2)); + return -EINVAL; + } + + idr1 =3D its_readl_relaxed(its, GICV5_ITS_IDR1); + + /* + * L2 ITT size is programmed into the L2DTE regardless of + * whether a two-level or linear ITT is built, init it. + */ + itt_l2sz =3D 0; + + two_level_itt =3D gicv5_its_l2sz_two_level(false, idr1, event_id_bits, + &itt_l2sz); + if (two_level_itt) + ret =3D gicv5_its_create_itt_two_level(its, its_dev, event_id_bits, + itt_l2sz, + its_dev->num_events); + else + ret =3D gicv5_its_create_itt_linear(its, its_dev, event_id_bits); + if (ret) + return ret; + + itt_phys_base =3D two_level_itt ? virt_to_phys(its_dev->itt_cfg.l2.l1itt)= : + virt_to_phys(its_dev->itt_cfg.linear.itt); + + itt_struct =3D two_level_itt ? GICV5_ITS_DT_ITT_CFGR_STRUCTURE_TWO_LEVEL : + GICV5_ITS_DT_ITT_CFGR_STRUCTURE_LINEAR; + + val =3D FIELD_PREP(GICV5_DTL2E_EVENT_ID_BITS, event_id_bits) | + FIELD_PREP(GICV5_DTL2E_ITT_STRUCTURE, itt_struct) | + (itt_phys_base & GICV5_DTL2E_ITT_ADDR_MASK) | + FIELD_PREP(GICV5_DTL2E_ITT_L2SZ, itt_l2sz) | + FIELD_PREP(GICV5_DTL2E_VALID, 0x1); + + its_write_table_entry(its, dte, cpu_to_le64(val)); + + ret =3D gicv5_its_device_cache_inv(its, its_dev); + if (ret) { + gicv5_its_free_itt(its_dev); + its_write_table_entry(its, dte, 0); + return ret; + } + + return 0; +} + +/* + * Unregister a device in the device table. Lookup the device by ID, free = the + * corresponding ITT, mark the device as invalid in the device table. + */ +static int gicv5_its_device_unregister(struct gicv5_its_chip_data *its, + struct gicv5_its_dev *its_dev) +{ + __le64 *dte; + int ret; + + ret =3D gicv5_its_devtab_get_dte_ref(its, &dte, its_dev->device_id, false= ); + if (ret) { + pr_debug("Failed to find DTE for DeviceID 0x%x\n", its_dev->device_id); + return -EINVAL; + } + + if (!FIELD_GET(GICV5_DTL2E_VALID, le64_to_cpu(*dte))) { + pr_debug("Device table entry for DeviceID 0x%x is not valid. Nothing to = clean up!", + its_dev->device_id); + return -EINVAL; + } + + gicv5_its_free_itt(its_dev); + + /* Zero everything - make it clear that this is an invalid entry */ + its_write_table_entry(its, dte, 0); + + return gicv5_its_device_cache_inv(its, its_dev); +} + +/* + * Allocate a 1-level device table. All entries are allocated, but marked + * invalid. + */ +static int gicv5_its_alloc_devtab_linear(struct gicv5_its_chip_data *its, + u8 device_id_bits) +{ + __le64 *devtab; + size_t sz; + u64 baser; + u32 cfgr; + + /* + * We expect a GICv5 implementation requiring a large number of + * deviceID bits to support a 2-level device table. If that's not + * the case, cap the number of deviceIDs supported according to the + * kmalloc limits so that the system can chug along with a linear + * device table. + */ + sz =3D BIT_ULL(device_id_bits) * sizeof(*devtab); + if (sz > KMALLOC_MAX_SIZE) { + u8 device_id_cap =3D ilog2(KMALLOC_MAX_SIZE/sizeof(*devtab)); + + pr_warn("Limiting device ID bits from %u to %u\n", + device_id_bits, device_id_cap); + device_id_bits =3D device_id_cap; + } + + devtab =3D kcalloc(BIT(device_id_bits), sizeof(*devtab), GFP_KERNEL); + if (!devtab) + return -ENOMEM; + + if (its->flags & ITS_FLAGS_NON_COHERENT) + dcache_clean_inval_poc((unsigned long)devtab, + (unsigned long)devtab + sz); + else + dsb(ishst); + + cfgr =3D FIELD_PREP(GICV5_ITS_DT_CFGR_STRUCTURE, + GICV5_ITS_DT_ITT_CFGR_STRUCTURE_LINEAR) | + FIELD_PREP(GICV5_ITS_DT_CFGR_L2SZ, 0) | + FIELD_PREP(GICV5_ITS_DT_CFGR_DEVICEID_BITS, device_id_bits); + its_writel_relaxed(its, cfgr, GICV5_ITS_DT_CFGR); + + baser =3D virt_to_phys(devtab) & GICV5_ITS_DT_BASER_ADDR_MASK; + its_writeq_relaxed(its, baser, GICV5_ITS_DT_BASER); + + its->devtab_cfgr.cfgr =3D cfgr; + its->devtab_cfgr.linear.devtab =3D devtab; + + return 0; +} + +/* + * Allocate a 2-level device table. L2 entries are not allocated, + * they are allocated on-demand. + */ +static int gicv5_its_alloc_devtab_two_level(struct gicv5_its_chip_data *it= s, + u8 device_id_bits, + u8 devtab_l2sz) +{ + unsigned int l1_bits, l2_bits, i; + __le64 *l1devtab, **l2ptrs; + size_t l1_sz; + u64 baser; + u32 cfgr; + int ret; + + ret =3D gicv5_its_l2sz_to_l2_bits(devtab_l2sz); + if (ret < 0) + return ret; + + l2_bits =3D ret; + + l1_bits =3D device_id_bits - l2_bits; + l1_sz =3D BIT(l1_bits) * sizeof(*l1devtab); + /* + * With 2-level device table support it is highly unlikely + * that we are not able to allocate the required amount of + * device table memory to cover deviceID space; cap the + * deviceID space if we encounter such set-up. + * If this ever becomes a problem we could revisit the policy + * behind level 2 size selection to reduce level-1 deviceID bits. + */ + if (l1_sz > KMALLOC_MAX_SIZE) { + l1_bits =3D ilog2(KMALLOC_MAX_SIZE/sizeof(*l1devtab)); + + pr_warn("Limiting device ID bits from %u to %u\n", + device_id_bits, l1_bits + l2_bits); + device_id_bits =3D l1_bits + l2_bits; + l1_sz =3D KMALLOC_MAX_SIZE; + } + + l1devtab =3D kcalloc(BIT(l1_bits), sizeof(*l1devtab), GFP_KERNEL); + if (!l1devtab) + return -ENOMEM; + + l2ptrs =3D kcalloc(BIT(l1_bits), sizeof(*l2ptrs), GFP_KERNEL); + if (!l2ptrs) { + kfree(l1devtab); + return -ENOMEM; + } + + for (i =3D 0; i < BIT(l1_bits); i++) + l1devtab[i] =3D cpu_to_le64(FIELD_PREP(GICV5_DTL1E_SPAN, l2_bits)); + + if (its->flags & ITS_FLAGS_NON_COHERENT) + dcache_clean_inval_poc((unsigned long)l1devtab, + (unsigned long)l1devtab + l1_sz); + else + dsb(ishst); + + cfgr =3D FIELD_PREP(GICV5_ITS_DT_CFGR_STRUCTURE, + GICV5_ITS_DT_ITT_CFGR_STRUCTURE_TWO_LEVEL) | + FIELD_PREP(GICV5_ITS_DT_CFGR_L2SZ, devtab_l2sz) | + FIELD_PREP(GICV5_ITS_DT_CFGR_DEVICEID_BITS, device_id_bits); + its_writel_relaxed(its, cfgr, GICV5_ITS_DT_CFGR); + + baser =3D virt_to_phys(l1devtab) & GICV5_ITS_DT_BASER_ADDR_MASK; + its_writeq_relaxed(its, baser, GICV5_ITS_DT_BASER); + + its->devtab_cfgr.cfgr =3D cfgr; + its->devtab_cfgr.l2.l1devtab =3D l1devtab; + its->devtab_cfgr.l2.l2ptrs =3D l2ptrs; + + return 0; +} + +/* + * Initialise the device table as either 1- or 2-level depending on what is + * supported by the hardware. + */ +static int gicv5_its_init_devtab(struct gicv5_its_chip_data *its) +{ + u8 device_id_bits, devtab_l2sz; + bool two_level_devtab; + u32 idr1; + + idr1 =3D its_readl_relaxed(its, GICV5_ITS_IDR1); + + device_id_bits =3D FIELD_GET(GICV5_ITS_IDR1_DEVICEID_BITS, idr1); + two_level_devtab =3D gicv5_its_l2sz_two_level(true, idr1, device_id_bits, + &devtab_l2sz); + if (two_level_devtab) + return gicv5_its_alloc_devtab_two_level(its, device_id_bits, + devtab_l2sz); + else + return gicv5_its_alloc_devtab_linear(its, device_id_bits); +} + +static void gicv5_its_compose_msi_msg(struct irq_data *d, struct msi_msg *= msg) +{ + struct gicv5_its_dev *its_dev =3D irq_data_get_irq_chip_data(d); + struct gicv5_its_chip_data *its =3D its_dev->its_node; + u64 addr; + + addr =3D its->its_trans_phys_base; + + msg->data =3D FIELD_GET(GICV5_ITS_HWIRQ_EVENT_ID, d->hwirq); + msi_msg_set_addr(irq_data_get_msi_desc(d), msg, addr); +} + +static const struct irq_chip gicv5_its_irq_chip =3D { + .name =3D "GICv5-ITS-MSI", + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_eoi =3D irq_chip_eoi_parent, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D irq_chip_set_parent_state, + .irq_compose_msi_msg =3D gicv5_its_compose_msi_msg, + .flags =3D IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_MASK_ON_SUSPEND +}; + +static struct gicv5_its_dev *gicv5_its_find_device(struct gicv5_its_chip_d= ata *its, + u32 device_id) +{ + struct gicv5_its_dev *dev =3D xa_load(&its->its_devices, device_id); + + return dev ? dev : ERR_PTR(-ENODEV); +} + +static struct gicv5_its_dev *gicv5_its_alloc_device( + struct gicv5_its_chip_data *its, int nvec, + u32 dev_id) +{ + struct gicv5_its_dev *its_dev; + int ret; + + its_dev =3D gicv5_its_find_device(its, dev_id); + if (!IS_ERR(its_dev)) { + pr_debug("A device with this DeviceID (0x%x) has already been registered= .\n", + dev_id); + + if (nvec > its_dev->num_events) { + pr_debug("Requesting more ITT entries than allocated\n"); + return ERR_PTR(-ENXIO); + } + + its_dev->shared =3D true; + + return its_dev; + } + + its_dev =3D kzalloc(sizeof(*its_dev), GFP_KERNEL); + if (!its_dev) + return ERR_PTR(-ENOMEM); + + its_dev->device_id =3D dev_id; + its_dev->num_events =3D nvec; + its_dev->num_mapped_events =3D 0; + + ret =3D gicv5_its_device_register(its, its_dev); + if (ret) { + pr_debug("Failed to register the device\n"); + kfree(its_dev); + return ERR_PTR(ret); + } + + gicv5_its_device_cache_inv(its, its_dev); + + /* + * This is the first time we have seen this device. Hence, it is not + * shared. + */ + its_dev->shared =3D false; + + its_dev->its_node =3D its; + + its_dev->event_map =3D + (unsigned long *)bitmap_zalloc(its_dev->num_events, GFP_KERNEL); + if (!its_dev->event_map) { + gicv5_its_device_unregister(its, its_dev); + kfree(its_dev); + return ERR_PTR(-ENOMEM); + } + + xa_store(&its->its_devices, dev_id, its_dev, GFP_KERNEL); + + return its_dev; +} + +static int gicv5_its_msi_prepare(struct irq_domain *domain, struct device = *dev, + int nvec, msi_alloc_info_t *info) +{ + u32 dev_id =3D info->scratchpad[0].ul; + struct msi_domain_info *msi_info; + struct gicv5_its_chip_data *its; + struct gicv5_its_dev *its_dev; + + msi_info =3D msi_get_domain_info(domain); + its =3D msi_info->data; + + guard(mutex)(&its->dev_alloc_lock); + + its_dev =3D gicv5_its_alloc_device(its, nvec, dev_id); + if (IS_ERR(its_dev)) + return PTR_ERR(its_dev); + + if (info->flags & MSI_ALLOC_FLAGS_PROXY_DEVICE) + its_dev->shared =3D true; + + return 0; +} + +static struct msi_domain_ops its_msi_domain_ops =3D { + .msi_prepare =3D gicv5_its_msi_prepare, +}; + +static int gicv5_its_alloc_event(struct gicv5_its_dev *its_dev, u16 event_= id, + u32 lpi) +{ + struct gicv5_its_chip_data *its =3D its_dev->its_node; + u64 itt_entry; + __le64 *itte; + int ret; + + if (event_id >=3D its_dev->num_events) { + pr_debug("EventID 0x%x outside of ITT range (0x%x)\n", event_id, + its_dev->num_events); + return -EINVAL; + } + + if (WARN(its_dev->num_mapped_events =3D=3D its_dev->num_events, + "Reached maximum number of events\n")) + return -EINVAL; + + ret =3D gicv5_its_device_get_itte_ref(its_dev, &itte, event_id); + if (ret) + return ret; + + if (FIELD_GET(GICV5_ITTL2E_VALID, *itte)) + return -EEXIST; + + itt_entry =3D FIELD_PREP(GICV5_ITTL2E_LPI_ID, lpi) | + FIELD_PREP(GICV5_ITTL2E_VALID, 0x1); + + its_write_table_entry(its, itte, cpu_to_le64(itt_entry)); + + gicv5_its_itt_cache_inv(its, its_dev->device_id, event_id); + + its_dev->num_mapped_events +=3D 1; + + return 0; +} + +static void gicv5_its_free_event(struct gicv5_its_dev *its_dev, u16 event_= id) +{ + struct gicv5_its_chip_data *its =3D its_dev->its_node; + u64 itte_val; + __le64 *itte; + int ret; + + if (WARN(!its_dev->num_mapped_events, "No mapped events\n")) + return; + + ret =3D gicv5_its_device_get_itte_ref(its_dev, &itte, event_id); + if (ret) { + pr_debug("Failed to get the ITTE!\n"); + return; + } + + itte_val =3D le64_to_cpu(*itte); + itte_val &=3D ~GICV5_ITTL2E_VALID; + + its_write_table_entry(its, itte, cpu_to_le64(itte_val)); + + gicv5_its_itt_cache_inv(its, its_dev->device_id, event_id); + + its_dev->num_mapped_events -=3D 1; +} + +static int gicv5_its_alloc_eventid(struct gicv5_its_dev *its_dev, + unsigned int nr_irqs, u32 *eventid) +{ + int ret; + + ret =3D bitmap_find_free_region(its_dev->event_map, + its_dev->num_events, + get_count_order(nr_irqs)); + + if (ret < 0) + return ret; + + *eventid =3D ret; + + return 0; +} + +static void gicv5_its_free_eventid(struct gicv5_its_dev *its_dev, + u32 event_id_base, + unsigned int nr_irqs) +{ + bitmap_release_region(its_dev->event_map, event_id_base, + get_count_order(nr_irqs)); +} + +static int gicv5_its_irq_domain_alloc(struct irq_domain *domain, unsigned = int virq, + unsigned int nr_irqs, void *arg) +{ + u32 device_id, event_id_base, lpi; + struct msi_domain_info *msi_info; + struct gicv5_its_chip_data *its; + struct gicv5_its_dev *its_dev; + msi_alloc_info_t *info =3D arg; + irq_hw_number_t hwirq; + struct irq_data *irqd; + int ret, i; + + device_id =3D info->scratchpad[0].ul; + + msi_info =3D msi_get_domain_info(domain); + its =3D msi_info->data; + + mutex_lock(&its->dev_alloc_lock); + + its_dev =3D gicv5_its_find_device(its, device_id); + if (IS_ERR(its_dev)) { + mutex_unlock(&its->dev_alloc_lock); + return PTR_ERR(its_dev); + } + + ret =3D gicv5_its_alloc_eventid(its_dev, nr_irqs, &event_id_base); + if (ret) { + mutex_unlock(&its->dev_alloc_lock); + return ret; + } + + mutex_unlock(&its->dev_alloc_lock); + + ret =3D iommu_dma_prepare_msi(info->desc, its->its_trans_phys_base); + if (ret) + goto out_eventid; + + for (i =3D 0; i < nr_irqs; i++) { + lpi =3D gicv5_alloc_lpi(); + if (ret < 0) { + pr_debug("Failed to find free LPI!\n"); + goto out_eventid; + } + + ret =3D irq_domain_alloc_irqs_parent(domain, virq + i, 1, &lpi); + if (ret) + goto out_free_lpi; + + /* + * Store eventid and deviceid into the hwirq for later use. + * + * hwirq =3D event_id << 32 | device_id + */ + hwirq =3D FIELD_PREP(GICV5_ITS_HWIRQ_DEVICE_ID, device_id) | + FIELD_PREP(GICV5_ITS_HWIRQ_EVENT_ID, (u64)event_id_base + i); + irq_domain_set_info(domain, virq + i, hwirq, + &gicv5_its_irq_chip, its_dev, + handle_fasteoi_irq, NULL, NULL); + + irqd =3D irq_get_irq_data(virq + i); + irqd_set_single_target(irqd); + irqd_set_affinity_on_activate(irqd); + irqd_set_resend_when_in_progress(irqd); + } + + return 0; +out_free_lpi: + gicv5_free_lpi(lpi); +out_eventid: + gicv5_its_free_eventid(its_dev, event_id_base, nr_irqs); + + return ret; +} + +static void gicv5_its_irq_domain_free(struct irq_domain *domain, unsigned = int virq, + unsigned int nr_irqs) +{ + struct msi_domain_info *msi_info; + struct gicv5_its_chip_data *its; + struct gicv5_its_dev *its_dev; + struct irq_data *d; + u16 event_id_base; + bool free_device; + u32 device_id; + int i; + + msi_info =3D msi_get_domain_info(domain); + its =3D msi_info->data; + + d =3D irq_domain_get_irq_data(domain, virq); + device_id =3D FIELD_GET(GICV5_ITS_HWIRQ_DEVICE_ID, d->hwirq); + event_id_base =3D FIELD_GET(GICV5_ITS_HWIRQ_EVENT_ID, d->hwirq); + + guard(mutex)(&its->dev_alloc_lock); + + its_dev =3D gicv5_its_find_device(its, device_id); + if (IS_ERR(its_dev)) { + pr_debug("Couldn't find the ITS device!\n"); + return; + } + + bitmap_release_region(its_dev->event_map, event_id_base, + get_count_order(nr_irqs)); + + free_device =3D !its_dev->shared && bitmap_empty(its_dev->event_map, + its_dev->num_events); + + /* Hierarchically free irq data */ + for (i =3D 0; i < nr_irqs; i++) { + d =3D irq_domain_get_irq_data(domain, virq + i); + + gicv5_free_lpi(d->parent_data->hwirq); + irq_domain_reset_irq_data(d); + } + irq_domain_free_irqs_parent(domain, virq, nr_irqs); + + gicv5_its_syncr(its, its_dev); + gicv5_irs_syncr(); + + if (free_device) { + gicv5_its_device_unregister(its, its_dev); + bitmap_free(its_dev->event_map); + xa_erase(&its->its_devices, device_id); + kfree(its_dev); + } +} + +static int gicv5_its_irq_domain_activate(struct irq_domain *domain, + struct irq_data *d, bool reserve) +{ + struct gicv5_its_dev *its_dev =3D irq_data_get_irq_chip_data(d); + u16 event_id; + u32 lpi; + + event_id =3D FIELD_GET(GICV5_ITS_HWIRQ_EVENT_ID, d->hwirq); + lpi =3D d->parent_data->hwirq; + + return gicv5_its_alloc_event(its_dev, event_id, lpi); +} + +static void gicv5_its_irq_domain_deactivate(struct irq_domain *domain, + struct irq_data *d) +{ + struct gicv5_its_dev *its_dev =3D irq_data_get_irq_chip_data(d); + u16 event_id; + + event_id =3D FIELD_GET(GICV5_ITS_HWIRQ_EVENT_ID, d->hwirq); + + gicv5_its_free_event(its_dev, event_id); +} +static const struct irq_domain_ops gicv5_its_irq_domain_ops =3D { + .alloc =3D gicv5_its_irq_domain_alloc, + .free =3D gicv5_its_irq_domain_free, + .activate =3D gicv5_its_irq_domain_activate, + .deactivate =3D gicv5_its_irq_domain_deactivate, + .select =3D msi_lib_irq_domain_select, +}; + +static int gicv5_its_wait_for_cr0(struct gicv5_its_chip_data *its) +{ + return gicv5_its_wait_for_op(its->its_base, GICV5_ITS_CR0, + GICV5_ITS_CR0_IDLE); +} + +static void gicv5_its_print_info(struct gicv5_its_chip_data *its_node) +{ + bool devtab_linear; + u8 device_id_bits; + u8 str; + + device_id_bits =3D FIELD_GET(GICV5_ITS_DT_CFGR_DEVICEID_BITS, + its_node->devtab_cfgr.cfgr); + + str =3D FIELD_GET(GICV5_ITS_DT_CFGR_STRUCTURE, its_node->devtab_cfgr.cfgr= ); + devtab_linear =3D (str =3D=3D GICV5_ITS_DT_ITT_CFGR_STRUCTURE_LINEAR); + + pr_info("ITS %s enabled using %s device table device_id_bits %u\n", + fwnode_get_name(its_node->fwnode), + devtab_linear ? "linear" : "2-level", + device_id_bits); +} + +static int __init gicv5_its_init_bases(phys_addr_t its_trans_base, + void __iomem *its_base, + struct fwnode_handle *handle, + struct irq_domain *parent_domain) +{ + struct device_node *np =3D to_of_node(handle); + struct gicv5_its_chip_data *its_node; + struct msi_domain_info *info; + struct irq_domain *d; + u32 cr0, cr1; + bool enabled; + int ret; + + info =3D kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + its_node =3D kzalloc(sizeof(*its_node), GFP_KERNEL); + if (!its_node) { + kfree(info); + return -ENOMEM; + } + + info->ops =3D &its_msi_domain_ops; + info->data =3D its_node; + + mutex_init(&its_node->dev_alloc_lock); + xa_init(&its_node->its_devices); + its_node->fwnode =3D handle; + its_node->its_base =3D its_base; + its_node->its_trans_phys_base =3D its_trans_base; + + d =3D irq_domain_create_hierarchy(parent_domain, IRQ_DOMAIN_FLAG_ISOLATED= _MSI, + 0, handle, &gicv5_its_irq_domain_ops, info); + its_node->domain =3D d; + irq_domain_update_bus_token(its_node->domain, DOMAIN_BUS_NEXUS); + + its_node->domain->msi_parent_ops =3D &gic_its_msi_parent_ops; + its_node->domain->flags |=3D IRQ_DOMAIN_FLAG_MSI_PARENT; + + cr0 =3D its_readl_relaxed(its_node, GICV5_ITS_CR0); + enabled =3D FIELD_GET(GICV5_ITS_CR0_ITSEN, cr0); + if (WARN(enabled, "ITS %s enabled, disabling it before proceeding\n", + np->full_name)) { + cr0 =3D FIELD_PREP(GICV5_ITS_CR0_ITSEN, 0x0); + its_writel_relaxed(its_node, cr0, GICV5_ITS_CR0); + ret =3D gicv5_its_wait_for_cr0(its_node); + if (ret) { + irq_domain_remove(its_node->domain); + kfree(info); + kfree(its_node); + return ret; + } + } + + if (of_property_read_bool(np, "dma-noncoherent")) { + /* + * A non-coherent ITS implies that some cache levels cannot be + * used coherently by the cores and GIC. Our only option is to mark + * memory attributes for the GIC as non-cacheable; by default, + * non-cacheable memory attributes imply outer-shareable + * shareability, the value written into ITS_CR1_SH is ignored. + */ + cr1 =3D FIELD_PREP(GICV5_ITS_CR1_ITT_RA, GICV5_NO_READ_ALLOC) | + FIELD_PREP(GICV5_ITS_CR1_DT_RA, GICV5_NO_READ_ALLOC) | + FIELD_PREP(GICV5_ITS_CR1_IC, GICV5_NON_CACHE) | + FIELD_PREP(GICV5_ITS_CR1_OC, GICV5_NON_CACHE); + its_node->flags |=3D ITS_FLAGS_NON_COHERENT; + } else { + cr1 =3D FIELD_PREP(GICV5_ITS_CR1_ITT_RA, GICV5_READ_ALLOC) | + FIELD_PREP(GICV5_ITS_CR1_DT_RA, GICV5_READ_ALLOC) | + FIELD_PREP(GICV5_ITS_CR1_IC, GICV5_WB_CACHE) | + FIELD_PREP(GICV5_ITS_CR1_OC, GICV5_WB_CACHE) | + FIELD_PREP(GICV5_ITS_CR1_SH, GICV5_INNER_SHARE); + } + + its_writel_relaxed(its_node, cr1, GICV5_ITS_CR1); + + ret =3D gicv5_its_init_devtab(its_node); + if (ret) { + irq_domain_remove(its_node->domain); + kfree(info); + kfree(its_node); + return ret; + } + + cr0 =3D FIELD_PREP(GICV5_ITS_CR0_ITSEN, 0x1); + its_writel_relaxed(its_node, cr0, GICV5_ITS_CR0); + + ret =3D gicv5_its_wait_for_cr0(its_node); + if (ret) { + irq_domain_remove(its_node->domain); + kfree(info); + kfree(its_node); + return ret; + } + + list_add(&its_node->entry, &its_nodes); + + gicv5_its_print_info(its_node); + + return 0; +} + +static int __init gicv5_its_init(struct device_node *node) +{ + void __iomem *its_base; + struct resource res; + int ret; + + its_base =3D of_io_request_and_map(node, 0, "ITS"); + if (IS_ERR(its_base)) { + pr_err("%pOF: unable to map GICv5 ITS_CONFIG_FRAME\n", node); + return PTR_ERR(its_base); + } + + /* + * The ITS_TRANSLATE_FRAME is the second reg entry, (first is the + * ITS_CONFIG_FRAME) - extract it and use it to init ITS data + * structures. + */ + ret =3D of_address_to_resource(node, 1, &res); + if (ret) + goto out_unmap; + + ret =3D gicv5_its_init_bases(res.start, its_base, &node->fwnode, + gicv5_global_data.lpi_domain); + if (ret) + goto out_unmap; + + return 0; +out_unmap: + iounmap(its_base); + return ret; +} + +void __init gicv5_its_of_probe(struct device_node *parent) +{ + struct device_node *np; + + for_each_available_child_of_node(parent, np) { + if (!of_device_is_compatible(np, "arm,gic-v5-its")) + continue; + + if (gicv5_its_init(np)) + pr_err("Failed to init ITS %s\n", np->full_name); + } +} diff --git a/drivers/irqchip/irq-gic-v5.c b/drivers/irqchip/irq-gic-v5.c index c4d4e85382f672fa4ae334db1a4e4c7c4f46b9fe..e483d0774936035b5cf2407da9a= 65d776bad3138 100644 --- a/drivers/irqchip/irq-gic-v5.c +++ b/drivers/irqchip/irq-gic-v5.c @@ -55,12 +55,12 @@ static void release_lpi(u32 lpi) ida_free(&lpi_ida, lpi); } =20 -static int gicv5_alloc_lpi(void) +int gicv5_alloc_lpi(void) { return alloc_lpi(); } =20 -static void gicv5_free_lpi(u32 lpi) +void gicv5_free_lpi(u32 lpi) { release_lpi(lpi); } @@ -1045,6 +1045,8 @@ static int __init gicv5_of_init(struct device_node *n= ode, =20 gicv5_smp_init(); =20 + gicv5_irs_its_probe(); + return 0; out_int: gicv5_cpu_disable_interrupts(); diff --git a/drivers/irqchip/irq-gic-v5.h b/drivers/irqchip/irq-gic-v5.h index 19569639153a084760c3b5b7f0fa84791ba0195c..f5a453599493020b36d9c7f18c0= 8171c51ba8669 100644 --- a/drivers/irqchip/irq-gic-v5.h +++ b/drivers/irqchip/irq-gic-v5.h @@ -5,6 +5,8 @@ #ifndef __LINUX_IRQCHIP_GIC_V5_H #define __LINUX_IRQCHIP_GIC_V5_H =20 +#include + #include #include =20 @@ -41,6 +43,8 @@ #define GICV5_IRS_IDR7 0x001c #define GICV5_IRS_CR0 0x0080 #define GICV5_IRS_CR1 0x0084 +#define GICV5_IRS_SYNCR 0x00c0 +#define GICV5_IRS_SYNC_STATUSR 0x00c4 #define GICV5_IRS_SPI_SELR 0x0108 #define GICV5_IRS_SPI_CFGR 0x0114 #define GICV5_IRS_SPI_STATUSR 0x0118 @@ -94,6 +98,10 @@ #define GICV5_IRS_CR1_OC GENMASK(3, 2) #define GICV5_IRS_CR1_SH GENMASK(1, 0) =20 +#define GICV5_IRS_SYNCR_SYNC BIT(31) + +#define GICV5_IRS_SYNC_STATUSR_IDLE BIT(0) + #define GICV5_IRS_SPI_STATUSR_V BIT(1) #define GICV5_IRS_SPI_STATUSR_IDLE BIT(0) =20 @@ -135,6 +143,101 @@ =20 #define GICV5_ISTL1E_L2_ADDR_MASK GENMASK_ULL(55, 12) =20 +#define GICV5_ITS_IDR1 0x0004 +#define GICV5_ITS_IDR2 0x0008 +#define GICV5_ITS_CR0 0x0080 +#define GICV5_ITS_CR1 0x0084 +#define GICV5_ITS_DT_BASER 0x00c0 +#define GICV5_ITS_DT_CFGR 0x00d0 +#define GICV5_ITS_DIDR 0x0100 +#define GICV5_ITS_EIDR 0x0108 +#define GICV5_ITS_INV_EVENTR 0x010c +#define GICV5_ITS_INV_DEVICER 0x0110 +#define GICV5_ITS_STATUSR 0x0120 +#define GICV5_ITS_SYNCR 0x0140 +#define GICV5_ITS_SYNC_STATUSR 0x0148 + +#define GICV5_ITS_IDR1_L2SZ GENMASK(10, 8) +#define GICV5_ITS_IDR1_ITT_LEVELS BIT(7) +#define GICV5_ITS_IDR1_DT_LEVELS BIT(6) +#define GICV5_ITS_IDR1_DEVICEID_BITS GENMASK(5, 0) + +#define GICV5_ITS_IDR1_L2SZ_SUPPORT_4KB(r) FIELD_GET(BIT(8), (r)) +#define GICV5_ITS_IDR1_L2SZ_SUPPORT_16KB(r) FIELD_GET(BIT(9), (r)) +#define GICV5_ITS_IDR1_L2SZ_SUPPORT_64KB(r) FIELD_GET(BIT(10), (r)) + +#define GICV5_ITS_IDR2_XDMN_EVENTs GENMASK(6, 5) +#define GICV5_ITS_IDR2_EVENTID_BITS GENMASK(4, 0) + +#define GICV5_ITS_CR0_IDLE BIT(1) +#define GICV5_ITS_CR0_ITSEN BIT(0) + +#define GICV5_ITS_CR1_ITT_RA BIT(7) +#define GICV5_ITS_CR1_DT_RA BIT(6) +#define GICV5_ITS_CR1_IC GENMASK(5, 4) +#define GICV5_ITS_CR1_OC GENMASK(3, 2) +#define GICV5_ITS_CR1_SH GENMASK(1, 0) + +#define GICV5_ITS_DT_CFGR_STRUCTURE BIT(16) +#define GICV5_ITS_DT_CFGR_L2SZ GENMASK(7, 6) +#define GICV5_ITS_DT_CFGR_DEVICEID_BITS GENMASK(5, 0) + +#define GICV5_ITS_DT_BASER_ADDR_MASK GENMASK_ULL(55, 3) + +#define GICV5_ITS_INV_DEVICER_I BIT(31) +#define GICV5_ITS_INV_DEVICER_EVENTID_BITS GENMASK(5, 1) +#define GICV5_ITS_INV_DEVICER_L1 BIT(0) + +#define GICV5_ITS_DIDR_DEVICEID GENMASK_ULL(31, 0) + +#define GICV5_ITS_EIDR_EVENTID GENMASK(15, 0) + +#define GICV5_ITS_INV_EVENTR_I BIT(31) +#define GICV5_ITS_INV_EVENTR_ITT_L2SZ GENMASK(2, 1) +#define GICV5_ITS_INV_EVENTR_L1 BIT(0) + +#define GICV5_ITS_STATUSR_IDLE BIT(0) + +#define GICV5_ITS_SYNCR_SYNC BIT_ULL(63) +#define GICV5_ITS_SYNCR_SYNCALL BIT_ULL(32) +#define GICV5_ITS_SYNCR_DEVICEID GENMASK_ULL(31, 0) + +#define GICV5_ITS_SYNC_STATUSR_IDLE BIT(0) + +#define GICV5_DTL1E_VALID BIT_ULL(0) +// Note that there is no shift for the address by design +#define GICV5_DTL1E_L2_ADDR_MASK GENMASK_ULL(55, 3) +#define GICV5_DTL1E_SPAN GENMASK_ULL(63, 60) + +#define GICV5_DTL2E_VALID BIT_ULL(0) +#define GICV5_DTL2E_ITT_L2SZ GENMASK_ULL(2, 1) +// Note that there is no shift for the address by design +#define GICV5_DTL2E_ITT_ADDR_MASK GENMASK_ULL(55, 3) +#define GICV5_DTL2E_ITT_DSWE BIT_ULL(57) +#define GICV5_DTL2E_ITT_STRUCTURE BIT_ULL(58) +#define GICV5_DTL2E_EVENT_ID_BITS GENMASK_ULL(63, 59) + +#define GICV5_ITTL1E_VALID BIT_ULL(0) +// Note that there is no shift for the address by design +#define GICV5_ITTL1E_L2_ADDR_MASK GENMASK_ULL(55, 3) +#define GICV5_ITTL1E_SPAN GENMASK_ULL(63, 60) + +#define GICV5_ITTL2E_LPI_ID GENMASK_ULL(23, 0) +#define GICV5_ITTL2E_DAC GENMASK_ULL(29, 28) +#define GICV5_ITTL2E_VIRTUAL BIT_ULL(30) +#define GICV5_ITTL2E_VALID BIT_ULL(31) +#define GICV5_ITTL2E_VM_ID GENMASK_ULL(47, 32) + +#define GICV5_ITS_DT_ITT_CFGR_L2SZ_4k 0b00 +#define GICV5_ITS_DT_ITT_CFGR_L2SZ_16k 0b01 +#define GICV5_ITS_DT_ITT_CFGR_L2SZ_64k 0b10 + +#define GICV5_ITS_DT_ITT_CFGR_STRUCTURE_LINEAR 0 +#define GICV5_ITS_DT_ITT_CFGR_STRUCTURE_TWO_LEVEL 1 + +#define GICV5_ITS_HWIRQ_DEVICE_ID GENMASK_ULL(31, 0) +#define GICV5_ITS_HWIRQ_EVENT_ID GENMASK_ULL(63, 32) + struct gicv5_chip_data { struct fwnode_handle *fwnode; struct irq_domain *ppi_domain; @@ -168,17 +271,90 @@ struct gicv5_irs_chip_data { =20 void __init gicv5_init_lpi_domain(void); void __init gicv5_free_lpi_domain(void); +static inline int gicv5_wait_for_op(void __iomem *addr, u32 offset, u32 ma= sk, + u32 *val) +{ + void __iomem *reg =3D addr + offset; + u32 tmp; + int ret; + + ret =3D readl_poll_timeout_atomic(reg, tmp, tmp & mask, 1, 10 * USEC_PER_= MSEC); + + if (val) + *val =3D tmp; + + return ret; +} =20 int gicv5_irs_of_probe(struct device_node *parent); void gicv5_irs_remove(void); int gicv5_irs_enable(void); +void gicv5_irs_its_probe(void); int gicv5_irs_register_cpu(int cpuid); int gicv5_irs_cpu_to_iaffid(int cpu_id, u16 *iaffid); struct gicv5_irs_chip_data *gicv5_irs_lookup_by_spi_id(u32 spi_id); int gicv5_spi_irq_set_type(struct irq_data *d, unsigned int type); int gicv5_spi_set_type(struct irq_data *d, unsigned int type); int gicv5_irs_iste_alloc(u32 lpi); +void gicv5_irs_syncr(void); + +struct gicv5_its_devtab_cfg { + union { + struct { + __le64 *devtab; + } linear; + struct { + __le64 *l1devtab; + __le64 **l2ptrs; + } l2; + }; + u32 cfgr; +}; + +struct gicv5_its_itt_cfg { + union { + struct { + __le64 *itt; + unsigned int num_ents; + } linear; + struct { + __le64 *l1itt; + __le64 **l2ptrs; + unsigned int num_l1_ents; + u8 l2sz; + } l2; + }; + u8 event_id_bits; + bool l2itt; +}; + +struct gicv5_its_chip_data { + struct list_head entry; + struct xarray its_devices; + struct mutex dev_alloc_lock; + struct fwnode_handle *fwnode; + struct gicv5_its_devtab_cfg devtab_cfgr; + struct irq_domain *domain; + void __iomem *its_base; + phys_addr_t its_trans_phys_base; + u32 flags; +}; + +struct gicv5_its_dev { + struct gicv5_its_chip_data *its_node; + struct gicv5_its_itt_cfg itt_cfg; + unsigned long *event_map; + u32 device_id; + u32 num_events; + u32 num_mapped_events; + bool shared; +}; =20 void gicv5_init_lpis(u32 max); void gicv5_deinit_lpis(void); + +int gicv5_alloc_lpi(void); +void gicv5_free_lpi(u32 lpi); + +void __init gicv5_its_of_probe(struct device_node *parent); #endif --=20 2.48.0 From nobody Sun Feb 8 13:09:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 324632580D1; Thu, 24 Apr 2025 10:27:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490460; cv=none; b=Drzv2ud+8V9kmWzgL1kmkkKP/CV67DJ7wV9KKXmFhoRF+dT3dEeHkPb9gPZk35v5IQHh6GfWVvWGQcM5SiJ5aCE9XSThOK3gvBz1weWPlcq9eXe/LIoC9TmGfQVESYH4IIZDm55wUNvTBnWeIAs2m4LAmQSQE1vrafoM2P1Jpc8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490460; c=relaxed/simple; bh=1GLl3i8svHuLk0FlkroR+rgzR5nzuU5kyjeurr+N8w4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=T3K+9UqcTtoaB/RAC7RBzDKyOwIVMNAlp0OEAV6NUFKOPFEOGv0/qGuO95kR9JrVu8vbmJ2nR016ly4MZexVojlqrCPbtYqUI8bA68AQmjxAKm4wn41Bm+WM8sPIMuGmtQzt4egRjyjJpaxJZ0/M8TRJvZLomenVyLbiLf5RHt8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CuZtpbRf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CuZtpbRf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0B7E3C4CEE4; Thu, 24 Apr 2025 10:27:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745490460; bh=1GLl3i8svHuLk0FlkroR+rgzR5nzuU5kyjeurr+N8w4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=CuZtpbRfdLR8ZOmja/d+4ds3Q4eWIUBVzdfCEJLx4nCqCC7ggYTAU2anXtKVvoXha 8jgD3S7szaNZTzQoNZAZOAejEHj9tRB8idr2kdQGvEF1aW3oNxFp5UYgIqzk0mwJ8W 4pmbn6NPvl8GlwoE5uGMArQvRrXILq3YSEv5xLH54fcPdzvP2v5i5bjDMXXhFzkzve QRmeZZMxQyC2EHGGuxR515XJxFfh/tgd0rZ5XEDIKV3yXbASGOzEDb1b0CStmoylK7 FZD8kxCTY4o6fvb3ksXS4RO7TKFT331l3xHokbrMODdzfJo0AInaVGw2SBq4eNNEis 69B9HcMcakRPw== From: Lorenzo Pieralisi Date: Thu, 24 Apr 2025 12:25:32 +0200 Subject: [PATCH v2 21/22] irqchip/gic-v5: Add GICv5 IWB support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-gicv5-host-v2-21-545edcaf012b@kernel.org> References: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> In-Reply-To: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.14.2 The GICv5 architecture implements the Interrupt Wire Bridge (IWB) in order to support wired interrupts that cannot be connected directly to an IRS and instead uses the ITS to translate a wire event into an IRQ signal. An IWB is a special ITS device with its own deviceID; upon probe, an IWB calls into the ITS driver to allocate DT/ITT tables for its events (ie wires). An IWB is always associated with a single ITS in the system. An IWB is connected to an ITS and it has its own deviceID for all interrupt wires that it manages; the IWB input wire number is exposed to the ITS as an eventID. This eventID is not programmable and therefore requires special handling in the ITS driver. Add an IWB driver in order to: - Probe IWBs in the system and allocate ITS tables - Manage IWB IRQ domains - Handle IWB input wires state (enable/disable) - Add the required IWB IRQchip representation - Handle firmware representation to Linux IRQ translation Co-developed-by: Sascha Bischoff Signed-off-by: Sascha Bischoff Co-developed-by: Timothy Hayes Signed-off-by: Timothy Hayes Signed-off-by: Lorenzo Pieralisi Cc: Thomas Gleixner Cc: Marc Zyngier --- drivers/irqchip/Makefile | 2 +- drivers/irqchip/irq-gic-v5-its.c | 68 ++++++-- drivers/irqchip/irq-gic-v5-iwb.c | 356 +++++++++++++++++++++++++++++++++++= ++++ drivers/irqchip/irq-gic-v5.c | 2 + drivers/irqchip/irq-gic-v5.h | 28 +++ 5 files changed, 437 insertions(+), 19 deletions(-) diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 4280395e3bdff7858102f0b4eaaea1121cace52f..7bfb2369fbe494a64b72308d95a= e33de93c6b8c6 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -37,7 +37,7 @@ obj-$(CONFIG_ARM_GIC_V3_ITS) +=3D irq-gic-v3-its.o irq-g= ic-v4.o obj-$(CONFIG_ARM_GIC_V3_ITS_FSL_MC) +=3D irq-gic-v3-its-fsl-mc-msi.o obj-$(CONFIG_PARTITION_PERCPU) +=3D irq-partition-percpu.o obj-$(CONFIG_ARM_GIC_V5) +=3D irq-gic-v5.o irq-gic-v5-irs.o -obj-$(CONFIG_ARM_GIC_V5_ITS) +=3D irq-gic-v5-its.o +obj-$(CONFIG_ARM_GIC_V5_ITS) +=3D irq-gic-v5-its.o irq-gic-v5-iwb.o obj-$(CONFIG_HISILICON_IRQ_MBIGEN) +=3D irq-mbigen.o obj-$(CONFIG_ARM_NVIC) +=3D irq-nvic.o obj-$(CONFIG_ARM_VIC) +=3D irq-vic.o diff --git a/drivers/irqchip/irq-gic-v5-its.c b/drivers/irqchip/irq-gic-v5-= its.c index da349b4709cc5ec8978859237838f039389ca4a1..b5eb4dbfe2296dc6620889eb929= 1b542cae4aeb6 100644 --- a/drivers/irqchip/irq-gic-v5-its.c +++ b/drivers/irqchip/irq-gic-v5-its.c @@ -786,9 +786,8 @@ static struct gicv5_its_dev *gicv5_its_find_device(stru= ct gicv5_its_chip_data *i return dev ? dev : ERR_PTR(-ENODEV); } =20 -static struct gicv5_its_dev *gicv5_its_alloc_device( - struct gicv5_its_chip_data *its, int nvec, - u32 dev_id) +struct gicv5_its_dev *gicv5_its_alloc_device(struct gicv5_its_chip_data *i= ts, + int nvec, u32 dev_id, bool is_iwb) { struct gicv5_its_dev *its_dev; int ret; @@ -815,6 +814,7 @@ static struct gicv5_its_dev *gicv5_its_alloc_device( its_dev->device_id =3D dev_id; its_dev->num_events =3D nvec; its_dev->num_mapped_events =3D 0; + its_dev->is_iwb =3D is_iwb; =20 ret =3D gicv5_its_device_register(its, its_dev); if (ret) { @@ -827,9 +827,11 @@ static struct gicv5_its_dev *gicv5_its_alloc_device( =20 /* * This is the first time we have seen this device. Hence, it is not - * shared. + * shared, unless it is an IWB that is a shared ITS device by + * definition, its eventids are hardcoded and never change - we allocate + * it once for all and never free it. */ - its_dev->shared =3D false; + its_dev->shared =3D is_iwb; =20 its_dev->its_node =3D its; =20 @@ -859,7 +861,7 @@ static int gicv5_its_msi_prepare(struct irq_domain *dom= ain, struct device *dev, =20 guard(mutex)(&its->dev_alloc_lock); =20 - its_dev =3D gicv5_its_alloc_device(its, nvec, dev_id); + its_dev =3D gicv5_its_alloc_device(its, nvec, dev_id, false); if (IS_ERR(its_dev)) return PTR_ERR(its_dev); =20 @@ -937,28 +939,55 @@ static void gicv5_its_free_event(struct gicv5_its_dev= *its_dev, u16 event_id) } =20 static int gicv5_its_alloc_eventid(struct gicv5_its_dev *its_dev, + msi_alloc_info_t *info, unsigned int nr_irqs, u32 *eventid) { - int ret; + int event_id_base; =20 - ret =3D bitmap_find_free_region(its_dev->event_map, - its_dev->num_events, - get_count_order(nr_irqs)); + if (!its_dev->is_iwb) { =20 - if (ret < 0) - return ret; + event_id_base =3D bitmap_find_free_region( + its_dev->event_map, its_dev->num_events, + get_count_order(nr_irqs)); + if (event_id_base < 0) + return event_id_base; + } else { + /* + * We want to have a fixed EventID mapped for the IWB. + */ + if (WARN(nr_irqs !=3D 1, "IWB requesting nr_irqs !=3D 1\n")) + return -EINVAL; =20 - *eventid =3D ret; + event_id_base =3D info->scratchpad[1].ul; + + if (event_id_base >=3D its_dev->num_events) { + pr_err("EventID ouside of ITT range; cannot allocate an ITT entry!\n"); + + return -EINVAL; + } + + if (test_and_set_bit(event_id_base, its_dev->event_map)) { + pr_warn("Can't reserve event_id bitmap\n"); + return -EINVAL; + + } + } + + *eventid =3D event_id_base; =20 return 0; + } =20 static void gicv5_its_free_eventid(struct gicv5_its_dev *its_dev, u32 event_id_base, unsigned int nr_irqs) { - bitmap_release_region(its_dev->event_map, event_id_base, + if (!its_dev->is_iwb) + bitmap_release_region(its_dev->event_map, event_id_base, get_count_order(nr_irqs)); + else + clear_bit(event_id_base, its_dev->event_map); } =20 static int gicv5_its_irq_domain_alloc(struct irq_domain *domain, unsigned = int virq, @@ -986,7 +1015,7 @@ static int gicv5_its_irq_domain_alloc(struct irq_domai= n *domain, unsigned int vi return PTR_ERR(its_dev); } =20 - ret =3D gicv5_its_alloc_eventid(its_dev, nr_irqs, &event_id_base); + ret =3D gicv5_its_alloc_eventid(its_dev, info, nr_irqs, &event_id_base); if (ret) { mutex_unlock(&its->dev_alloc_lock); return ret; @@ -994,9 +1023,12 @@ static int gicv5_its_irq_domain_alloc(struct irq_doma= in *domain, unsigned int vi =20 mutex_unlock(&its->dev_alloc_lock); =20 - ret =3D iommu_dma_prepare_msi(info->desc, its->its_trans_phys_base); - if (ret) - goto out_eventid; + /* IWBs are never upstream an IOMMU */ + if (!its_dev->is_iwb) { + ret =3D iommu_dma_prepare_msi(info->desc, its->its_trans_phys_base); + if (ret) + goto out_eventid; + } =20 for (i =3D 0; i < nr_irqs; i++) { lpi =3D gicv5_alloc_lpi(); diff --git a/drivers/irqchip/irq-gic-v5-iwb.c b/drivers/irqchip/irq-gic-v5-= iwb.c new file mode 100644 index 0000000000000000000000000000000000000000..a0ff1467f15e6f5cf969ada3309= 775fdc6a67d2b --- /dev/null +++ b/drivers/irqchip/irq-gic-v5-iwb.c @@ -0,0 +1,356 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024-2025 ARM Limited, All Rights Reserved. + */ +#define pr_fmt(fmt) "GICv5 IWB: " fmt + +#include +#include +#include +#include +#include +#include + +#include "irq-gic-v5.h" + +static u32 iwb_readl_relaxed(struct gicv5_iwb_chip_data *iwb_node, + const u64 reg_offset) +{ + return readl_relaxed(iwb_node->iwb_base + reg_offset); +} + +static void iwb_writel_relaxed(struct gicv5_iwb_chip_data *iwb_node, + const u32 val, const u64 reg_offset) +{ + writel_relaxed(val, iwb_node->iwb_base + reg_offset); +} + +static int gicv5_iwb_wait_for_wenabler(struct gicv5_iwb_chip_data *iwb_nod= e) +{ + int ret; + + ret =3D gicv5_wait_for_op(iwb_node->iwb_base, GICV5_IWB_WENABLE_STATUSR, + GICV5_IWB_WENABLE_STATUSR_IDLE, NULL); + if (unlikely(ret =3D=3D -ETIMEDOUT)) + pr_err_ratelimited("IWB_WENABLE_STATUSR timeout\n"); + + return ret; +} + +static int __gicv5_iwb_set_wire_enable(struct gicv5_iwb_chip_data *iwb_nod= e, + u32 iwb_wire, bool enable) +{ + u32 n =3D iwb_wire / 32; + u8 i =3D iwb_wire % 32; + u32 val; + + if (n >=3D iwb_node->nr_regs) { + pr_err("IWB_WENABLER is invalid for n=3D%u\n", n); + return -EINVAL; + } + + /* + * Enable IWB wire/pin at this point + * Note: This is not the same as enabling the interrupt + */ + val =3D iwb_readl_relaxed(iwb_node, GICV5_IWB_WENABLER + (4 * n)); + if (enable) + val |=3D BIT(i); + else + val &=3D ~BIT(i); + iwb_writel_relaxed(iwb_node, val, GICV5_IWB_WENABLER + (4 * n)); + + return gicv5_iwb_wait_for_wenabler(iwb_node); +} + +static int gicv5_iwb_enable_wire(struct gicv5_iwb_chip_data *iwb_node, + u32 iwb_wire) +{ + return __gicv5_iwb_set_wire_enable(iwb_node, iwb_wire, true); +} + +static int gicv5_iwb_disable_wire(struct gicv5_iwb_chip_data *iwb_node, + u32 iwb_wire) +{ + return __gicv5_iwb_set_wire_enable(iwb_node, iwb_wire, false); +} + +static int gicv5_iwb_set_type(struct irq_data *d, unsigned int type) +{ + struct gicv5_iwb_chip_data *iwb_node =3D irq_data_get_irq_chip_data(d); + u32 iwb_wire, n, wtmr; + u8 i; + + iwb_wire =3D d->hwirq; + + i =3D iwb_wire % 32; + n =3D iwb_wire / 32; + + if (n >=3D iwb_node->nr_regs) { + pr_err_once("reg %u out of range\n", n); + return -EINVAL; + } + + wtmr =3D iwb_readl_relaxed(iwb_node, GICV5_IWB_WTMR + (4 * n)); + + switch (type) { + case IRQ_TYPE_LEVEL_HIGH: + case IRQ_TYPE_LEVEL_LOW: + wtmr |=3D BIT(i); + break; + case IRQ_TYPE_EDGE_RISING: + case IRQ_TYPE_EDGE_FALLING: + wtmr &=3D ~BIT(i); + break; + default: + pr_debug("unexpected wire trigger mode"); + return -EINVAL; + } + + iwb_writel_relaxed(iwb_node, wtmr, GICV5_IWB_WTMR + (4 * n)); + + return 0; +} + +static const struct irq_chip gicv5_iwb_chip =3D { + .name =3D "GICv5-IWB", + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_eoi =3D irq_chip_eoi_parent, + .irq_set_type =3D gicv5_iwb_set_type, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D irq_chip_set_parent_state, + .flags =3D IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_MASK_ON_SUSPEND +}; + +static int gicv5_iwb_irq_domain_translate(struct irq_domain *d, + struct irq_fwspec *fwspec, + irq_hw_number_t *hwirq, + unsigned int *type) +{ + if (!is_of_node(fwspec->fwnode)) + return -EINVAL; + + if (fwspec->param_count < 2) + return -EINVAL; + + /* + * param[0] is be the wire + * param[1] is the interrupt type + */ + *hwirq =3D fwspec->param[0]; + *type =3D fwspec->param[1] & IRQ_TYPE_SENSE_MASK; + + return 0; +} + +static void gicv5_iwb_irq_domain_free(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs) +{ + /* Free the local data, and then go up the hierarchy doing the same */ + struct gicv5_iwb_chip_data *iwb_node =3D domain->host_data; + struct irq_data *data; + + if (WARN_ON_ONCE(nr_irqs !=3D 1)) + return; + + data =3D irq_domain_get_irq_data(domain, virq); + gicv5_iwb_disable_wire(iwb_node, data->hwirq); + + irq_domain_reset_irq_data(data); + + irq_domain_free_irqs_parent(domain, virq, nr_irqs); +} + +/* + * Our parent is the ITS, which expects MSI devices with programmable + * event IDs. IWB event IDs are hardcoded. + * + * Use the msi_alloc_info_t structure to convey both our DeviceID + * (scratchpad[0]), and the wire that we are attempting to map to an LPI in + * the ITT (scratchpad[1]). + */ +static int iwb_alloc_lpi_irq_parent(struct irq_domain *domain, + unsigned int virq, irq_hw_number_t hwirq) +{ + struct gicv5_iwb_chip_data *iwb_node =3D domain->host_data; + msi_alloc_info_t info; + + info.scratchpad[0].ul =3D iwb_node->device_id; + info.scratchpad[1].ul =3D hwirq; + info.hwirq =3D hwirq; + + return irq_domain_alloc_irqs_parent(domain, virq, 1, &info); +} + +static int gicv5_iwb_irq_domain_alloc(struct irq_domain *domain, unsigned = int virq, + unsigned int nr_irqs, void *arg) +{ + struct gicv5_iwb_chip_data *iwb_node; + unsigned int type =3D IRQ_TYPE_NONE; + struct irq_fwspec *fwspec =3D arg; + irq_hw_number_t hwirq; + struct irq_data *irqd; + int ret; + + if (WARN_ON_ONCE(nr_irqs !=3D 1)) + return -EINVAL; + + ret =3D gicv5_iwb_irq_domain_translate(domain, fwspec, &hwirq, &type); + if (ret) + return ret; + + if (iwb_alloc_lpi_irq_parent(domain, virq, hwirq)) + return -EINVAL; + + irqd =3D irq_get_irq_data(virq); + iwb_node =3D domain->host_data; + + gicv5_iwb_enable_wire(iwb_node, hwirq); + + irq_domain_set_info(domain, virq, hwirq, &gicv5_iwb_chip, iwb_node, + handle_fasteoi_irq, NULL, NULL); + irq_set_probe(virq); + irqd_set_single_target(irqd); + + return 0; +} + +static const struct irq_domain_ops gicv5_iwb_irq_domain_ops =3D { + .translate =3D gicv5_iwb_irq_domain_translate, + .alloc =3D gicv5_iwb_irq_domain_alloc, + .free =3D gicv5_iwb_irq_domain_free, +}; + +static struct gicv5_iwb_chip_data * +__init gicv5_iwb_init_bases(void __iomem *iwb_base, + struct fwnode_handle *handle, + struct irq_domain *parent_domain, u32 device_id) +{ + struct gicv5_iwb_chip_data *iwb_node; + struct msi_domain_info *msi_info; + struct gicv5_its_chip_data *its; + struct gicv5_its_dev *its_dev; + u32 nr_wires, idr0, cr0; + int ret; + + msi_info =3D msi_get_domain_info(parent_domain); + its =3D msi_info->data; + if (!its) { + pr_warn("IWB %pOF can't find parent ITS, bailing\n", + to_of_node(handle)); + return ERR_PTR(-ENODEV); + } + + iwb_node =3D kzalloc(sizeof(*iwb_node), GFP_KERNEL); + if (!iwb_node) + return ERR_PTR(-ENOMEM); + + iwb_node->iwb_base =3D iwb_base; + iwb_node->device_id =3D device_id; + + idr0 =3D iwb_readl_relaxed(iwb_node, GICV5_IWB_IDR0); + nr_wires =3D (FIELD_GET(GICV5_IWB_IDR0_IW_RANGE, idr0) + 1) * 32; + + iwb_node->domain =3D irq_domain_create_hierarchy(parent_domain, 0, + nr_wires, handle, &gicv5_iwb_irq_domain_ops, + iwb_node); + irq_domain_update_bus_token(iwb_node->domain, DOMAIN_BUS_WIRED); + + cr0 =3D iwb_readl_relaxed(iwb_node, GICV5_IWB_CR0); + if (!FIELD_GET(GICV5_IWB_CR0_IWBEN, cr0)) { + pr_err("IWB %s must be enabled in firmware\n", + fwnode_get_name(handle)); + ret =3D -EINVAL; + goto out_free; + } + + iwb_node->nr_regs =3D FIELD_GET(GICV5_IWB_IDR0_IW_RANGE, idr0) + 1; + + for (unsigned int n =3D 0; n < iwb_node->nr_regs; n++) + iwb_writel_relaxed(iwb_node, 0, GICV5_IWB_WENABLER + (sizeof(u32) * n)); + + ret =3D gicv5_iwb_wait_for_wenabler(iwb_node); + if (ret) + goto out_free; + + mutex_lock(&its->dev_alloc_lock); + its_dev =3D gicv5_its_alloc_device(its, roundup_pow_of_two(nr_wires), + device_id, true); + mutex_unlock(&its->dev_alloc_lock); + if (IS_ERR(its_dev)) { + ret =3D -ENODEV; + goto out_free; + } + + return iwb_node; +out_free: + irq_domain_remove(iwb_node->domain); + kfree(iwb_node); + + return ERR_PTR(ret); +} + +static int __init gicv5_iwb_of_init(struct device_node *node) +{ + struct gicv5_iwb_chip_data *iwb_node; + struct irq_domain *parent_domain; + struct device_node *parent_its; + struct of_phandle_args args; + void __iomem *iwb_base; + u32 device_id; + int ret; + + iwb_base =3D of_io_request_and_map(node, 0, "IWB"); + if (IS_ERR(iwb_base)) { + pr_err("%pOF: unable to map GICv5 IWB registers\n", node); + return PTR_ERR(iwb_base); + } + + ret =3D of_parse_phandle_with_args(node, "msi-parent", "#msi-cells", 0, + &args); + if (ret) { + pr_err("%pOF: Can't retrieve deviceID\n", node); + goto out_unmap; + } + + parent_its =3D args.np; + parent_domain =3D irq_find_matching_host(parent_its, DOMAIN_BUS_NEXUS); + if (!parent_domain) { + pr_err("Unable to find the parent ITS domain for %pOF!\n", node); + ret =3D -ENXIO; + goto out_put; + } + + device_id =3D args.args[0]; + pr_debug("IWB deviceID: 0x%x\n", device_id); + + iwb_node =3D gicv5_iwb_init_bases(iwb_base, &node->fwnode, parent_domain, + device_id); + if (IS_ERR(iwb_node)) { + ret =3D PTR_ERR(iwb_node); + goto out_put; + } + + return 0; +out_put: + of_node_put(parent_its); +out_unmap: + iounmap(iwb_base); + return ret; +} + +void __init gicv5_iwb_of_probe(void) +{ + struct device_node *np; + int ret; + + for_each_compatible_node(np, NULL, "arm,gic-v5-iwb") { + ret =3D gicv5_iwb_of_init(np); + if (ret) + pr_err("Failed to init IWB %s\n", np->full_name); + } +} diff --git a/drivers/irqchip/irq-gic-v5.c b/drivers/irqchip/irq-gic-v5.c index e483d0774936035b5cf2407da9a65d776bad3138..0eaf1f40073d2659b60b3fa5ac0= 6c66a9e4f2e2f 100644 --- a/drivers/irqchip/irq-gic-v5.c +++ b/drivers/irqchip/irq-gic-v5.c @@ -1047,6 +1047,8 @@ static int __init gicv5_of_init(struct device_node *n= ode, =20 gicv5_irs_its_probe(); =20 + gicv5_iwb_of_probe(); + return 0; out_int: gicv5_cpu_disable_interrupts(); diff --git a/drivers/irqchip/irq-gic-v5.h b/drivers/irqchip/irq-gic-v5.h index f5a453599493020b36d9c7f18c08171c51ba8669..a71504cbee2d08c8ff54fb409be= 72373945bc65a 100644 --- a/drivers/irqchip/irq-gic-v5.h +++ b/drivers/irqchip/irq-gic-v5.h @@ -238,6 +238,20 @@ #define GICV5_ITS_HWIRQ_DEVICE_ID GENMASK_ULL(31, 0) #define GICV5_ITS_HWIRQ_EVENT_ID GENMASK_ULL(63, 32) =20 +#define GICV5_IWB_IDR0 0x0000 +#define GICV5_IWB_CR0 0x0080 +#define GICV5_IWB_WENABLE_STATUSR 0x00c0 +#define GICV5_IWB_WENABLER 0x2000 +#define GICV5_IWB_WTMR 0x4000 + +#define GICV5_IWB_IDR0_INT_DOMS GENMASK(14, 11) +#define GICV5_IWB_IDR0_IW_RANGE GENMASK(10, 0) + +#define GICV5_IWB_CR0_IDLE BIT(1) +#define GICV5_IWB_CR0_IWBEN BIT(0) + +#define GICV5_IWB_WENABLE_STATUSR_IDLE BIT(0) + struct gicv5_chip_data { struct fwnode_handle *fwnode; struct irq_domain *ppi_domain; @@ -348,6 +362,7 @@ struct gicv5_its_dev { u32 num_events; u32 num_mapped_events; bool shared; + bool is_iwb; }; =20 void gicv5_init_lpis(u32 max); @@ -357,4 +372,17 @@ int gicv5_alloc_lpi(void); void gicv5_free_lpi(u32 lpi); =20 void __init gicv5_its_of_probe(struct device_node *parent); +struct gicv5_its_dev *gicv5_its_alloc_device(struct gicv5_its_chip_data *i= ts, + int nvec, u32 dev_id, bool is_iwb); + +struct gicv5_iwb_chip_data { + void __iomem *iwb_base; + struct irq_domain *domain; + u64 flags; + u32 device_id; + u16 nr_regs; +}; + +void gicv5_iwb_of_probe(void); + #endif --=20 2.48.0 From nobody Sun Feb 8 13:09:10 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E6B3230272; Thu, 24 Apr 2025 10:27:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490466; cv=none; b=b0yUkTUMkSZfnv1Nw0T0iXRgwYhVlP/9YrpJwqirSGOXHL9DVEJxUzFa6K4JYZt779niayKXswlj31B2uA5ujAv4rDKX4RXEfHXbPOCVy5a+l4SzoYNFx9ZnkqjZTKZpWMVQnMFnXmKxjtmBONdZGjpDiyOZCNrCWEuCcxSA1VQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745490466; c=relaxed/simple; bh=Dhr0rsx9WpeMa8aspdbgl7YO+d4d6KcEE2+waQCoYbI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FQeLWXEI2BOc/yVLLwFJa4JAy747bYyb061I5+7AxyYecsZXkwsMoOQXCT01dIIdvIFM6J9Ks7tjrGd1t0Q4c2ckpG/zIf/iZUWrEhrG5SsdI7L+j7p06gPQgnrk/gm2JMBn0GWTY3N5sLrH8RN+NeK2OblZxprNo1LQUvvSoTY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Zbx8c1dL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Zbx8c1dL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B12B9C4CEE3; Thu, 24 Apr 2025 10:27:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745490465; bh=Dhr0rsx9WpeMa8aspdbgl7YO+d4d6KcEE2+waQCoYbI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Zbx8c1dLijPcaODhyVkHFGx5r2ZphraIAZSwlIYG86gb3W26LbpP4Fji8vaGl5y2K MZUj30RABRGse5hQ8qy57swFn1Ipysp2hqD9ujgEc/sCCdXZRUYEZ5f1UzC3ALXkod iZIE8+yDBCE+orVCF0tC0FMM5SuhWYnCr6CAQ1xU2iUK+t38VSe/XeKR1IDpHoSouL elD14Cb89Lw5VWoe6BkQSZOZBl9t+OOeRjfBKiy5PQkeWZoXRVcLh4gp70sDvlZi1V OYMnA71A/D+0tz+iTG1TVlCjAHhDzkcmF+3dwHyu6JgYWDIzCIcKfXEUds/073r5Rp P9X/p9JsBp8BQ== From: Lorenzo Pieralisi Date: Thu, 24 Apr 2025 12:25:33 +0200 Subject: [PATCH v2 22/22] arm64: Kconfig: Enable GICv5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-gicv5-host-v2-22-545edcaf012b@kernel.org> References: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> In-Reply-To: <20250424-gicv5-host-v2-0-545edcaf012b@kernel.org> To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Lorenzo Pieralisi X-Mailer: b4 0.14.2 Enable GICv5 driver code for the ARM64 architecture. Signed-off-by: Lorenzo Pieralisi Cc: Will Deacon Cc: Catalin Marinas Cc: Marc Zyngier --- arch/arm64/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index a182295e6f08bfa0f3e6f630dc4adfe797a4d273..f1b3c695b376717979ae8648652= 38ae12ad65ca2 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -128,6 +128,7 @@ config ARM64 select ARM_GIC_V2M if PCI select ARM_GIC_V3 select ARM_GIC_V3_ITS if PCI + select ARM_GIC_V5 select ARM_PSCI_FW select BUILDTIME_TABLE_SORT select CLONE_BACKWARDS --=20 2.48.0