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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-317d1b9a304sm1820461fa.99.2025.04.24.02.31.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Apr 2025 02:31:20 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 24 Apr 2025 12:30:35 +0300 Subject: [PATCH v3 31/33] drm/msm/dpu: get rid of DPU_DSC_NATIVE_42x_EN Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-dpu-drop-features-v3-31-cdaca81d356f@oss.qualcomm.com> References: <20250424-dpu-drop-features-v3-0-cdaca81d356f@oss.qualcomm.com> In-Reply-To: <20250424-dpu-drop-features-v3-0-cdaca81d356f@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=9210; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=19/sQF6QrfTaWj5BCZQZWlAaWBLn1zVu4zT1/dnr23I=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoCgSw7G/2CNYPilA2fKV1pmxvQuRa7WrmhzM0c yE6bqq3t3KJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaAoEsAAKCRCLPIo+Aiko 1XLFB/wIdQZk3lL7rB0Wx4ENOW3+dXsazKWrZkSr1FIeLdxk1x4P2RTgB8no0YPaxcFNkrgIjjr N5krjarM1WTgL1Y7fme8xSxgeqRfnowkSgNpzxFoYbj0oFn7mMR2T0G1xTsxBAqomWA5u906LBq UEu98A8KH+ycuPnUC8EPjtbzlCaTI6nodg7UO0mVEGmtUhTDFYrqjRzu7C6t3LVSfsbUURQUVy9 2crJhvSPUMWB2wtqrlHOlwpjq4/8+m4NjYDVdIF4g+Ii0aI9Wit5Y/kL+lU6LsBfyJe2ESkioai 07bJEs3GpZzeb/svulULGtZodpjaZ0oi40yun+QinbpJsvWp X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: 72-Cr0TEulOVAG_kTYCn3bwzDYE6oaK5 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI0MDA2MiBTYWx0ZWRfXxJvOg8drsTGT xhi5DcK6IMaF5x0mF0p73FeYXjXV5b4Lb37Po49bIVkQd53eOOeloe9VoGAK+8DqdjvcuHKzggk abo7GmO16JRyZSsxEyWMb4kI02O7lOGwj9daZzzE/aoRMpn+chQcNoL6cQUwuh+mpom4WstEEyb pxn4Tk8bXFUJbm4QbfYlyzZWXDGzThEwZPNoQLfmr9Pgo75j+dpGGwRnFXg4rYpZNtR7Fnc1VYT qk6hUzu66wuyRrfAqtdZ8sOaEh3fYBGuEE4cGHjItFwZmF5EBhFQUATjJOP/DGIcyrt7yExbZjX 7HWwy1Q0vBnrajFTs7vhQVqScA2uq33qYX802kco1TA3mjRYvCnE52ap+ruqVCoxY/zknHQf5cr d0/uk81TuZQVLQ/EWTUyjnx11lm7Lm+lIVkdAOaWZFPhujds1HrZhE4yO+y6DG+5ui3YiBK1 X-Authority-Analysis: v=2.4 cv=ELgG00ZC c=1 sm=1 tr=0 ts=680a04ec cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=KKAkSRfTAAAA:8 a=bDEOCHsu97kwrKHOfzcA:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: 72-Cr0TEulOVAG_kTYCn3bwzDYE6oaK5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.680,FMLib:17.12.80.40 definitions=2025-04-24_04,2025-04-22_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 malwarescore=0 clxscore=1015 bulkscore=0 phishscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504240062 From: Dmitry Baryshkov Continue cleanup of the feature flags and replace the last remaining LM feature with a bitfield flag, simplifying corresponding data structures and access. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 12 ++---------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c | 2 +- 10 files changed, 20 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index 2007aedc0526854d3d8c4eface5b507dc5c62c58..b8cac2dbec3c963b1a15337c648= 10a23ac6afc9e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -289,22 +289,22 @@ static const struct dpu_dsc_cfg sm8650_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_2_0", .id =3D DSC_4, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 2c59f0b77a75880df18900fa406f1ea7006927a1..26266d36520e7499feb26da0f33= 51405bbd2f87a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -274,12 +274,12 @@ static const struct dpu_dsc_cfg sm8350_dsc[] =3D { }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index cbc7e9081288fb8125438ad1cc0016042bf70661..3881dc839db71dd798863067a84= 69cdf3045719c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -150,7 +150,7 @@ static const struct dpu_dsc_cfg sc7280_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_0, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 0238eb019d98ad5599cc301e47bda43de762b24d..f9c572be7fea9660d03284d8150= 67a17ac4abe4a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -273,12 +273,12 @@ static const struct dpu_dsc_cfg sc8280xp_dsc[] =3D { }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_2_0", .id =3D DSC_4, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 3b2d99de20621a5c47a31212d7fb236e0b784d0a..08d5273554500a00a55adbe144b= 50fb4f8296ce7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -287,12 +287,12 @@ static const struct dpu_dsc_cfg sm8450_dsc[] =3D { }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index 14a1781c19bd8060d338ea52684f756258526996..d4eaf89821722bfccefe930e834= cbd83d52123e0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -286,12 +286,12 @@ static const struct dpu_dsc_cfg sa8775p_dsc[] =3D { }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_2_0", .id =3D DSC_4, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index f6893c7ea13bc0ac84b46d50a132e18e1c575a3d..83dce1aef9d991afb7f30f75724= a822854be3e78 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -283,12 +283,12 @@ static const struct dpu_dsc_cfg sm8550_dsc[] =3D { }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index f2a09026abf324a3c66c17264c8a5d8f2d75a580..2938ff15299ecc5002aa1bffd02= 292212fe51f03 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -283,12 +283,12 @@ static const struct dpu_dsc_cfg x1e80100_dsc[] =3D { }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 51b330f37c901b99c7db640a0b77149c7ac8cdd7..0f78958ac4476de414d07b727c0= 8feec1c2e9f44 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -128,16 +128,6 @@ enum { DPU_VBIF_MAX }; =20 -/** - * DSC sub-blocks/features - * @DPU_DSC_NATIVE_42x_EN Supports NATIVE_422_EN and NATIVE_420_EN enc= oding - * @DPU_DSC_MAX - */ -enum { - DPU_DSC_NATIVE_42x_EN =3D 0x1, - DPU_DSC_MAX -}; - /** * MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU * @name: string name for debug purposes @@ -474,10 +464,12 @@ struct dpu_merge_3d_cfg { * @len: length of hardware block * @features bit mask identifying sub-blocks/features * @sblk: sub-blocks information + * @have_native_42x: Supports NATIVE_422 and NATIVE_420 encoding */ struct dpu_dsc_cfg { DPU_HW_BLK_INFO; const struct dpu_dsc_sub_blks *sblk; + unsigned long have_native_42x : 1; }; =20 /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_dsc_1_2.c index b9c433567262a954b7f02233f6670ee6a8476846..42b4a5dbc2442ae0f2adab80a5a= 3df96b35e62b0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c @@ -62,7 +62,7 @@ static int _dsc_calc_output_buf_max_addr(struct dpu_hw_ds= c *hw_dsc, int num_soft { int max_addr =3D 2400 / num_softslice; =20 - if (hw_dsc->caps->features & BIT(DPU_DSC_NATIVE_42x_EN)) + if (hw_dsc->caps->have_native_42x) max_addr /=3D 2; =20 return max_addr - 1; --=20 2.39.5