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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-317d1b9a304sm1820461fa.99.2025.04.24.02.30.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Apr 2025 02:30:29 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 24 Apr 2025 12:30:07 +0300 Subject: [PATCH v3 03/33] drm/msm/dpu: inline _setup_ctl_ops() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-dpu-drop-features-v3-3-cdaca81d356f@oss.qualcomm.com> References: <20250424-dpu-drop-features-v3-0-cdaca81d356f@oss.qualcomm.com> In-Reply-To: <20250424-dpu-drop-features-v3-0-cdaca81d356f@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5798; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=6nM57vgHQs62/wjwRtInuGG9vKrODBr++a+KVt2bcP8=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoCgSqaDbO1cyuYOI8GY2KGOace+EMYeHMZnN4M 8YTpevhqVKJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaAoEqgAKCRCLPIo+Aiko 1ZzKCACc/Fqq3vdDRKnSwfbFcgQLxFyD9c/N04fCkEkisVRf1/kEa4lDji6r27tOe0LWjEAj7eG P+VqwUVMg9mNZmvpeWfRfnYcX60FxVk6WyiAocC3uh+WQco8rtSBtHALHqz4g/w1UKYsu+QLtXE LxQbEPx+5PJ+MOTz9XrcX7S1lp7PvafCYFDWW7DxJNl9hOxwehH3/0fVR+BLbrBb2g3dRAVHHAJ w+Uk5G9fN/NtZATLDFOzJ3+4HxVD15GSqCY1YmhXeEx5feUZSUKYF+GKYHA1r0aLKrTBtzaDYU7 SMzVcqzF+eX7lrmMR6Flji9l2BH4LBken36gXJqA0pd3aonX X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: _sIIIepx7x3myGTssBVPiNlXPBW0G4TA X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI0MDA2MiBTYWx0ZWRfX/eceCr9gEacg AbeGYy2Qn5K8oWrSAOe5r7AIOCaj0DwqEmZIOdI7j+9gFb9fG+SKVQoFyUSrnPE7gQTueglsbry 4hoTimcAcPcwg/DKi5Wm/6KLCpYJ3PhE/XF9Y/gWJi7+u4PIAPzubyeW4y9RG5rKJj7zTcptKSq sXjJn87E1OIp2JG7RP4OT+txkUlDmOXfA9jmpDGCt1kflJNhTMT+ZNv9h5sFZvK+vsK/w302aMh SoAsv7Vxlb2HqqepesXC/OH7niS/4G6xjpjs00Dff2o/00UVQa8YtEnptl5zMSNTuewuw5x9mkL +J01I/rmVV48legj5QQNcdE6xWinwUryQRB3ef00R1l7yn6jRdmdeVzN/iz+4u0KzAgEmw9Da0s lSLCMwPDvYYYt42EnCtaZ0YiUVFxAwX52AdnWuFqrnule++SAc4WVv2xnpPgvwBFffRgSQKq X-Authority-Analysis: v=2.4 cv=ELgG00ZC c=1 sm=1 tr=0 ts=680a04b7 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=KKAkSRfTAAAA:8 a=RpF703knbOfOEe3tTfUA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: _sIIIepx7x3myGTssBVPiNlXPBW0G4TA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.680,FMLib:17.12.80.40 definitions=2025-04-24_04,2025-04-22_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 malwarescore=0 clxscore=1015 bulkscore=0 phishscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504240062 From: Dmitry Baryshkov Inline the _setup_ctl_ops() function, it makes it easier to handle different conditions involving CTL configuration. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 98 ++++++++++++++------------= ---- 1 file changed, 47 insertions(+), 51 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.c index 411a7cf088eb72f856940c09b0af9e108ccade4b..466bfee3db52d980877a5cdc4ee= b739cae250afc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -714,56 +714,6 @@ static void dpu_hw_ctl_set_fetch_pipe_active(struct dp= u_hw_ctl *ctx, DPU_REG_WRITE(&ctx->hw, CTL_FETCH_PIPE_ACTIVE, val); } =20 -static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, - unsigned long cap) -{ - if (cap & BIT(DPU_CTL_ACTIVE_CFG)) { - ops->trigger_flush =3D dpu_hw_ctl_trigger_flush_v1; - ops->setup_intf_cfg =3D dpu_hw_ctl_intf_cfg_v1; - ops->reset_intf_cfg =3D dpu_hw_ctl_reset_intf_cfg_v1; - ops->update_pending_flush_intf =3D - dpu_hw_ctl_update_pending_flush_intf_v1; - - ops->update_pending_flush_periph =3D - dpu_hw_ctl_update_pending_flush_periph_v1; - - ops->update_pending_flush_merge_3d =3D - dpu_hw_ctl_update_pending_flush_merge_3d_v1; - ops->update_pending_flush_wb =3D dpu_hw_ctl_update_pending_flush_wb_v1; - ops->update_pending_flush_cwb =3D dpu_hw_ctl_update_pending_flush_cwb_v1; - ops->update_pending_flush_dsc =3D - dpu_hw_ctl_update_pending_flush_dsc_v1; - ops->update_pending_flush_cdm =3D dpu_hw_ctl_update_pending_flush_cdm_v1; - } else { - ops->trigger_flush =3D dpu_hw_ctl_trigger_flush; - ops->setup_intf_cfg =3D dpu_hw_ctl_intf_cfg; - ops->update_pending_flush_intf =3D - dpu_hw_ctl_update_pending_flush_intf; - ops->update_pending_flush_wb =3D dpu_hw_ctl_update_pending_flush_wb; - ops->update_pending_flush_cdm =3D dpu_hw_ctl_update_pending_flush_cdm; - } - ops->clear_pending_flush =3D dpu_hw_ctl_clear_pending_flush; - ops->update_pending_flush =3D dpu_hw_ctl_update_pending_flush; - ops->get_pending_flush =3D dpu_hw_ctl_get_pending_flush; - ops->get_flush_register =3D dpu_hw_ctl_get_flush_register; - ops->trigger_start =3D dpu_hw_ctl_trigger_start; - ops->is_started =3D dpu_hw_ctl_is_started; - ops->trigger_pending =3D dpu_hw_ctl_trigger_pending; - ops->reset =3D dpu_hw_ctl_reset_control; - ops->wait_reset_status =3D dpu_hw_ctl_wait_reset_status; - ops->clear_all_blendstages =3D dpu_hw_ctl_clear_all_blendstages; - ops->setup_blendstage =3D dpu_hw_ctl_setup_blendstage; - ops->update_pending_flush_sspp =3D dpu_hw_ctl_update_pending_flush_sspp; - ops->update_pending_flush_mixer =3D dpu_hw_ctl_update_pending_flush_mixer; - if (cap & BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) - ops->update_pending_flush_dspp =3D dpu_hw_ctl_update_pending_flush_dspp_= sub_blocks; - else - ops->update_pending_flush_dspp =3D dpu_hw_ctl_update_pending_flush_dspp; - - if (cap & BIT(DPU_CTL_FETCH_ACTIVE)) - ops->set_active_pipes =3D dpu_hw_ctl_set_fetch_pipe_active; -}; - /** * dpu_hw_ctl_init() - Initializes the ctl_path hw driver object. * Should be called before accessing any ctl_path register. @@ -789,7 +739,53 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *= dev, c->hw.log_mask =3D DPU_DBG_MASK_CTL; =20 c->caps =3D cfg; - _setup_ctl_ops(&c->ops, c->caps->features); + + if (c->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) { + c->ops.trigger_flush =3D dpu_hw_ctl_trigger_flush_v1; + c->ops.setup_intf_cfg =3D dpu_hw_ctl_intf_cfg_v1; + c->ops.reset_intf_cfg =3D dpu_hw_ctl_reset_intf_cfg_v1; + c->ops.update_pending_flush_intf =3D + dpu_hw_ctl_update_pending_flush_intf_v1; + + c->ops.update_pending_flush_periph =3D + dpu_hw_ctl_update_pending_flush_periph_v1; + + c->ops.update_pending_flush_merge_3d =3D + dpu_hw_ctl_update_pending_flush_merge_3d_v1; + c->ops.update_pending_flush_wb =3D dpu_hw_ctl_update_pending_flush_wb_v1; + c->ops.update_pending_flush_cwb =3D dpu_hw_ctl_update_pending_flush_cwb_= v1; + c->ops.update_pending_flush_dsc =3D + dpu_hw_ctl_update_pending_flush_dsc_v1; + c->ops.update_pending_flush_cdm =3D dpu_hw_ctl_update_pending_flush_cdm_= v1; + } else { + c->ops.trigger_flush =3D dpu_hw_ctl_trigger_flush; + c->ops.setup_intf_cfg =3D dpu_hw_ctl_intf_cfg; + c->ops.update_pending_flush_intf =3D + dpu_hw_ctl_update_pending_flush_intf; + c->ops.update_pending_flush_wb =3D dpu_hw_ctl_update_pending_flush_wb; + c->ops.update_pending_flush_cdm =3D dpu_hw_ctl_update_pending_flush_cdm; + } + c->ops.clear_pending_flush =3D dpu_hw_ctl_clear_pending_flush; + c->ops.update_pending_flush =3D dpu_hw_ctl_update_pending_flush; + c->ops.get_pending_flush =3D dpu_hw_ctl_get_pending_flush; + c->ops.get_flush_register =3D dpu_hw_ctl_get_flush_register; + c->ops.trigger_start =3D dpu_hw_ctl_trigger_start; + c->ops.is_started =3D dpu_hw_ctl_is_started; + c->ops.trigger_pending =3D dpu_hw_ctl_trigger_pending; + c->ops.reset =3D dpu_hw_ctl_reset_control; + c->ops.wait_reset_status =3D dpu_hw_ctl_wait_reset_status; + c->ops.clear_all_blendstages =3D dpu_hw_ctl_clear_all_blendstages; + c->ops.setup_blendstage =3D dpu_hw_ctl_setup_blendstage; + c->ops.update_pending_flush_sspp =3D dpu_hw_ctl_update_pending_flush_sspp; + c->ops.update_pending_flush_mixer =3D dpu_hw_ctl_update_pending_flush_mix= er; + if (c->caps->features & BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) + c->ops.update_pending_flush_dspp =3D dpu_hw_ctl_update_pending_flush_dsp= p_sub_blocks; + else + c->ops.update_pending_flush_dspp =3D dpu_hw_ctl_update_pending_flush_dsp= p; + + if (c->caps->features & BIT(DPU_CTL_FETCH_ACTIVE)) + c->ops.set_active_pipes =3D dpu_hw_ctl_set_fetch_pipe_active; + c->idx =3D cfg->id; c->mixer_count =3D mixer_count; c->mixer_hw_caps =3D mixer; --=20 2.39.5