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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-317d1b9a304sm1820461fa.99.2025.04.24.02.31.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Apr 2025 02:31:05 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 24 Apr 2025 12:30:27 +0300 Subject: [PATCH v3 23/33] drm/msm/dpu: get rid of DPU_DSC_HW_REV_1_2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-dpu-drop-features-v3-23-cdaca81d356f@oss.qualcomm.com> References: <20250424-dpu-drop-features-v3-0-cdaca81d356f@oss.qualcomm.com> In-Reply-To: <20250424-dpu-drop-features-v3-0-cdaca81d356f@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=12855; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=Q3MTIf4rQy+am/uHf/BMkZYmbIwxtrhN/RYvyuNUjQI=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoCgSv7xfDVWi92hHXZlm3iZWDhXKcseAs1FBz3 InjFsxQLMiJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaAoErwAKCRCLPIo+Aiko 1b4XB/0VsYnB5FTAl0bgYt8XOKDghnKAsAi6wX55QnBqun1a8IhFq6MH+KuZKVoZKugcthkPYjY enBv0frQ16euveh70KD31GHNYu6U9D7fNOmCQuUKUkaDlzjFarNbd626pvbDa+NNF0JokiViPw4 2CpS2nstCH0dh9Z7LZ7hjJ8dDJedXWuytLpN7Y423boSl9XstAbV4YNiTfxI5BsTTHJ3LgulTsX d8uvxl7PBjNEN/c7/5Ab0aoAq5We7CiRlB30w/NmsTdCz8hlgnUzbh2WU0MDu/fUSEhsgjjobi6 bMcAmasfvwiCR5+Q5/X2NtG/gHhlZqna6hhY+HrmqKJM46qZ X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI0MDA2MyBTYWx0ZWRfX7LZm7QzdBK3r KutWk1rOHvWB1OFbOTIaEey7Ikds3fhJJIiSpMQYi5jdlPsZlJSKG0seC9eZjLcBI9nBtyF4xD5 jVjJD7g6WSIgL5o2bgMDsbVwgMYWuzIgT2pN0QxWVw89hg+0+2N9Wwv+tyKzTBNL02h6Q3lmwmd NWUaEXLwi2d3XzgbyY7nIX5LkPGSjPT2IIgqo2vU1icmXXgU4vX/s8RpqEsEQ1bkFzhBvLEv53b qpFbuGO4/tBAVhT1WFkXrvqPCBy2hop+nitXMJBm5jJcr3Np5izF6n00cxXbxTCsjCfyABX3zoy ODHqM30b9xpmfh2ijRxeesP12M1TQ+Db+2ZeC0XVGNsWfwAwdtvNi2COGTK8B4MKDbu6f8ldR/R bE+8uaFRZckjtGgqZxZQhIdjrRjAckq869iLpA0RFRuI+S8sn2MKJgVnx1OPEIgduBK/dnb6 X-Proofpoint-GUID: XaPZ32OiKHSak63OONoaMjHb9NV0TXx5 X-Authority-Analysis: v=2.4 cv=ZuTtK87G c=1 sm=1 tr=0 ts=680a04dc cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=KKAkSRfTAAAA:8 a=C81KZioEkqZAcCmD564A:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: XaPZ32OiKHSak63OONoaMjHb9NV0TXx5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.680,FMLib:17.12.80.40 definitions=2025-04-24_04,2025-04-22_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 impostorscore=0 bulkscore=0 mlxscore=0 adultscore=0 lowpriorityscore=0 mlxlogscore=999 priorityscore=1501 malwarescore=0 suspectscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504240063 From: Dmitry Baryshkov Continue migration to the MDSS-revision based checks and replace DPU_DSC_HW_REV_1_2 feature bit with the core_major_ver >=3D 7 check. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 10 ++++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 6 ++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 8 ++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 6 ++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 8 ++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 6 ++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 6 ++---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +- 11 files changed, 19 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index d64366f608ea673422bbf4e5b6ae7f4ad8570784..5f6b1251f30f3c6dfb20261a0d1= bbf776ed5dd33 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -289,32 +289,30 @@ static const struct dpu_dsc_cfg sm8650_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_2_0", .id =3D DSC_4, .base =3D 0x82000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_2_1", .id =3D DSC_5, .base =3D 0x82000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 62de32268ee5528ff0fb16a3ff7c2baa5ea42466..bb35eea64a5af844965259cd96b= ef10d9955b493 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -266,22 +266,20 @@ static const struct dpu_dsc_cfg sm8350_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 202de6f9b0c65c6f2caa9e9d5232f5b92d8bdf01..d21b2266909050fd20bf55b6fab= e07351e445c5a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -150,7 +150,7 @@ static const struct dpu_dsc_cfg sc7280_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 43916752cfd5836718a3770df4c8767635f77ee9..72110b2a2770435ac886e992b1c= cce280c5ac3db 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -265,32 +265,28 @@ static const struct dpu_dsc_cfg sc8280xp_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_2_0", .id =3D DSC_4, .base =3D 0x82000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_2_1", .id =3D DSC_5, .base =3D 0x82000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index d58d5b7ce79b8c069d111c3c2aa3e9cdb2c1a435..305a798768c60a2ec409c1021a9= 1efc4eccc92fd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -279,22 +279,20 @@ static const struct dpu_dsc_cfg sm8450_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index 064546d4fd4538cd5a6b56fca3ee12d482a7dbb6..67aed1ebc78952c6dfce0cc9f16= 80fa75ec26e13 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -278,32 +278,28 @@ static const struct dpu_dsc_cfg sa8775p_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_2_0", .id =3D DSC_4, .base =3D 0x82000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_2_1", .id =3D DSC_5, .base =3D 0x82000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 959f3e9dbc5455fe53c1bb240b5db57212f2d4eb..b54a208e48a8508c39b4e4e95c9= e26ce28ba7c02 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -275,22 +275,20 @@ static const struct dpu_dsc_cfg sm8550_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index 174cfdfcfdf9860ea86c983c6b6591ba98da5400..da2fdf01a17d29fd9a7ea46890d= b7a33fedee31e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -275,22 +275,20 @@ static const struct dpu_dsc_cfg x1e80100_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 8e6fcb51aad8278eb80570a44a423c2443744c61..ee8dd66a68f421161961495dd68= d39dd4622ecf6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -178,13 +178,11 @@ enum { * DSC sub-blocks/features * @DPU_DSC_OUTPUT_CTRL Configure which PINGPONG block gets * the pixel output from this DSC. - * @DPU_DSC_HW_REV_1_2 DSC block supports DSC 1.1 and 1.2 * @DPU_DSC_NATIVE_42x_EN Supports NATIVE_422_EN and NATIVE_420_EN enc= oding * @DPU_DSC_MAX */ enum { DPU_DSC_OUTPUT_CTRL =3D 0x1, - DPU_DSC_HW_REV_1_2, DPU_DSC_NATIVE_42x_EN, DPU_DSC_MAX }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index f3f84c8c302fb1bfe6e6d70e4110d0b89259e55c..d44461e7e1641b25c5181bf7c0c= 9bbedffcc869d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1043,7 +1043,7 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_stat= e *disp_state, struct msm_k msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len, base, "%s", cat->dsc[i].name); =20 - if (cat->dsc[i].features & BIT(DPU_DSC_HW_REV_1_2)) { + if (cat->mdss_ver->core_major_ver >=3D 7) { struct dpu_dsc_blk enc =3D cat->dsc[i].sblk->enc; struct dpu_dsc_blk ctl =3D cat->dsc[i].sblk->ctl; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.c index 5d55b246b32f0757281d8743ae2d1a23cc6e333d..f917ffb85d2f1b1a0ee826f125d= 02980b7a79052 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -166,7 +166,7 @@ int dpu_rm_init(struct drm_device *dev, struct dpu_hw_dsc *hw; const struct dpu_dsc_cfg *dsc =3D &cat->dsc[i]; =20 - if (test_bit(DPU_DSC_HW_REV_1_2, &dsc->features)) + if (cat->mdss_ver->core_major_ver >=3D 7) hw =3D dpu_hw_dsc_init_1_2(dev, dsc, mmio); else hw =3D dpu_hw_dsc_init(dev, dsc, mmio); --=20 2.39.5