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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-317d1b9a304sm1820461fa.99.2025.04.24.02.30.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Apr 2025 02:30:26 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 24 Apr 2025 12:30:05 +0300 Subject: [PATCH v3 01/33] drm/msm/dpu: stop passing mdss_ver to setup_timing_gen() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-dpu-drop-features-v3-1-cdaca81d356f@oss.qualcomm.com> References: <20250424-dpu-drop-features-v3-0-cdaca81d356f@oss.qualcomm.com> In-Reply-To: <20250424-dpu-drop-features-v3-0-cdaca81d356f@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3649; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=sURLU3QRO4lBSIODQBucrC/9R5zvezCH7Xkam1qgsTU=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoCgSpsfUttjT/E6RZYKlS5nYVZCE+2yoZls12h D4PfcXaHZqJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaAoEqQAKCRCLPIo+Aiko 1bTFB/92pxDvmbvS+yabonuD1bCGKJY1BKkJm6f8na4d/gMftQ1VQUbSnqYCO9cU6vZhMrL+dLZ 0fC1YClRxEtSzSqhFHU2kR6/0CRnRGt9AK40wFlV42PLNkotShDhBLDNMy+j2fmve2qdCeGH4vs nUkgTSxi9weAx9T3ow57fjVNPSx+u2D4sxBZBobPaFPr6Q9d1tLoNx8HFAMihc8GDzNrC6DU8A+ 7z5NF9vPqLCmJo00slWXzHl6cxMfs/qDmHxT9wHNFXVS07DLAK2OgqpglhhmGTtVQg7atcqdeDq oyChjjymCjHzxjJImyQLDrYx46Ny2vdpwjPUUBkXEVZa7yua X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: OG5rrnXBocZqyIIrrx4hsKnkHdxZgQNS X-Proofpoint-ORIG-GUID: OG5rrnXBocZqyIIrrx4hsKnkHdxZgQNS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI0MDA2MyBTYWx0ZWRfX2JB/hXvu39y1 ddlNkZyWmIxQyvLYqsqUCswNphFreh+65yKZ338mst9ZjhZOLAzcH++P1T510ysW5rlXqRS/lrv cHNxdSaaWwDSidiNJC/D0rOtZmmifreMdZ8K4UXr4qtuH28qOUt+4IHm+0RD22qWpo1oVMi90D5 hY2B7qItE34P54/26olDut9Fz1dxvMHcC31TcWfIzYBLBPdwhwuoPrRHRW01hxlv2LcGZVEoWYV p2oi9J3/WwleMxu2yRcZz5cfmgBgHnecFqOlWoD7RYzzPxM4fj78RTAkGcpmFIxUvXMy7N14zpm KHTY+5U78+yb8SC9bnlJUil0Rw24GQL+BTNts2xPD0/FEpSpB4BibjQCJTKtAdFdMY0MKBh5TXy ikVzmt7ONw9FYJpFGy+eIq8lFrGDrbjLlaS42KJpNGy5nWrnb2GTvleSpyfv2OL47bGuL7T/ X-Authority-Analysis: v=2.4 cv=ZpjtK87G c=1 sm=1 tr=0 ts=680a04c1 cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=KKAkSRfTAAAA:8 a=Fc1Z5Xec4v_XsjI5eh8A:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.680,FMLib:17.12.80.40 definitions=2025-04-24_04,2025-04-22_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 clxscore=1015 bulkscore=0 suspectscore=0 mlxlogscore=999 spamscore=0 impostorscore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504240063 From: Dmitry Baryshkov As a preparation to further MDSS-revision cleanups stop passing MDSS revision to the setup_timing_gen() callback. Instead store a pointer to it inside struct dpu_hw_intf and use it diretly. It's not that the MDSS revision can chance between dpu_hw_intf_init() and dpu_encoder_phys_vid_setup_timing_engine(). Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 3 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 7 ++++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 5 +++-- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers= /gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index abd6600046cb3a91bf88ca240fd9b9c306b0ea2e..3e0f1288ad17e19f6d0b7c5dcba= 19d3e5977a461 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -307,8 +307,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine( =20 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf, - &timing_params, fmt, - phys_enc->dpu_kms->catalog->mdss_ver); + &timing_params, fmt); phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); =20 /* setup which pp blk will connect to this intf */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_intf.c index fb1d25baa518057e74fec3406faffd48969d492b..1d56c21ac79095ab515aeb48534= 6e1eb5793c260 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -98,8 +98,7 @@ =20 static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, const struct dpu_hw_intf_timing_params *p, - const struct msm_format *fmt, - const struct dpu_mdss_version *mdss_ver) + const struct msm_format *fmt) { struct dpu_hw_blk_reg_map *c =3D &intf->hw; u32 hsync_period, vsync_period; @@ -180,7 +179,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_= hw_intf *intf, =20 /* TODO: handle DSC+DP case, we only handle DSC+DSI case so far */ if (p->compression_en && !dp_intf && - mdss_ver->core_major_ver >=3D 7) + intf->mdss_ver->core_major_ver >=3D 7) intf_cfg2 |=3D INTF_CFG2_DCE_DATA_COMPRESS; =20 hsync_data_start_x =3D hsync_start_x; @@ -580,6 +579,8 @@ struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device = *dev, c->idx =3D cfg->id; c->cap =3D cfg; =20 + c->mdss_ver =3D mdss_rev; + c->ops.setup_timing_gen =3D dpu_hw_intf_setup_timing_engine; c->ops.setup_prg_fetch =3D dpu_hw_intf_setup_prg_fetch; c->ops.get_status =3D dpu_hw_intf_get_status; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_intf.h index 114be272ac0ae67fe0d4dfc0c117baa4106f77c9..f31067a9aaf1d6b96c771571351= 22e5e8bccb7c4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h @@ -81,8 +81,7 @@ struct dpu_hw_intf_cmd_mode_cfg { struct dpu_hw_intf_ops { void (*setup_timing_gen)(struct dpu_hw_intf *intf, const struct dpu_hw_intf_timing_params *p, - const struct msm_format *fmt, - const struct dpu_mdss_version *mdss_ver); + const struct msm_format *fmt); =20 void (*setup_prg_fetch)(struct dpu_hw_intf *intf, const struct dpu_hw_intf_prog_fetch *fetch); @@ -126,6 +125,8 @@ struct dpu_hw_intf { enum dpu_intf idx; const struct dpu_intf_cfg *cap; =20 + const struct dpu_mdss_version *mdss_ver; + /* ops */ struct dpu_hw_intf_ops ops; }; --=20 2.39.5