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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54e7cb3987csm3852e87.59.2025.04.23.14.11.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Apr 2025 14:11:09 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 24 Apr 2025 00:10:20 +0300 Subject: [PATCH v2 24/33] drm/msm/dpu: get rid of DPU_DSC_OUTPUT_CTRL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-dpu-drop-features-v2-24-0a9a66a7b3a2@oss.qualcomm.com> References: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> In-Reply-To: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8937; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=HOkBs/6zBYjscOwL9t+s9f3+kkK5I+SwIYI8RcLTw34=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoCVctmgVurNwAYEJFpA4Zw9ZG1w4hRQEdFFqVj kg93M3vUnaJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaAlXLQAKCRCLPIo+Aiko 1f1NB/wMU4ysJvf0NiIhGNgq4avl1Ut1itt5HDEzi3JmSh23hMOp1Mi95CcfDn7Y1OW33FPWHdc nx6ddCXDHRKZdlFMiCiGc2VMaYuuoR7/7p2JTBY1gNE1ngmMgtY5ZXjMx4vk8dOUJSfCbo861vD sX9n+BTW9+bdNJ9cWt16iH6PsBwwe5In36Mucg2agXtnd43GeN+hkoNSghw4rG2sOvdRb9NlpQX yQLjmLcTDwbvMNTJOTO5xYSbptk5JkU7/qjtHaOloj2P7fgIjo4ocsC9QMoXWJSbgvBfrFvw3aw xq2aPY0IBBoUBGlJR40V7uY/kkIP0dK1IMlqQthz/WkiczpV X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: gJ3DsRLb_MqqPXq_I1VQWTTR7P3zsH8j X-Proofpoint-ORIG-GUID: gJ3DsRLb_MqqPXq_I1VQWTTR7P3zsH8j X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDIzMDE0NCBTYWx0ZWRfX9mjwEh4mzeAh VgdD1JxflG/wwl3Ia7wiDOwTjH6NqyKtEGrCaRAq2UDBqJpY4wz+03BUwE4DK82+5tWlW1v3sQB tYW9ykbd92Xiy/jXcl8K/PYNzlU519WsXK+IswiAzks7ZJCs7S2MUr2bYNPAzRLD0yl78cxtgSh AqcwZlFNU7av0HSXPQpbXb0+lheQY725el/yx6cvy/UBIqchMblQm4uHmB83C20IK7Ji8eV48YU ODycXEksHj8JQRa3k7jyykqdTImXkL4vrjcZTHh0PiqdQaIo++8Oq1YehNanl3BJP7iHjLERNo9 cLPrEIkJjX7iiY2Gdd3+9dP2zMW2WqER/jxcCAJlOXmvWv2noKp5fUghD2/rLoMzdKDx7/ZX11c LmCHjaV6xKrgvOpfsbF5OoPO6CaOAa6uCnTgbzUR5Rty57uxcxHnxe+fT2imSnufhEQB5bdz X-Authority-Analysis: v=2.4 cv=ZpjtK87G c=1 sm=1 tr=0 ts=68095772 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=s0E_TIProlikEKm38KMA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.680,FMLib:17.12.80.40 definitions=2025-04-23_11,2025-04-22_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 clxscore=1015 bulkscore=0 suspectscore=0 mlxlogscore=999 spamscore=0 impostorscore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504230144 From: Dmitry Baryshkov Continue migration to the MDSS-revision based checks and replace DPU_DSC_OUTPUT_CTRL feature bit with the core_major_ver >=3D 5 check. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 6 ------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 5 +---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 6 ++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 3 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +- 10 files changed, 8 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index 634b7dc452839f994c948601fe9a09581cb42a42..c5d964e915cdde1f8a83c2793b0= 020d7cecde672 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -262,19 +262,15 @@ static const struct dpu_dsc_cfg sm8150_dsc[] =3D { { .name =3D "dsc_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_1", .id =3D DSC_1, .base =3D 0x80400, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_2", .id =3D DSC_2, .base =3D 0x80800, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_3", .id =3D DSC_3, .base =3D 0x80c00, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index 59e280edcd508c14ee297857a19e9974970566de..dc21c5c232a7ce7d8c21d3a3f30= a5c1bc352ddd7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -261,27 +261,21 @@ static const struct dpu_dsc_cfg sc8180x_dsc[] =3D { { .name =3D "dsc_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_1", .id =3D DSC_1, .base =3D 0x80400, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_2", .id =3D DSC_2, .base =3D 0x80800, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_3", .id =3D DSC_3, .base =3D 0x80c00, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_4", .id =3D DSC_4, .base =3D 0x81000, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_5", .id =3D DSC_5, .base =3D 0x81400, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h index af0d789c47917e9b712282a542c3d0886313c049..c1e620ae9596f400655b64b47e6= b51a8d25e1428 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h @@ -195,11 +195,9 @@ static const struct dpu_dsc_cfg sm7150_dsc[] =3D { { .name =3D "dsc_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_1", .id =3D DSC_1, .base =3D 0x80400, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 4da7445aa8019894b35b12ace18c0bd6209b9148..81af11630202943b910cd5896f0= 7a32e53a23c6a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -261,19 +261,15 @@ static const struct dpu_dsc_cfg sm8250_dsc[] =3D { { .name =3D "dsc_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_1", .id =3D DSC_1, .base =3D 0x80400, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_2", .id =3D DSC_2, .base =3D 0x80800, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_3", .id =3D DSC_3, .base =3D 0x80c00, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index 6563296190bb27b6cab1b03921af6cff34037cd2..8cdd601a5350e80a5324db42c23= bdeb474a59b0c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -135,7 +135,6 @@ static const struct dpu_dsc_cfg sm6350_dsc[] =3D { { .name =3D "dsc_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index b5a3574e2ce43f7f5d47c42fe1bdd0f084396a9f..c08d8bae3293d00ef7ff2894269= 9ae2a52e2cea9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -87,7 +87,6 @@ static const struct dpu_dsc_cfg sm6375_dsc[] =3D { { .name =3D "dsc_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index ee8dd66a68f421161961495dd68d39dd4622ecf6..981d259c33631d31f0216f5cfae= 948b828d03592 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -176,14 +176,11 @@ enum { =20 /** * DSC sub-blocks/features - * @DPU_DSC_OUTPUT_CTRL Configure which PINGPONG block gets - * the pixel output from this DSC. * @DPU_DSC_NATIVE_42x_EN Supports NATIVE_422_EN and NATIVE_420_EN enc= oding * @DPU_DSC_MAX */ enum { - DPU_DSC_OUTPUT_CTRL =3D 0x1, - DPU_DSC_NATIVE_42x_EN, + DPU_DSC_NATIVE_42x_EN =3D 0x1, DPU_DSC_MAX }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_dsc.c index c7db917afd27e3daf1e8aad2ad671246bf6c8fbf..3a149caa7ff4f20dc7a902033cf= 29a168268839e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c @@ -186,11 +186,13 @@ static void dpu_hw_dsc_bind_pingpong_blk( * @dev: Corresponding device for devres management * @cfg: DSC catalog entry for which driver object is required * @addr: Mapped register io address of MDP + * @mdss_ver: dpu core's major and minor versions * Return: Error code or allocated dpu_hw_dsc context */ struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev, const struct dpu_dsc_cfg *cfg, - void __iomem *addr) + void __iomem *addr, + const struct dpu_mdss_version *mdss_ver) { struct dpu_hw_dsc *c; =20 @@ -207,7 +209,7 @@ struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *d= ev, c->ops.dsc_disable =3D dpu_hw_dsc_disable; c->ops.dsc_config =3D dpu_hw_dsc_config; c->ops.dsc_config_thresh =3D dpu_hw_dsc_config_thresh; - if (c->caps->features & BIT(DPU_DSC_OUTPUT_CTRL)) + if (mdss_ver->core_major_ver >=3D 5) c->ops.dsc_bind_pingpong_blk =3D dpu_hw_dsc_bind_pingpong_blk; =20 return c; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_dsc.h index fc171bdeca488f6287cf2ba7362ed330ad55b28f..b7013c9822d23238eb5411a5e28= 4bb072ecc3395 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h @@ -64,7 +64,8 @@ struct dpu_hw_dsc { =20 struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev, const struct dpu_dsc_cfg *cfg, - void __iomem *addr); + void __iomem *addr, + const struct dpu_mdss_version *mdss_ver); =20 struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(struct drm_device *dev, const struct dpu_dsc_cfg *cfg, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.c index f917ffb85d2f1b1a0ee826f125d02980b7a79052..f118c6caa1b9007eb03fa9b39ef= a87dfb46583ba 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -169,7 +169,7 @@ int dpu_rm_init(struct drm_device *dev, if (cat->mdss_ver->core_major_ver >=3D 7) hw =3D dpu_hw_dsc_init_1_2(dev, dsc, mmio); else - hw =3D dpu_hw_dsc_init(dev, dsc, mmio); + hw =3D dpu_hw_dsc_init(dev, dsc, mmio, cat->mdss_ver); =20 if (IS_ERR(hw)) { rc =3D PTR_ERR(hw); --=20 2.39.5