From nobody Mon Feb 9 16:51:43 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36E3F29DB96 for ; Wed, 23 Apr 2025 21:11:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745442673; cv=none; b=pWk4QaPy8D7Ego71F+3FUvMHyK/utCvj6n9DGpQnvq6I0lqJMaN8lKv/6fcxQ25VvXjSBD2XdEBylPGBDnEi6hB3kAOWHEXZxlATJfWUWc1X9jD5dHj8ZU0eKuRSEcgl3OTmFTRw8u0Lb/52Wu7RuYqWSvSuuNPghZYe37Dq1AM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745442673; c=relaxed/simple; bh=1Q5Qq8LHMqly9awcKHGrFdqYsNlcXps1NPzZnn8xu94=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tKalQmh3Yj+a/XiWpSHJ1oMiY3s/eC+I6O/mNcavlvbXqmmTtaux0RCPkc5EJf73kLu1HGtJvIy3YIxj4Q640GAM033HQaLpxQ51MXdHe7l88bmXUIgpYbVUxxQdSJN1CLKGYeD4xj1N58JJG7rpc/ZFe0bm8N6hjLTmN1BVN64= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Cz+Pe0VM; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Cz+Pe0VM" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 53NApGe6021142 for ; Wed, 23 Apr 2025 21:11:10 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= KBx0IIwlE6kHNbdjV51MVQZY6MRAmSHziUCDNMFzOHA=; b=Cz+Pe0VMV7jrxPVu htzSnFG2U8Hp+4KvzbFrjNTyWrbFybm2djPSJtuaLCJ+JEC7qcc3DGDjuHfcLXf8 Eo52kBb1a5lALw28BpZ1DXQdKo2htfva0ibuy9HkMUT8jXUX4QMOZ9jR+nk3nwet Wgk3+06MNdLRJ2td+MFYLFdU8vAhaDH7JbELEm/XfUp3hmScGcJMutueYgH+6MxH Nw4CgWv2GgFeCy3H5btDOsxBhsPX0KqJqYRg43YFxD2Y0+bn+pMqmEvEBhqvOqtU D68TpdGsTqA8xfT1t7NcCuQlLPU7JkaM/5+iJMcFecYeohP3C3rJWSz/Y4I4abbE g/rcCA== Received: from mail-qk1-f199.google.com (mail-qk1-f199.google.com [209.85.222.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 466jh23e0k-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Wed, 23 Apr 2025 21:11:10 +0000 (GMT) Received: by mail-qk1-f199.google.com with SMTP id af79cd13be357-7c0a3ff7e81so49686985a.3 for ; Wed, 23 Apr 2025 14:11:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745442668; x=1746047468; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KBx0IIwlE6kHNbdjV51MVQZY6MRAmSHziUCDNMFzOHA=; b=j0hAU0PGLt5Dx4Puk4b0qdEdF2UmHPebgKk2cuJbNN1MAsuZhL6lRzo3Fz4sBKvzhp XjTheNO0f7RO9OcRHj1SlTjf4sBFb8/kJmuR0nAZ4LqnKJNXqc6IkV/osEX4ppt/lx1w W2MgRgSu8qXX5otpnMxmepvATs2jS+uxo8nYOhtBMy3IVXAQO2IoGqq9LrtlOAkIbZvZ +7ecaqK7KJAK0bOkE+eoAiRi3eXT/UVJ/BFkleDsHxMTx2WubGTTJ5QFTtc7M1utt4pZ VDbI2UBBaj8I8yOkxhOADCeRm9PoBGo+NAUdRLH0QAIyuS5qNOqiM4Hqp7UhUPnB3FeY 4wxw== X-Forwarded-Encrypted: i=1; AJvYcCV+jxq876zBWWzIZvJriM1gCGsNEnM5+kqOLYjzGA/Ka6531mEzPcA8xfhZcUZYczTlDY7KrEV9pzHwQwI=@vger.kernel.org X-Gm-Message-State: AOJu0YxnNenX+Q2MwZQTI7Jf4yG+SKcZk7PWOPN4MHD/9gMrOHpTn+MQ sZQKiQr2kbKgeGPycCWo3TeArAMzPZ9uNW302sR6yBzJZNcof5AOYPv0vIX3pxKbFefeeuzj3vU 66QNw1J+NI+Y+4IDnu8q99yEZvvEoEx/zX2NN7Ufiz4iBuVSdnlqtiPvKzjfMEhQ= X-Gm-Gg: ASbGncsJvrEJcYfdELUgqC8WKO0TjrFSKBAgyYxDd2wVxW+Lji+ovvKCfk3KAnLmQDD F1umSShvwtf9r3S+d7RONF4sV1bBbw+jmam4A7YwGwe8Mcxxl6YUO3MEHJOQz7QNuz4iUEDwU7T bSzK645Ep3YuLwY+Tc13MTG9oGnN6RzGar9ZPFqebnx5B580z2b5M0zG7aIJADMn9p7E3uZjlh4 nPNYvIXnXLmn943EfDbhwD7ku6PuZ+y2bMJctZrplz7jaSEkH09LlPTg0tbcFlzLVXhmCcNRccF /MCsKc79ZSHG42lSZgtTzxMbRK3hwZc2LV+A6wXezdqQt5dYbQqeTh4HvDZZ7k1wDJ5OxOh6SWz Ve9zElmSJTqzHp2C0bB2eUmV4 X-Received: by 2002:a05:620a:280a:b0:7c7:a63c:319a with SMTP id af79cd13be357-7c956e7c5fdmr50052185a.9.1745442668411; Wed, 23 Apr 2025 14:11:08 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGOcujn1f1pN5wnkFBUAymhqnHRowVXS7nSEsU2cWCk3LZp7tigzFEk2SEbAqgFOYEMqvGYqA== X-Received: by 2002:a05:620a:280a:b0:7c7:a63c:319a with SMTP id af79cd13be357-7c956e7c5fdmr50046885a.9.1745442667797; Wed, 23 Apr 2025 14:11:07 -0700 (PDT) Received: from umbar.lan (2001-14ba-a0c3-3a00-264b-feff-fe8b-be8a.rev.dnainternet.fi. [2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54e7cb3987csm3852e87.59.2025.04.23.14.11.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Apr 2025 14:11:05 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 24 Apr 2025 00:10:19 +0300 Subject: [PATCH v2 23/33] drm/msm/dpu: get rid of DPU_DSC_HW_REV_1_2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-dpu-drop-features-v2-23-0a9a66a7b3a2@oss.qualcomm.com> References: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> In-Reply-To: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=12855; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=Q3MTIf4rQy+am/uHf/BMkZYmbIwxtrhN/RYvyuNUjQI=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoCVctzKa9fJu4DotHY6EFC71m03848hAFtkbHi rTcVurxiAqJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaAlXLQAKCRCLPIo+Aiko 1Q3cB/0Sxn3FwqWTKfjpLAYxMM1PDjbruGyyi90Cw1OrkKBOEtRehZMQFpq+hlUgi08Thl0Y4k4 YY/qjFhTO7DXxtJxlAk7bVPl7HNVZksR/ANnV6OZgawU1VxszbPsmvD29UcABIraNq9lvpxXJyt 57EkE9bHworM6UiLTvj+2Y3enpWZ7hAkLXtGZGGoGXO/YRAwWOJkipmoO38gCmx3mOXK1D/yEy1 Ke+OQD5Qlb8v5Y7Oa5B9RgxHrUWAIkwK+8YtreOh4DyAzcPmJzYWp76OtJty6FAClJPKaba5b21 9mvA0R27BfQfRkNQocMhS1vlaJKsYJjss12wGzfWPtc8RKlF X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=EtLSrTcA c=1 sm=1 tr=0 ts=6809576e cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=C81KZioEkqZAcCmD564A:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: LzVHbE8NXdCA_UNo0bQNZqa1rEj-6dWi X-Proofpoint-ORIG-GUID: LzVHbE8NXdCA_UNo0bQNZqa1rEj-6dWi X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDIzMDE0NCBTYWx0ZWRfX+MY9pUa1Q6w8 DgYmbyhwpeuHNCFtME+eneaqKrDQBDSTTAWTZ7pUmTzzse3aptNUKrN8iyUs29/Y66xkrfaYw6G cb1iIfO/n/m0+fBw2VPZMT/UdKsocfzOUtlNN5DeeYWqn1P/DujjkcgDPYdv24vmCTM2pGHr/GH Ao18LCehvYbPIwVBDI2OWhVD5HSaYh5uDcBJNcr/vfJSoK2JwylHWJWG4jblxAMDgd2fz3ald8T CcMDyMfi/ymwdaQQre6G4AMvhwKqOxxNyHui3bowIUuWjKH6/a5OB5vrVl80R7Xp4rewFFGZQ1+ vDNx6cFO8977dUPjXp1pk7CG9cwrfN9SLiucNqe6HZ+CUTZhCjblxl0uXEJQSAhV0kDXQyYpBOL GYFtlBfW9tyT7sNwYb9z85nDaMvSjJQM/0G+58AxTDQBSOj/fXEAMhgbU/5qmQx9LfNEqOXh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.680,FMLib:17.12.80.40 definitions=2025-04-23_11,2025-04-22_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 suspectscore=0 mlxscore=0 clxscore=1015 spamscore=0 mlxlogscore=999 lowpriorityscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504230144 From: Dmitry Baryshkov Continue migration to the MDSS-revision based checks and replace DPU_DSC_HW_REV_1_2 feature bit with the core_major_ver >=3D 7 check. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 10 ++++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 6 ++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 8 ++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 6 ++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 8 ++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 6 ++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 6 ++---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +- 11 files changed, 19 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index d64366f608ea673422bbf4e5b6ae7f4ad8570784..5f6b1251f30f3c6dfb20261a0d1= bbf776ed5dd33 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -289,32 +289,30 @@ static const struct dpu_dsc_cfg sm8650_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_2_0", .id =3D DSC_4, .base =3D 0x82000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_2_1", .id =3D DSC_5, .base =3D 0x82000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 62de32268ee5528ff0fb16a3ff7c2baa5ea42466..bb35eea64a5af844965259cd96b= ef10d9955b493 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -266,22 +266,20 @@ static const struct dpu_dsc_cfg sm8350_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 202de6f9b0c65c6f2caa9e9d5232f5b92d8bdf01..d21b2266909050fd20bf55b6fab= e07351e445c5a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -150,7 +150,7 @@ static const struct dpu_dsc_cfg sc7280_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 43916752cfd5836718a3770df4c8767635f77ee9..72110b2a2770435ac886e992b1c= cce280c5ac3db 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -265,32 +265,28 @@ static const struct dpu_dsc_cfg sc8280xp_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_2_0", .id =3D DSC_4, .base =3D 0x82000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_2_1", .id =3D DSC_5, .base =3D 0x82000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index d58d5b7ce79b8c069d111c3c2aa3e9cdb2c1a435..305a798768c60a2ec409c1021a9= 1efc4eccc92fd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -279,22 +279,20 @@ static const struct dpu_dsc_cfg sm8450_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index 064546d4fd4538cd5a6b56fca3ee12d482a7dbb6..67aed1ebc78952c6dfce0cc9f16= 80fa75ec26e13 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -278,32 +278,28 @@ static const struct dpu_dsc_cfg sa8775p_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_2_0", .id =3D DSC_4, .base =3D 0x82000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_2_1", .id =3D DSC_5, .base =3D 0x82000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 959f3e9dbc5455fe53c1bb240b5db57212f2d4eb..b54a208e48a8508c39b4e4e95c9= e26ce28ba7c02 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -275,22 +275,20 @@ static const struct dpu_dsc_cfg sm8550_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index 174cfdfcfdf9860ea86c983c6b6591ba98da5400..da2fdf01a17d29fd9a7ea46890d= b7a33fedee31e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -275,22 +275,20 @@ static const struct dpu_dsc_cfg x1e80100_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 8e6fcb51aad8278eb80570a44a423c2443744c61..ee8dd66a68f421161961495dd68= d39dd4622ecf6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -178,13 +178,11 @@ enum { * DSC sub-blocks/features * @DPU_DSC_OUTPUT_CTRL Configure which PINGPONG block gets * the pixel output from this DSC. - * @DPU_DSC_HW_REV_1_2 DSC block supports DSC 1.1 and 1.2 * @DPU_DSC_NATIVE_42x_EN Supports NATIVE_422_EN and NATIVE_420_EN enc= oding * @DPU_DSC_MAX */ enum { DPU_DSC_OUTPUT_CTRL =3D 0x1, - DPU_DSC_HW_REV_1_2, DPU_DSC_NATIVE_42x_EN, DPU_DSC_MAX }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index f3f84c8c302fb1bfe6e6d70e4110d0b89259e55c..d44461e7e1641b25c5181bf7c0c= 9bbedffcc869d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1043,7 +1043,7 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_stat= e *disp_state, struct msm_k msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len, base, "%s", cat->dsc[i].name); =20 - if (cat->dsc[i].features & BIT(DPU_DSC_HW_REV_1_2)) { + if (cat->mdss_ver->core_major_ver >=3D 7) { struct dpu_dsc_blk enc =3D cat->dsc[i].sblk->enc; struct dpu_dsc_blk ctl =3D cat->dsc[i].sblk->ctl; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.c index 5d55b246b32f0757281d8743ae2d1a23cc6e333d..f917ffb85d2f1b1a0ee826f125d= 02980b7a79052 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -166,7 +166,7 @@ int dpu_rm_init(struct drm_device *dev, struct dpu_hw_dsc *hw; const struct dpu_dsc_cfg *dsc =3D &cat->dsc[i]; =20 - if (test_bit(DPU_DSC_HW_REV_1_2, &dsc->features)) + if (cat->mdss_ver->core_major_ver >=3D 7) hw =3D dpu_hw_dsc_init_1_2(dev, dsc, mmio); else hw =3D dpu_hw_dsc_init(dev, dsc, mmio); --=20 2.39.5