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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54e7cb3987csm3852e87.59.2025.04.23.14.10.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Apr 2025 14:10:51 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 24 Apr 2025 00:10:14 +0300 Subject: [PATCH v2 18/33] drm/msm/dpu: get rid of DPU_MDP_VSYNC_SEL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-dpu-drop-features-v2-18-0a9a66a7b3a2@oss.qualcomm.com> References: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> In-Reply-To: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8032; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=aitBeEK1lAlbuZORfcr1XUSiZGXBb4ytUSBho231JhA=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoCVcsrxoAthuShM8NE8HARFr0pMmaa+QFSo8Iq /P35ifg7DiJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaAlXLAAKCRCLPIo+Aiko 1b3PB/0S6ovu7fDyFkI0O1lHhaqdLMgrng8GmDHpFN7x+EElzoZ8tJKVh8GIDC0o1ed6G0DCWPO 4P/eyDHjusNK93ymoGKPjXDlT/KfrzzwECCrtFyP0s+vQngBVSMbw4h7SvlusAIglv1otcPK5cw uOsk0GhFpvyxjR4yM4qcG6nQhUgkQr8eWIy/vlEoa92lt5XbJYlz14H6gZhS4atNpfoQHXvxXex OwHvgNmfat6UB8rGp45wn867Fu85+sifBfy0fbi31IIMYPKtK90IgOzX25ZIs6wqNRztEbHUTUf HcjNQwV67TnltxZgfT+I4YwOS+vqkpnUY8mxDoLSwFwVk3f3 X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDIzMDE0NCBTYWx0ZWRfXwU7f2ias6C2K 6S+rzn6tXPgPJtCW4BHxVGYUT0ZOGMxtrv/6eea+0rIQMgpNxi51G6jJgdC6RbRlx980SazD+Xv AWOxFXuyy2FbOIBwPc+hVp/bJNSG/770PBRWECbfhn+H5C6c4ulMbvh1d+2IdVeyirx4oV1lwm0 +Rz9yGq/OP9Pi4Y67iZ0vRWFzAQKjKaEMYpnzvwbLLez6EXB2rJOhjI87pTKsmgjvr4Sa2zIG6U tmWYYCkuutqaffkgG1oCktmgTXt7s1puTjdjnRaWLmRktD/JDG9P42ilLQxWF99F0IqS1JT871n 6xNsfk52YoDTDug8WWWqiGH5/hhXD6AtDUvqQSlLgOr1UwMb7V3bkrWOsDpFBkve1zvyQcqUuY0 S4mtvy2Dek+be7LVr/O8CvnAx/aN/h0VtmZudCE6iIpvuxsY5lO+09LSA8BIGT0Q1PTp9NUf X-Proofpoint-GUID: Bt7aIFFAStnEqfy2aKFrd7KlO2fh4Lwd X-Authority-Analysis: v=2.4 cv=ZuTtK87G c=1 sm=1 tr=0 ts=6809575f cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=ul0-cYutqJjMKJRySm4A:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: Bt7aIFFAStnEqfy2aKFrd7KlO2fh4Lwd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.680,FMLib:17.12.80.40 definitions=2025-04-23_11,2025-04-22_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 impostorscore=0 bulkscore=0 mlxscore=0 adultscore=0 lowpriorityscore=0 mlxlogscore=805 priorityscore=1501 malwarescore=0 suspectscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504230144 From: Dmitry Baryshkov Continue migration to the MDSS-revision based checks and replace DPU_MDP_VSYNC_SEL feature bit with the core_major_ver < 5 check. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 2 +- 10 files changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h index c0b4db94777c42efd941fdd52993b854ab54c694..29e0eba91930f96fb94c97c33b4= 490771c3a7c17 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h @@ -19,7 +19,6 @@ static const struct dpu_mdp_cfg msm8937_mdp[] =3D { { .name =3D "top_0", .base =3D 0x0, .len =3D 0x454, - .features =3D BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_RGB0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 4 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h index d3e4c48be306a04b457cc002910eb018a3f13154..cb1ee4b63f9fe8f0b069ad4a75b= 121d40e988d2b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h @@ -19,7 +19,6 @@ static const struct dpu_mdp_cfg msm8917_mdp[] =3D { { .name =3D "top_0", .base =3D 0x0, .len =3D 0x454, - .features =3D BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_RGB0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 4 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h index c488b88332d0e69cfb23bcf4e41a2e4f4be6844d..b44d02b48418f7bca50b0411954= 0122fb861b971 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h @@ -19,7 +19,6 @@ static const struct dpu_mdp_cfg msm8953_mdp[] =3D { { .name =3D "top_0", .base =3D 0x0, .len =3D 0x454, - .features =3D BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_RGB0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 4 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h index ac0d872ac06be7376b7b4111e1ac5f4057b5fb76..436fa56e2ba2d867b58b59ec6b0= 2d1d0f396c23b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h @@ -22,7 +22,6 @@ static const struct dpu_mdp_cfg msm8996_mdp[] =3D { { .name =3D "top_0", .base =3D 0x0, .len =3D 0x454, - .features =3D BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_VIG1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index b171e26165f11185645ac5e6d22c499a949d8271..38cdea019bf2b1391c242953e4c= 67d9dc4c2274c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -23,7 +23,6 @@ static const struct dpu_caps msm8998_dpu_caps =3D { static const struct dpu_mdp_cfg msm8998_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x458, - .features =3D BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_VIG1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h index 6308dece88db70932d55d1e2d4e8af713996d9e0..176640bff1214e89606286ce572= f74300f6f343f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h @@ -22,7 +22,6 @@ static const struct dpu_caps sdm660_dpu_caps =3D { static const struct dpu_mdp_cfg sdm660_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x458, - .features =3D BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_VIG1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h index 25954ae17cec5b141637e7c2eba29a1bc826b1fe..e6eb95173cfef2a52f5dc606ca4= 1a2f1f5650c2c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h @@ -22,7 +22,6 @@ static const struct dpu_caps sdm630_dpu_caps =3D { static const struct dpu_mdp_cfg sdm630_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x458, - .features =3D BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_DMA0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 8 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 283e709065be31131f6bc51580296e836b8487ae..9f04c7cd5539c012a9490556a57= 36d09aa0a10c1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -23,7 +23,7 @@ static const struct dpu_caps sdm845_dpu_caps =3D { static const struct dpu_mdp_cfg sdm845_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x45c, - .features =3D BIT(DPU_MDP_AUDIO_SELECT) | BIT(DPU_MDP_VSYNC_SEL), + .features =3D BIT(DPU_MDP_AUDIO_SELECT), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_VIG1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 530eb74b0548b0a257abc89c3e12ab990addd550..3a0de200cc5c9751adebe681f80= 679e0d527ab1c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -34,8 +34,6 @@ * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats * @DPU_MDP_PERIPH_0_REMOVED Indicates that access to periph top0 block re= sults * in a failure - * @DPU_MDP_VSYNC_SEL Enables vsync source selection via MDP_VSYNC_SE= L register - * (moved into INTF block since DPU 5.0.0) * @DPU_MDP_MAX Maximum value =20 */ @@ -44,7 +42,6 @@ enum { DPU_MDP_10BIT_SUPPORT, DPU_MDP_AUDIO_SELECT, DPU_MDP_PERIPH_0_REMOVED, - DPU_MDP_VSYNC_SEL, DPU_MDP_MAX }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_top.c index 562a3f4c5238a3ad6c8c1fa4d285b9165ada3cfd..cebe7ce7b258fc178a687770906= f7c4c20aa0d4c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c @@ -270,7 +270,7 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops, ops->setup_clk_force_ctrl =3D dpu_hw_setup_clk_force_ctrl; ops->get_danger_status =3D dpu_hw_get_danger_status; =20 - if (cap & BIT(DPU_MDP_VSYNC_SEL)) + if (mdss_rev->core_major_ver < 5) ops->setup_vsync_source =3D dpu_hw_setup_vsync_sel; else if (!(cap & BIT(DPU_MDP_PERIPH_0_REMOVED))) ops->setup_vsync_source =3D dpu_hw_setup_wd_timer; --=20 2.39.5