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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54e7cb3987csm3852e87.59.2025.04.23.14.10.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Apr 2025 14:10:37 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 24 Apr 2025 00:10:09 +0300 Subject: [PATCH v2 13/33] drm/msm/dpu: get rid of DPU_DATA_HCTL_EN Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-dpu-drop-features-v2-13-0a9a66a7b3a2@oss.qualcomm.com> References: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> In-Reply-To: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2745; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=RMvwZw2IoUGRGV6OIhReHxHfhgm4YrJasKj5L020giI=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoCVcsgHXSRWQsQpb7cjMEJ4q8XMjB7P0NtBHbO UmFK5Vs7QuJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaAlXLAAKCRCLPIo+Aiko 1TjcB/wIbmuUwTeNRUvW4dGyL85rL8ac8oHysgu2g9gKUuC9oYDQaeqt2enNDmjDMIBWEo1SsZi EW61+QeJSzm8t3YnJJHb/fid0qGpMRxeYrAXqP0x9r0bVAiglh3Ye96Yi+VAxggdGX6mNdTqvTo kJ2Ra6ZC8wB02tPdfpdskdxRiB8Idwy6b6bE7UILMANizhDQkY1kiuY903XwbSHeArpVTgNNSfq E3S68/AKz0I770W25Q6hNohRbaOSfQ6t+Ke+WTxt8RpHpPcrfjTiYkRFLexY/AiFz9V0HJGsOYq iZatFbp2AcQTe9swXeDmyoBfg2Mopct6BJPfJvFlkJpqyNf2 X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: rjHHzWn5MM99SmWkw2X2YE11j3mxhs5n X-Authority-Analysis: v=2.4 cv=OY6YDgTY c=1 sm=1 tr=0 ts=68095758 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=BlGH1-kmwhya4yQ-KWAA:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: rjHHzWn5MM99SmWkw2X2YE11j3mxhs5n X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDIzMDE0NCBTYWx0ZWRfXw7TY/2D3eFW3 nbB6G8vted0ldAxphYPMnk1Bx2RtSmCuw4qGNt2sbzUK8jXcV7zi7+KcZEl6z2Bo/IW7HHJMfcM eyb2/kFS5VdkTcYoyOHFkLxanp9DxvAZ2tWnGmaFNL45U7jwadpHjS+1m/5KbTy14J45I3jG80I VpRGiUo/JSCT14CkMxQX8QpslfcPXwQYcz2FWSgPsnV7OypKuRI/tv3U+CELQrwVMG3qbJr7OaG zQMxJm0omSrlrqCQY2WlwhRRmr518GdYJNU0VfOcZkHyHprQ3YpDVtMJ4NmQ2RgjbRRLxx7Ib7I 6HDjKeSbM23h6enVVmToiIbgQCs7KgA7CYSqsUYguA6GYhpo7oc2tEo4fap2Weu5WAwIXjDu8uZ jVOqumUHGfLfo1LpwDqFN7QVYULOcZZoVJkW4mvE+30hcfmBab2bsMZNanrogiKAPTUbA7Cj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.680,FMLib:17.12.80.40 definitions=2025-04-23_11,2025-04-22_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 mlxscore=0 clxscore=1015 malwarescore=0 mlxlogscore=999 phishscore=0 priorityscore=1501 spamscore=0 adultscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504230144 From: Dmitry Baryshkov Continue migration to the MDSS-revision based checks and replace DPU_DATA_HCTL_EN feature bit with the core_major_ver >=3D 5 check. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 2 +- 3 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 22ca093419059600f0ad7e1e7a0a4e443b977860..20f4700ef9969003cfa4728049b= 9737cb9eb6229 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -112,8 +112,7 @@ =20 #define INTF_SC7180_MASK \ (BIT(DPU_INTF_INPUT_CTRL) | \ - BIT(DPU_INTF_STATUS_SUPPORTED) | \ - BIT(DPU_DATA_HCTL_EN)) + BIT(DPU_INTF_STATUS_SUPPORTED)) =20 #define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \ BIT(DPU_WB_UBWC) | \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 27422a5a340b90ee02f36a87cf1bab9d97504c76..36100e21135fba09fcafdd5d36a= c919cd17f63c0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -145,14 +145,11 @@ enum { * INTF sub-blocks * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from = which * pixel data arrives to this INTF - * @DPU_DATA_HCTL_EN Allows data to be transferred at diffe= rent rate - * than video timing * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register * @DPU_INTF_MAX */ enum { DPU_INTF_INPUT_CTRL =3D 0x1, - DPU_DATA_HCTL_EN, DPU_INTF_STATUS_SUPPORTED, DPU_INTF_MAX }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_intf.c index 1d56c21ac79095ab515aeb485346e1eb5793c260..8f9733aad2dec3a9b5464d55b00= f350348842911 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -237,7 +237,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_= hw_intf *intf, DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3); DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg); DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format); - if (intf->cap->features & BIT(DPU_DATA_HCTL_EN)) { + if (intf->mdss_ver->core_major_ver >=3D 5) { /* * DATA_HCTL_EN controls data timing which can be different from * video timing. It is recommended to enable it for all cases, except --=20 2.39.5