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Instead store a pointer to it inside struct dpu_hw_intf and use it diretly. It's not that the MDSS revision can chance between dpu_hw_intf_init() and dpu_encoder_phys_vid_setup_timing_engine(). Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 3 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 7 ++++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 5 +++-- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers= /gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index abd6600046cb3a91bf88ca240fd9b9c306b0ea2e..3e0f1288ad17e19f6d0b7c5dcba= 19d3e5977a461 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -307,8 +307,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine( =20 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf, - &timing_params, fmt, - phys_enc->dpu_kms->catalog->mdss_ver); + &timing_params, fmt); phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); =20 /* setup which pp blk will connect to this intf */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_intf.c index fb1d25baa518057e74fec3406faffd48969d492b..1d56c21ac79095ab515aeb48534= 6e1eb5793c260 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -98,8 +98,7 @@ =20 static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, const struct dpu_hw_intf_timing_params *p, - const struct msm_format *fmt, - const struct dpu_mdss_version *mdss_ver) + const struct msm_format *fmt) { struct dpu_hw_blk_reg_map *c =3D &intf->hw; u32 hsync_period, vsync_period; @@ -180,7 +179,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_= hw_intf *intf, =20 /* TODO: handle DSC+DP case, we only handle DSC+DSI case so far */ if (p->compression_en && !dp_intf && - mdss_ver->core_major_ver >=3D 7) + intf->mdss_ver->core_major_ver >=3D 7) intf_cfg2 |=3D INTF_CFG2_DCE_DATA_COMPRESS; =20 hsync_data_start_x =3D hsync_start_x; @@ -580,6 +579,8 @@ struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device = *dev, c->idx =3D cfg->id; c->cap =3D cfg; =20 + c->mdss_ver =3D mdss_rev; + c->ops.setup_timing_gen =3D dpu_hw_intf_setup_timing_engine; c->ops.setup_prg_fetch =3D dpu_hw_intf_setup_prg_fetch; c->ops.get_status =3D dpu_hw_intf_get_status; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_intf.h index 114be272ac0ae67fe0d4dfc0c117baa4106f77c9..f31067a9aaf1d6b96c771571351= 22e5e8bccb7c4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h @@ -81,8 +81,7 @@ struct dpu_hw_intf_cmd_mode_cfg { struct dpu_hw_intf_ops { void (*setup_timing_gen)(struct dpu_hw_intf *intf, const struct dpu_hw_intf_timing_params *p, - const struct msm_format *fmt, - const struct dpu_mdss_version *mdss_ver); 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Stop defining a separate symbol and use the INTF_SC7180_MASK instead. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 6 +++--- .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 18 +++++++++-----= ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 8 ++++---- .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 16 ++++++++------= -- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 8 ++++---- .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 18 +++++++++-----= ---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 -- 9 files changed, 45 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index 6ac97c378056c08c937ed992b81d139cbb1fbbb0..a8b5c5b5a2e8d9d67ee185f00d9= 2feeec42e490f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -375,7 +375,7 @@ static const struct dpu_intf_cfg sm8650_intf[] =3D { { .name =3D "intf_0", .id =3D INTF_0, .base =3D 0x34000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -384,7 +384,7 @@ static const struct dpu_intf_cfg sm8650_intf[] =3D { }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x35000, .len =3D 0x300, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -394,7 +394,7 @@ static const struct dpu_intf_cfg sm8650_intf[] =3D { }, { .name =3D "intf_2", .id =3D INTF_2, .base =3D 0x36000, .len =3D 0x300, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, @@ -404,7 +404,7 @@ static const struct dpu_intf_cfg sm8650_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x37000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 0c860e804cab8ece8966596f4ec2b17ff3aa226f..93427f7cac3a370fdac3f119134= bf9fee8b87a17 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -319,7 +319,7 @@ static const struct dpu_intf_cfg sm8350_intf[] =3D { { .name =3D "intf_0", .id =3D INTF_0, .base =3D 0x34000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -328,7 +328,7 @@ static const struct dpu_intf_cfg sm8350_intf[] =3D { }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x35000, .len =3D 0x2c4, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -338,7 +338,7 @@ static const struct dpu_intf_cfg sm8350_intf[] =3D { }, { .name =3D "intf_2", .id =3D INTF_2, .base =3D 0x36000, .len =3D 0x2c4, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, @@ -348,7 +348,7 @@ static const struct dpu_intf_cfg sm8350_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x37000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index e9625c48c5677ef221b8fc80e7f9df8957b847e2..1edec0644b078ac1fff129354d4= d02eec015a331 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -183,7 +183,7 @@ static const struct dpu_intf_cfg sc7280_intf[] =3D { { .name =3D "intf_0", .id =3D INTF_0, .base =3D 0x34000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -192,7 +192,7 @@ static const struct dpu_intf_cfg sc7280_intf[] =3D { }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x35000, .len =3D 0x2c4, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -202,7 +202,7 @@ static const struct dpu_intf_cfg sc7280_intf[] =3D { }, { .name =3D "intf_5", .id =3D INTF_5, .base =3D 0x39000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index fcee1c3665f88a9defca4fec38dd76d56c97297e..7d698fc354666a2dc468a71ff08= cb8df0c37234c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -315,7 +315,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { { .name =3D "intf_0", .id =3D INTF_0, .base =3D 0x34000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -324,7 +324,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x35000, .len =3D 0x300, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -334,7 +334,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { }, { .name =3D "intf_2", .id =3D INTF_2, .base =3D 0x36000, .len =3D 0x300, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, @@ -344,7 +344,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x37000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_NONE, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -353,7 +353,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { }, { .name =3D "intf_4", .id =3D INTF_4, .base =3D 0x38000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, @@ -362,7 +362,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { }, { .name =3D "intf_5", .id =3D INTF_5, .base =3D 0x39000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_3, .prog_fetch_lines_worst_case =3D 24, @@ -371,7 +371,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { }, { .name =3D "intf_6", .id =3D INTF_6, .base =3D 0x3a000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_2, .prog_fetch_lines_worst_case =3D 24, @@ -380,7 +380,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { }, { .name =3D "intf_7", .id =3D INTF_7, .base =3D 0x3b000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_NONE, .controller_id =3D MSM_DP_CONTROLLER_2, .prog_fetch_lines_worst_case =3D 24, @@ -389,7 +389,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { }, { .name =3D "intf_8", .id =3D INTF_8, .base =3D 0x3c000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_NONE, .controller_id =3D MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 19b2ee8bbd5fd3ab6096ea1c9dc2e0f804bec973..ce050c898b9f21e69e5ff967c2a= f7c2df1e08232 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -335,7 +335,7 @@ static const struct dpu_intf_cfg sm8450_intf[] =3D { { .name =3D "intf_0", .id =3D INTF_0, .base =3D 0x34000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -344,7 +344,7 @@ static const struct dpu_intf_cfg sm8450_intf[] =3D { }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x35000, .len =3D 0x300, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -354,7 +354,7 @@ static const struct dpu_intf_cfg sm8450_intf[] =3D { }, { .name =3D "intf_2", .id =3D INTF_2, .base =3D 0x36000, .len =3D 0x300, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, @@ -364,7 +364,7 @@ static const struct dpu_intf_cfg sm8450_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x37000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index 4d96ce71746f2595427649d0fdb73dae0c18be60..4291b4f9ce324eb517022eabe3a= b6078b1c3a2fb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -345,7 +345,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] =3D { { .name =3D "intf_0", .id =3D INTF_0, .base =3D 0x34000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -354,7 +354,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] =3D { }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x35000, .len =3D 0x300, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -364,7 +364,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] =3D { }, { .name =3D "intf_2", .id =3D INTF_2, .base =3D 0x36000, .len =3D 0x300, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, @@ -374,7 +374,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x37000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_NONE, .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case =3D 24, @@ -383,7 +383,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] =3D { }, { .name =3D "intf_4", .id =3D INTF_4, .base =3D 0x38000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, @@ -392,7 +392,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] =3D { }, { .name =3D "intf_6", .id =3D INTF_6, .base =3D 0x3A000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_NONE, .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case =3D 24, @@ -401,7 +401,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] =3D { }, { .name =3D "intf_7", .id =3D INTF_7, .base =3D 0x3b000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_NONE, .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case =3D 24, @@ -410,7 +410,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] =3D { }, { .name =3D "intf_8", .id =3D INTF_8, .base =3D 0x3c000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_NONE, .controller_id =3D MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */ .prog_fetch_lines_worst_case =3D 24, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 24f988465bf6ba8e3d3d2691534f0981f222fa27..a6ab5c49654010194bfc1d4991f= fec411ef6e6fd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -330,7 +330,7 @@ static const struct dpu_intf_cfg sm8550_intf[] =3D { { .name =3D "intf_0", .id =3D INTF_0, .base =3D 0x34000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -339,7 +339,7 @@ static const struct dpu_intf_cfg sm8550_intf[] =3D { }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x35000, .len =3D 0x300, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -349,7 +349,7 @@ static const struct dpu_intf_cfg sm8550_intf[] =3D { }, { .name =3D "intf_2", .id =3D INTF_2, .base =3D 0x36000, .len =3D 0x300, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, @@ -359,7 +359,7 @@ static const struct dpu_intf_cfg sm8550_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x37000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index 6417baa84f826feb3bc6eaa6b063ad75e597a9d7..ad486b03c54d9beb6d77df4d6b5= f142fd1dd8d8d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -331,7 +331,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { { .name =3D "intf_0", .id =3D INTF_0, .base =3D 0x34000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -340,7 +340,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x35000, .len =3D 0x300, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -350,7 +350,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { }, { .name =3D "intf_2", .id =3D INTF_2, .base =3D 0x36000, .len =3D 0x300, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, @@ -360,7 +360,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x37000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_NONE, .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case =3D 24, @@ -369,7 +369,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { }, { .name =3D "intf_4", .id =3D INTF_4, .base =3D 0x38000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, @@ -378,7 +378,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { }, { .name =3D "intf_5", .id =3D INTF_5, .base =3D 0x39000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_3, .prog_fetch_lines_worst_case =3D 24, @@ -387,7 +387,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { }, { .name =3D "intf_6", .id =3D INTF_6, .base =3D 0x3A000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_2, .prog_fetch_lines_worst_case =3D 24, @@ -396,7 +396,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { }, { .name =3D "intf_7", .id =3D INTF_7, .base =3D 0x3b000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_NONE, .controller_id =3D MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */ .prog_fetch_lines_worst_case =3D 24, @@ -405,7 +405,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { }, { .name =3D "intf_8", .id =3D INTF_8, .base =3D 0x3c000, .len =3D 0x280, - .features =3D INTF_SC7280_MASK, + .features =3D INTF_SC7180_MASK, .type =3D INTF_NONE, .controller_id =3D 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54e7cb3987csm3852e87.59.2025.04.23.14.10.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Apr 2025 14:10:14 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 24 Apr 2025 00:09:59 +0300 Subject: [PATCH v2 03/33] drm/msm/dpu: inline _setup_ctl_ops() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-dpu-drop-features-v2-3-0a9a66a7b3a2@oss.qualcomm.com> References: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> In-Reply-To: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5798; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=6nM57vgHQs62/wjwRtInuGG9vKrODBr++a+KVt2bcP8=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoCVcqR78AVabkljNMdVv4nChjUUZi19cLr/AkO te1yG+cha+JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaAlXKgAKCRCLPIo+Aiko 1UF4CACtPfY/P7W/9z6muHd/1TjgUuQPAMTG/CDZLtb0nMV3YCQP+r3BkPMztFwLpqnaI1ntlEa SixOPQ8FkQKfUBi1Q8q4zggAEMhCe2CeoG/QxZgPQeS1WIVXFvFrJgNQ9QSZikQ5uKxZlQlOpEX nHPYV+hb8Q4xHqvz7TyNlsQqzXfVLSHiKtgX4bWG3HQj8UnvO9C015QnoplGwFT1oJv8jGYlWD3 1cYagbeGBXFI3HYwJAhe/UPE1X9JMdgcATZacObmwMQj4wRAHK4qLuGW8yGplYAiLMSYzqhc/x/ XupU9bqm3Degoqt15RXa/dJBlCDejc144gZiwVBBCP6I5IyC X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: 7l8Niidcgh_oT3pM3jNN6HWh3Yhxorg1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDIzMDE0MyBTYWx0ZWRfXx8jCzLYVqoa6 0ROvYTVFrAMiRgZFTd6BAiVhea6Sl/tfl0XM+8VnVKMV29mIm2XoZAsRPTBpIbz7ey8r7dfd9Nc EAOD+d7jfrapXGAqkcCojcHYOsseXqjNP7/YJRsa7+kI4nA4ZzCI7GrNaKgT/xwO8ywb9BH9KIf Sof24CV4o+g0jNG9gtJqz5vpadSqgbh5r3Q5C00IYLqJqIXBHXIz1T0BDbSGpqr3yk4Pq7Qt6Yi NHEgMqfkl+4Te+1Nfx1JmTVGB5fGrZG8EyvlodizJRFfoLHTvf62Xne9pe+cwuUwobxYw3LqqvU +YshNsQMFX3y1rJaVzjFhlT83JZtkozux4/3rp2+fbL8+o6elkO/397xPnU/n9G9giiVZ/gkayV Es8y+7+IkJHFEVfzJbGWu5xY61ot12roK0RW+7IgJ7OD98mEyl3QutP2E+73tyebul3T1BOn X-Authority-Analysis: v=2.4 cv=Tu/mhCXh c=1 sm=1 tr=0 ts=68095738 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=RpF703knbOfOEe3tTfUA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: 7l8Niidcgh_oT3pM3jNN6HWh3Yhxorg1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.680,FMLib:17.12.80.40 definitions=2025-04-23_11,2025-04-22_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 phishscore=0 mlxlogscore=999 bulkscore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504230143 From: Dmitry Baryshkov Inline the _setup_ctl_ops() function, it makes it easier to handle different conditions involving CTL configuration. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 98 ++++++++++++++------------= ---- 1 file changed, 47 insertions(+), 51 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.c index 411a7cf088eb72f856940c09b0af9e108ccade4b..466bfee3db52d980877a5cdc4ee= b739cae250afc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -714,56 +714,6 @@ static void dpu_hw_ctl_set_fetch_pipe_active(struct dp= u_hw_ctl *ctx, DPU_REG_WRITE(&ctx->hw, CTL_FETCH_PIPE_ACTIVE, val); } =20 -static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, - unsigned long cap) -{ - if (cap & BIT(DPU_CTL_ACTIVE_CFG)) { - ops->trigger_flush =3D dpu_hw_ctl_trigger_flush_v1; - ops->setup_intf_cfg =3D dpu_hw_ctl_intf_cfg_v1; - ops->reset_intf_cfg =3D dpu_hw_ctl_reset_intf_cfg_v1; - ops->update_pending_flush_intf =3D - dpu_hw_ctl_update_pending_flush_intf_v1; - - ops->update_pending_flush_periph =3D - dpu_hw_ctl_update_pending_flush_periph_v1; - - ops->update_pending_flush_merge_3d =3D - dpu_hw_ctl_update_pending_flush_merge_3d_v1; - ops->update_pending_flush_wb =3D dpu_hw_ctl_update_pending_flush_wb_v1; - ops->update_pending_flush_cwb =3D dpu_hw_ctl_update_pending_flush_cwb_v1; - ops->update_pending_flush_dsc =3D - dpu_hw_ctl_update_pending_flush_dsc_v1; - ops->update_pending_flush_cdm =3D dpu_hw_ctl_update_pending_flush_cdm_v1; - } else { - ops->trigger_flush =3D dpu_hw_ctl_trigger_flush; - ops->setup_intf_cfg =3D dpu_hw_ctl_intf_cfg; - ops->update_pending_flush_intf =3D - dpu_hw_ctl_update_pending_flush_intf; - ops->update_pending_flush_wb =3D dpu_hw_ctl_update_pending_flush_wb; - ops->update_pending_flush_cdm =3D dpu_hw_ctl_update_pending_flush_cdm; - } - ops->clear_pending_flush =3D dpu_hw_ctl_clear_pending_flush; - ops->update_pending_flush =3D dpu_hw_ctl_update_pending_flush; - ops->get_pending_flush =3D dpu_hw_ctl_get_pending_flush; - ops->get_flush_register =3D dpu_hw_ctl_get_flush_register; - ops->trigger_start =3D dpu_hw_ctl_trigger_start; - ops->is_started =3D dpu_hw_ctl_is_started; - ops->trigger_pending =3D dpu_hw_ctl_trigger_pending; - ops->reset =3D dpu_hw_ctl_reset_control; - ops->wait_reset_status =3D dpu_hw_ctl_wait_reset_status; - ops->clear_all_blendstages =3D dpu_hw_ctl_clear_all_blendstages; - ops->setup_blendstage =3D dpu_hw_ctl_setup_blendstage; - ops->update_pending_flush_sspp =3D dpu_hw_ctl_update_pending_flush_sspp; - ops->update_pending_flush_mixer =3D dpu_hw_ctl_update_pending_flush_mixer; - if (cap & BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) - ops->update_pending_flush_dspp =3D dpu_hw_ctl_update_pending_flush_dspp_= sub_blocks; - else - ops->update_pending_flush_dspp =3D dpu_hw_ctl_update_pending_flush_dspp; - - if (cap & BIT(DPU_CTL_FETCH_ACTIVE)) - ops->set_active_pipes =3D dpu_hw_ctl_set_fetch_pipe_active; -}; - /** * dpu_hw_ctl_init() - Initializes the ctl_path hw driver object. * Should be called before accessing any ctl_path register. @@ -789,7 +739,53 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *= dev, c->hw.log_mask =3D DPU_DBG_MASK_CTL; =20 c->caps =3D cfg; - _setup_ctl_ops(&c->ops, c->caps->features); + + if (c->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) { + c->ops.trigger_flush =3D dpu_hw_ctl_trigger_flush_v1; + c->ops.setup_intf_cfg =3D dpu_hw_ctl_intf_cfg_v1; + c->ops.reset_intf_cfg =3D dpu_hw_ctl_reset_intf_cfg_v1; + c->ops.update_pending_flush_intf =3D + dpu_hw_ctl_update_pending_flush_intf_v1; + + c->ops.update_pending_flush_periph =3D + dpu_hw_ctl_update_pending_flush_periph_v1; + + c->ops.update_pending_flush_merge_3d =3D + dpu_hw_ctl_update_pending_flush_merge_3d_v1; + c->ops.update_pending_flush_wb =3D dpu_hw_ctl_update_pending_flush_wb_v1; + c->ops.update_pending_flush_cwb =3D dpu_hw_ctl_update_pending_flush_cwb_= v1; + c->ops.update_pending_flush_dsc =3D + dpu_hw_ctl_update_pending_flush_dsc_v1; + c->ops.update_pending_flush_cdm =3D dpu_hw_ctl_update_pending_flush_cdm_= v1; + } else { + c->ops.trigger_flush =3D dpu_hw_ctl_trigger_flush; + c->ops.setup_intf_cfg =3D dpu_hw_ctl_intf_cfg; + c->ops.update_pending_flush_intf =3D + dpu_hw_ctl_update_pending_flush_intf; + c->ops.update_pending_flush_wb =3D dpu_hw_ctl_update_pending_flush_wb; + c->ops.update_pending_flush_cdm =3D dpu_hw_ctl_update_pending_flush_cdm; + } + c->ops.clear_pending_flush =3D dpu_hw_ctl_clear_pending_flush; + c->ops.update_pending_flush =3D dpu_hw_ctl_update_pending_flush; + c->ops.get_pending_flush =3D dpu_hw_ctl_get_pending_flush; + c->ops.get_flush_register =3D dpu_hw_ctl_get_flush_register; + c->ops.trigger_start =3D dpu_hw_ctl_trigger_start; + c->ops.is_started =3D dpu_hw_ctl_is_started; + c->ops.trigger_pending =3D dpu_hw_ctl_trigger_pending; + c->ops.reset =3D dpu_hw_ctl_reset_control; + c->ops.wait_reset_status =3D dpu_hw_ctl_wait_reset_status; + c->ops.clear_all_blendstages =3D dpu_hw_ctl_clear_all_blendstages; + c->ops.setup_blendstage =3D dpu_hw_ctl_setup_blendstage; + c->ops.update_pending_flush_sspp =3D dpu_hw_ctl_update_pending_flush_sspp; + c->ops.update_pending_flush_mixer =3D dpu_hw_ctl_update_pending_flush_mix= er; + if (c->caps->features & BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) + c->ops.update_pending_flush_dspp =3D dpu_hw_ctl_update_pending_flush_dsp= p_sub_blocks; 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Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_dsc.c index cec6d4e8baec4d00282465cfd2885d365f835976..c7db917afd27e3daf1e8aad2ad6= 71246bf6c8fbf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c @@ -181,16 +181,6 @@ static void dpu_hw_dsc_bind_pingpong_blk( DPU_REG_WRITE(c, dsc_ctl_offset, mux_cfg); } =20 -static void _setup_dsc_ops(struct dpu_hw_dsc_ops *ops, - unsigned long cap) -{ - ops->dsc_disable =3D dpu_hw_dsc_disable; - ops->dsc_config =3D dpu_hw_dsc_config; - ops->dsc_config_thresh =3D dpu_hw_dsc_config_thresh; - if (cap & BIT(DPU_DSC_OUTPUT_CTRL)) - ops->dsc_bind_pingpong_blk =3D dpu_hw_dsc_bind_pingpong_blk; -}; - /** * dpu_hw_dsc_init() - Initializes the DSC hw driver object. * @dev: Corresponding device for devres management @@ -213,7 +203,12 @@ struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *= dev, =20 c->idx =3D cfg->id; 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Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_dspp.c index 829ca272873e45b122c04bea7da22dc569732e10..0f5a74398e66642fba48c112db4= 1ffc75ae2a79f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c @@ -63,13 +63,6 @@ static void dpu_setup_dspp_pcc(struct dpu_hw_dspp *ctx, DPU_REG_WRITE(&ctx->hw, base, PCC_EN); } =20 -static void _setup_dspp_ops(struct dpu_hw_dspp *c, - unsigned long features) -{ - if (test_bit(DPU_DSPP_PCC, &features)) - c->ops.setup_pcc =3D dpu_setup_dspp_pcc; -} - /** * dpu_hw_dspp_init() - Initializes the DSPP hw driver object. * should be called once before accessing every DSPP. @@ -97,7 +90,8 @@ struct dpu_hw_dspp *dpu_hw_dspp_init(struct drm_device *d= ev, /* Assign ops */ c->idx =3D cfg->id; c->cap =3D cfg; - _setup_dspp_ops(c, c->cap->features); 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Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 24 +++++++++--------------- 1 file changed, 9 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_hw_lm.c index 81b56f066519a68c9e72f0b42df12652139ab83a..4f57cfca89bd3962e7e51295280= 9db0300cb9baf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -144,20 +144,6 @@ static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer= *ctx, DPU_REG_WRITE(c, LM_OP_MODE, op_mode); } =20 -static void _setup_mixer_ops(struct dpu_hw_lm_ops *ops, - unsigned long features) -{ - ops->setup_mixer_out =3D dpu_hw_lm_setup_out; - if (test_bit(DPU_MIXER_COMBINED_ALPHA, &features)) - ops->setup_blend_config =3D dpu_hw_lm_setup_blend_config_combined_alpha; - else - ops->setup_blend_config =3D dpu_hw_lm_setup_blend_config; - ops->setup_alpha_out =3D dpu_hw_lm_setup_color3; - ops->setup_border_color =3D dpu_hw_lm_setup_border_color; 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54e7cb3987csm3852e87.59.2025.04.23.14.10.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Apr 2025 14:10:22 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 24 Apr 2025 00:10:03 +0300 Subject: [PATCH v2 07/33] drm/msm/dpu: remove DSPP_SC7180_MASK Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-dpu-drop-features-v2-7-0a9a66a7b3a2@oss.qualcomm.com> References: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> In-Reply-To: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=25067; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=N2ibSK9AaVQQSoYkm2800cwsnJJzF8hIkM91nNwFHLE=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoCVcrZMtmDP8i8sKB/XAsqCk6rnkU0On9y0l3k /pMJ8SgpmeJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaAlXKwAKCRCLPIo+Aiko 1ePZB/0ZEAUC59XEYL1cs43a87J7CLpCpCP9N0tnKg+0GXaA6U2s1w1Okrt9125ytn7020tQ9+v vSfw2UpygkSh9b6S8Isj5fOgKWrMyjA6eyH3ywt9LdCxrdsGAYppPDNLlO0QcjB4ZB+wYrW3vy5 2/AhV5UPItmQDONw7lnDXadjOZ4xVzSnyeCQLynRigieSzeKgV2oCfQD9WFsr46ojWXrihCuDem xJx50YmZqxnN8/2LGS18bSJm0t4HcjP4VvKIbXS6EXHCuKCYqa3vNVrjRG99yz/qVt5BuXmihOH wOjl4f8WRcm20vLslNl+9+XcYW6HylkdY+2tWN0OI4YV5Tvq X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: QN1puBfj-5aUTcUryMTkSiGrss125Wgc X-Proofpoint-GUID: QN1puBfj-5aUTcUryMTkSiGrss125Wgc X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDIzMDE0NCBTYWx0ZWRfX+Iywaj9I3EkY 81dFkXuiCnH+hqu98A4uWnWRhjNHaoUUR0C/pitds1S1GWfSsQ9AH9D4jrftxIz42k3M/fOHJTi YlZ/gPAcdjwrMrvzfXL0zknncVkyTZL4ykl0PhdDLq8x4MP6y3gMULBXf8AyXWGDyGjhJcClEPL bwFMWicqEVCkCsEsJuGeMEY0DpzfP+12RV+ADNat3xFA/7bS9QDT1QPBsp+lEuB3V9BCTsdg+Xh D3ebQniM/EqcvDXT3p8HvTHIhR7VgLcpHaMFrEDJ/kU+4GDb5AvIzo6Lcukg3EeKVh1wAOFUjLH A+n5X9TP5LV9vQ6xLKR+NJzm9C1g1Z0goMt0WexJTeC9t3wbFHC3ze9tuzGinnDIj3a6VQvT9yw ha4SvdJ65pUpiLHxHFaLhOL3wgI/NYBGIefj+Bnrt7cEmAZSdJsLUzmR5D57TD0yYO/ho8u4 X-Authority-Analysis: v=2.4 cv=Mepsu4/f c=1 sm=1 tr=0 ts=68095755 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=U5TJg58F3aoNapyFlmsA:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.680,FMLib:17.12.80.40 definitions=2025-04-23_11,2025-04-22_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 adultscore=0 lowpriorityscore=0 spamscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 mlxscore=0 impostorscore=0 clxscore=1015 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504230144 From: Dmitry Baryshkov Stop declaring DPU_DSPP_PCC as a part of the DSPP features, use the presence of the PCC sblk to check whether PCC is present in the hardware or not. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c | 2 +- 30 files changed, 1 insertion(+), 69 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index a8b5c5b5a2e8d9d67ee185f00d92feeec42e490f..f7acceba7af1e8ec4b9c0cb52cb= ec60842c73704 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -190,22 +190,18 @@ static const struct dpu_dspp_cfg sm8650_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_1", .id =3D DSPP_1, .base =3D 0x56000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_2", .id =3D DSPP_2, .base =3D 0x58000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_3", .id =3D DSPP_3, .base =3D 0x5a000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h index ad60089f18ea6c22160533874ea0cc54c352e064..78ade3e977108fe98dc63ed9353= 5ae3d947d871b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h @@ -118,7 +118,6 @@ static const struct dpu_dspp_cfg msm8937_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &msm8998_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h index a1cf89a0a42d5f3c909798c30901fe8796b15075..63dd5afdb60b051f6d531257b28= 44920cc09ed80 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h @@ -104,7 +104,6 @@ static const struct dpu_dspp_cfg msm8917_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &msm8998_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h index eea9b80e2287a86448ab4e1a5914c1914d5a2090..4f09d483fbde29c74e3fd9bd0ba= 7a1a9c2638183 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h @@ -118,7 +118,6 @@ static const struct dpu_dspp_cfg msm8953_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &msm8998_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h index ae18a354e5d2a3d2e073f2099e4d970bff5ed085..54477e300c273182172a78b81dd= 0274242689895 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h @@ -223,12 +223,10 @@ static const struct dpu_dspp_cfg msm8996_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &msm8998_dspp_sblk, }, { .name =3D "dspp_1", .id =3D DSPP_1, .base =3D 0x56000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &msm8998_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index 746474679ef5b9ce7ef351e2d5434706d6109d33..9dc84c8dfb64c5f6642fe47ff9a= a9ab16922687f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -212,12 +212,10 @@ static const struct dpu_dspp_cfg msm8998_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &msm8998_dspp_sblk, }, { .name =3D "dspp_1", .id =3D DSPP_1, .base =3D 0x56000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &msm8998_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h index bb89da0a481dec053e06369dee8b0854a3427aaf..5ec81e3eb6c0902113b4ef1bf85= 0b946d0ce4b1b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h @@ -183,12 +183,10 @@ static const struct dpu_dspp_cfg sdm660_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &msm8998_dspp_sblk, }, { .name =3D "dspp_1", .id =3D DSPP_1, .base =3D 0x56000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &msm8998_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h index 7caf876ca3e30cc9230cbc6f19b9d3d1b954e2e0..2a80a881a233f48aa7f0b8a9345= 386eb85e3157d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h @@ -133,7 +133,6 @@ static const struct dpu_dspp_cfg sdm630_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &msm8998_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index ab7b4822ca630f8258bc9eb52c0b967e9bc34d18..968076c5f2211552bec1bd75040= 9e4be57dddeff 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -170,22 +170,18 @@ static const struct dpu_dspp_cfg sdm845_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_1", .id =3D DSPP_1, .base =3D 0x56000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_2", .id =3D DSPP_2, .base =3D 0x58000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_3", .id =3D DSPP_3, .base =3D 0x5a000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h index c2fde980fb521d9259a9f1e3bf88cc81f46fdfe8..3a60432a758a942eb1541f14301= 8bd466b2bdf20 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h @@ -103,12 +103,10 @@ static const struct dpu_dspp_cfg sdm670_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_1", .id =3D DSPP_1, .base =3D 0x56000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index 979527d98fbcb19c33ccb45b5ba4716031949985..7731bd79c135f1f28cc3e5a53bf= 05097cc9f70e9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -194,22 +194,18 @@ static const struct dpu_dspp_cfg sm8150_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_1", .id =3D DSPP_1, .base =3D 0x56000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_2", .id =3D DSPP_2, .base =3D 0x58000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_3", .id =3D DSPP_3, .base =3D 0x5a000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index d76b8992a6c18c21a54eb2a373c789720b876c8b..899a5502229f1321403a27c4431= c10bdbfeeeda8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -193,22 +193,18 @@ static const struct dpu_dspp_cfg sc8180x_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_1", .id =3D DSPP_1, .base =3D 0x56000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_2", .id =3D DSPP_2, .base =3D 0x58000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_3", .id =3D DSPP_3, .base =3D 0x5a000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h index 83db11339b29dc6e11010bfc73f112f93cf6f7c6..830f416c0b5183cb764b2d6381b= dc4a74df0ab0c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h @@ -150,12 +150,10 @@ static const struct dpu_dspp_cfg sm7150_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_1", .id =3D DSPP_1, .base =3D 0x56000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h index da11830d44072666e47b0505e2edc3ae7717eb23..dc6d8fd05c2e3afbe5182b1ae8d= d9fea8b6543e5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h @@ -136,7 +136,6 @@ static const struct dpu_dspp_cfg sm6150_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h index d3d3a34d0b45de08a33436f46a197cc836cf2629..14ecf429e7695c167e85f500b11= 3952ebdbc3aa6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h @@ -117,7 +117,6 @@ static const struct dpu_dspp_cfg sm6125_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 47e01c3c242f9a2ecb201b04be5effd7ff0d04b1..8dab7f63928bb708c79080b1393= 95c3410fd45bf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -192,22 +192,18 @@ static const struct dpu_dspp_cfg sm8250_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_1", .id =3D DSPP_1, .base =3D 0x56000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_2", .id =3D DSPP_2, .base =3D 0x58000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_3", .id =3D DSPP_3, .base =3D 0x5a000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index 040c94c0bb66ef5aaab2808f6f5ee04dd53e2540..f648d19123fa95a1c20074abd4d= d0bda5147ed29 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -106,7 +106,6 @@ static const struct dpu_dspp_cfg sc7180_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index 43f64a005f5a89e09ee9506a12cfff781530cb80..f8164950a0f7721643eabf5cb2b= b7a5e3bcdfbfa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -69,7 +69,6 @@ static const struct dpu_dspp_cfg sm6115_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index 397278ba999b24722b116e73b008b2d0aec5fcb5..ddf05cb3954e12e6689cb579f20= b20e1d220156c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -115,7 +115,6 @@ static const struct dpu_dspp_cfg sm6350_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index 3cbb2fe8aba24c7b9db6bb61ff4c48f34db48bf4..6d424a4fd60bd94ddc0374466d8= 6770138b2831f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -69,7 +69,6 @@ static const struct dpu_dspp_cfg qcm2290_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index a06c8634d2d7779f7e867fb821f8d332652ba7e9..aaf4b270f20dcc5fb91fbcb783c= 6d3bc673894f5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -71,7 +71,6 @@ static const struct dpu_dspp_cfg sm6375_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 93427f7cac3a370fdac3f119134bf9fee8b87a17..6fc6083607403be8ad2287952c9= 9c7bd4d30f2e4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -192,22 +192,18 @@ static const struct dpu_dspp_cfg sm8350_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_1", .id =3D DSPP_1, .base =3D 0x56000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_2", .id =3D DSPP_2, .base =3D 0x58000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_3", .id =3D DSPP_3, .base =3D 0x5a000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 1edec0644b078ac1fff129354d4d02eec015a331..281826170da082fc90a05c64106= 0901ece0fbed3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -117,7 +117,6 @@ static const struct dpu_dspp_cfg sc7280_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 7d698fc354666a2dc468a71ff08cb8df0c37234c..957e92d63f07723c8834bbb6e9c= 5a4d6449999a4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -192,22 +192,18 @@ static const struct dpu_dspp_cfg sc8280xp_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_1", .id =3D DSPP_1, .base =3D 0x56000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_2", .id =3D DSPP_2, .base =3D 0x58000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_3", .id =3D DSPP_3, .base =3D 0x5a000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index ce050c898b9f21e69e5ff967c2af7c2df1e08232..ec0cf30306d2adbd5f07a2b6a6a= 443d29e11f712 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -193,22 +193,18 @@ static const struct dpu_dspp_cfg sm8450_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_1", .id =3D DSPP_1, .base =3D 0x56000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_2", .id =3D DSPP_2, .base =3D 0x58000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_3", .id =3D DSPP_3, .base =3D 0x5a000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index 4291b4f9ce324eb517022eabe3ab6078b1c3a2fb..4bded17f2e371a48a5b21808b9f= 0c55c00efbecf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -192,22 +192,18 @@ static const struct dpu_dspp_cfg sa8775p_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_1", .id =3D DSPP_1, .base =3D 0x56000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_2", .id =3D DSPP_2, .base =3D 0x58000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_3", .id =3D DSPP_3, .base =3D 0x5a000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index a6ab5c49654010194bfc1d4991ffec411ef6e6fd..3907d143056e2513a6a6bdd8aa2= b56f63ac406cb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -190,22 +190,18 @@ static const struct dpu_dspp_cfg sm8550_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_1", .id =3D DSPP_1, .base =3D 0x56000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_2", .id =3D DSPP_2, .base =3D 0x58000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_3", .id =3D DSPP_3, .base =3D 0x5a000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index ad486b03c54d9beb6d77df4d6b5f142fd1dd8d8d..8cbec3741338aba07a780194ae5= 0c162d2087d83 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -189,22 +189,18 @@ static const struct dpu_dspp_cfg x1e80100_dspp[] =3D { { .name =3D "dspp_0", .id =3D DSPP_0, .base =3D 0x54000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_1", .id =3D DSPP_1, .base =3D 0x56000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_2", .id =3D DSPP_2, .base =3D 0x58000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, { .name =3D "dspp_3", .id =3D DSPP_3, .base =3D 0x5a000, .len =3D 0x1800, - .features =3D DSPP_SC7180_MASK, .sblk =3D &sdm845_dspp_sblk, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 671e1ba35d28a20ca3a483bfc6412a8e53c25709..fda429972c35acc1e44c4384cf6= d72d7e9f120eb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -119,8 +119,6 @@ #define CTL_SM8550_MASK \ (CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4)) =20 -#define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC) - #define INTF_SC7180_MASK \ (BIT(DPU_INTF_INPUT_CTRL) | \ BIT(DPU_INTF_STATUS_SUPPORTED) | \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_dspp.c index 0f5a74398e66642fba48c112db41ffc75ae2a79f..11fb1bc54fa92a5d9926addb437= bc4b8f283723b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c @@ -90,7 +90,7 @@ struct dpu_hw_dspp *dpu_hw_dspp_init(struct drm_device *d= ev, /* Assign ops */ c->idx =3D cfg->id; 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Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 5 ++++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 4 ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +- 8 files changed, 27 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index f7acceba7af1e8ec4b9c0cb52cbec60842c73704..922c9c6ebd82cdfc7f948df5900= 91852282c9f64 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -32,32 +32,32 @@ static const struct dpu_ctl_cfg sm8650_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x1000, - .features =3D CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), + .features =3D CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x1000, - .features =3D CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), + .features =3D CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x17000, .len =3D 0x1000, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x18000, .len =3D 0x1000, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x19000, .len =3D 0x1000, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a000, .len =3D 0x1000, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 3907d143056e2513a6a6bdd8aa2b56f63ac406cb..e17345d954f26b234ef6cd65843= e1cb349376ed3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -32,32 +32,32 @@ static const struct dpu_ctl_cfg sm8550_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), + .features =3D CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), + .features =3D CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x17000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x18000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x19000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index 8cbec3741338aba07a780194ae50c162d2087d83..4d37587d6a6374d9e6ed6d8f138= 37aae0ef55c34 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -31,32 +31,32 @@ static const struct dpu_ctl_cfg x1e80100_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), + .features =3D CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), + .features =3D CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x17000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x18000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x19000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a000, .len =3D 0x290, - .features =3D CTL_SM8550_MASK, + .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index fda429972c35acc1e44c4384cf6d72d7e9f120eb..c3b659a12d58e18aaba65ba88ff= 5de131d712412 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -116,9 +116,6 @@ BIT(DPU_CTL_VM_CFG) | \ BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) =20 -#define CTL_SM8550_MASK \ - (CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4)) - #define INTF_SC7180_MASK \ (BIT(DPU_INTF_INPUT_CTRL) | \ BIT(DPU_INTF_STATUS_SUPPORTED) | \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 4cea19e1a20380c56ae014f2d33a6884a72e0ca0..81592cbdd5d234dacc154778492= 382faecfddb39 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -136,7 +136,6 @@ enum { * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs) * @DPU_CTL_VM_CFG: CTL config to support multiple VMs - * @DPU_CTL_HAS_LAYER_EXT4: CTL has the CTL_LAYER_EXT4 register * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush * @DPU_CTL_MAX */ @@ -145,7 +144,6 @@ enum { DPU_CTL_ACTIVE_CFG, DPU_CTL_FETCH_ACTIVE, DPU_CTL_VM_CFG, - DPU_CTL_HAS_LAYER_EXT4, DPU_CTL_DSPP_SUB_BLOCK_FLUSH, DPU_CTL_MAX }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.c index 466bfee3db52d980877a5cdc4eeb739cae250afc..8a7408801bb59e8799e67115ee0= 0cdfe87eba668 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -549,7 +549,7 @@ static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_c= tl *ctx, DPU_REG_WRITE(c, CTL_LAYER_EXT(lm), mixercfg[1]); DPU_REG_WRITE(c, CTL_LAYER_EXT2(lm), mixercfg[2]); DPU_REG_WRITE(c, CTL_LAYER_EXT3(lm), mixercfg[3]); - if ((test_bit(DPU_CTL_HAS_LAYER_EXT4, &ctx->caps->features))) + if (ctx->mdss_ver->core_major_ver >=3D 9) DPU_REG_WRITE(c, CTL_LAYER_EXT4(lm), mixercfg[4]); } =20 @@ -720,12 +720,14 @@ static void dpu_hw_ctl_set_fetch_pipe_active(struct d= pu_hw_ctl *ctx, * @dev: Corresponding device for devres management * @cfg: ctl_path catalog entry for which driver object is required * @addr: mapped register io address of MDP + * @mdss_ver: dpu core's major and minor versions * @mixer_count: Number of mixers in @mixer * @mixer: Pointer to an array of Layer Mixers defined in the catalog */ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev, const struct dpu_ctl_cfg *cfg, void __iomem *addr, + const struct dpu_mdss_version *mdss_ver, u32 mixer_count, const struct dpu_lm_cfg *mixer) { @@ -739,6 +741,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *d= ev, c->hw.log_mask =3D DPU_DBG_MASK_CTL; =20 c->caps =3D cfg; + c->mdss_ver =3D mdss_ver; =20 if (c->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) { c->ops.trigger_flush =3D dpu_hw_ctl_trigger_flush_v1; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.h index 080a9550a0cc6530b4115165dd737857b6213d15..aa560df698ed4e57a25e4a893d7= 333e19b065fe8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -272,6 +272,7 @@ struct dpu_hw_ctl_ops { * @pending_cwb_flush_mask: pending CWB flush * @pending_dsc_flush_mask: pending DSC flush * @pending_cdm_flush_mask: pending CDM flush + * @mdss_ver: MDSS revision information * @ops: operation list */ struct dpu_hw_ctl { @@ -293,6 +294,8 @@ struct dpu_hw_ctl { u32 pending_dsc_flush_mask; u32 pending_cdm_flush_mask; =20 + const struct dpu_mdss_version *mdss_ver; + /* ops */ struct dpu_hw_ctl_ops ops; }; @@ -310,6 +313,7 @@ static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct d= pu_hw_blk *hw) struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev, const struct dpu_ctl_cfg *cfg, void __iomem *addr, + const struct dpu_mdss_version *mdss_ver, u32 mixer_count, const struct dpu_lm_cfg *mixer); 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54e7cb3987csm3852e87.59.2025.04.23.14.10.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Apr 2025 14:10:28 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 24 Apr 2025 00:10:05 +0300 Subject: [PATCH v2 09/33] drm/msm/dpu: get rid of DPU_CTL_ACTIVE_CFG Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-dpu-drop-features-v2-9-0a9a66a7b3a2@oss.qualcomm.com> References: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> In-Reply-To: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=18958; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=ZNJ38EuFTkNMEqkAwQ+8h/9Btpclakp0rdOuryipKi8=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoCVcroAgdHrwmzbhWatxh9rL9FyfcLKVWW2PSn HLXJR1LJkCJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaAlXKwAKCRCLPIo+Aiko 1ZsSB/9BU3PYf8Rs/KEbmk2HXK5+dP3L1dn0YwOi+G3wmzFwt/xki7kUh2r8va2eYlxMu3Bcey2 KCb2g8XTYxpFzDXy8bqiMEQotjrL8J/Ctr64LoskAnRtWfE1zb0SNZmtPNvYfYsusN4FCGQtIER P+riSS5rrvcz9mJ1Qe9+MS1dCYFNIaGhD5xVbvV89cRAxJiZnzwalodzfkINMzVgejcvrtr++hc igGEXMrRkX00UCBSt7rDVpN33ZBgREZQ/v/huq9cg3gYtjGrdtmuP0Xap/q5I6vwS+TMq0RkTdX LshU4xOwNKVV8wLUhTkro8dQ/7HT+48XoMjePo34YqK34YYJ X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: OEVUeGkYVAYlGhB4aerHNqj2G7yD5eai X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDIzMDE0NCBTYWx0ZWRfX28mh6updjvxf XNdku66rZDPzxG4wov6YaAhVk4sRBjpWKH5axXeIxDpPp6fJEHWErQZHMiN7Thgk43iia8sTqHg RdVeoanshNVodGLWOvql+9npKRGyGp9mpWSbIoCaOb+7WlPJmQ1iJ9oRhirhchjFtOrmWyUL2Dk vgJ6mybOQCoW9QHpXp2tEtHasGzjyXAXGPRwadYtpDrLthqIeQcUlqDNl+ShaSQza20Jy3joR7Q 6j86wne1R0OCw2frPggp0J7rrZuWFUr6XD1cH/UqWasUbeebPcfPz4nUNWZpXw7UgCWZTOo+T2a hFR30vlUdFrY4/yLskhlmFfXIFgRxsDElLkEFo1nB7elyk/G17jYIPnWGps5g+mwLzPT0PF1vZs PnP3TtUsh5+iM4y5pcEnkHNWS0SgudXcYKCT7ctKMHt78z80aFQbjzhVwKx4Ri0Czo1pcRBt X-Authority-Analysis: v=2.4 cv=ELgG00ZC c=1 sm=1 tr=0 ts=68095757 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=QkM7UoOa6lEXaYzOGzoA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: OEVUeGkYVAYlGhB4aerHNqj2G7yD5eai X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.680,FMLib:17.12.80.40 definitions=2025-04-23_11,2025-04-22_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 malwarescore=0 clxscore=1015 bulkscore=0 phishscore=0 spamscore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504230144 From: Dmitry Baryshkov Continue migration to the MDSS-revision based checks and replace DPU_CTL_ACTIVE_CFG feature bit with the core_major_ver >=3D 5 check. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 8 ++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 8 ++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 8 ++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 6 ------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 6 ------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 8 ++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 3 --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 7 ++----- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +- 16 files changed, 13 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index 7731bd79c135f1f28cc3e5a53bf05097cc9f70e9..3bb0749f931d7417f8e90bfe373= 6ce77dafccb57 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -42,32 +42,28 @@ static const struct dpu_ctl_cfg sm8150_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x1000, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x1200, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x1400, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x1600, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x1800, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a00, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index 899a5502229f1321403a27c4431c10bdbfeeeda8..84114df5f072af16aeedd3aada8= a106ca4369ddb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -41,32 +41,28 @@ static const struct dpu_ctl_cfg sc8180x_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x1000, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x1200, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x1400, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x1600, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x1800, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a00, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h index 830f416c0b5183cb764b2d6381bdc4a74df0ab0c..7a04eacb108bea33573cf75fb55= 37b80e8273039 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h @@ -38,32 +38,28 @@ static const struct dpu_ctl_cfg sm7150_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x1000, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x1200, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x1400, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x1600, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x1800, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a00, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h index dc6d8fd05c2e3afbe5182b1ae8dd9fea8b6543e5..d44db988a6e2f443803a422846f= 817779d382b2a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h @@ -35,32 +35,26 @@ static const struct dpu_ctl_cfg sm6150_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x1000, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x1200, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x1400, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x1600, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x1800, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a00, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h index 14ecf429e7695c167e85f500b113952ebdbc3aa6..ba631cdbbff0cec7453685bc102= 8791eadbbb2d4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h @@ -35,32 +35,26 @@ static const struct dpu_ctl_cfg sm6125_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x1000, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x1200, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x1400, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x1600, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x1800, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a00, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 8dab7f63928bb708c79080b139395c3410fd45bf..5f7bee25a7a4f80d1f2fb86f126= 863b721c41281 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -40,32 +40,28 @@ static const struct dpu_ctl_cfg sm8250_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x1000, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x1200, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x1400, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x1600, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x1800, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a00, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index f648d19123fa95a1c20074abd4dd0bda5147ed29..0ede8223a3a85414f271de11b60= 1b648ca865fbe 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -32,17 +32,14 @@ static const struct dpu_ctl_cfg sc7180_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x1000, .len =3D 0x1dc, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x1200, .len =3D 0x1dc, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x1400, .len =3D 0x1dc, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index f8164950a0f7721643eabf5cb2bb7a5e3bcdfbfa..01e398add3c45a8bc504da5ca26= 8df0487462113 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -29,7 +29,6 @@ static const struct dpu_ctl_cfg sm6115_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x1000, .len =3D 0x1dc, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index ddf05cb3954e12e6689cb579f20b20e1d220156c..da04822327975aa70cab679f5e5= 3d53f65fb749c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -35,22 +35,18 @@ static const struct dpu_ctl_cfg sm6350_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x1000, .len =3D 0x1dc, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x1200, .len =3D 0x1dc, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x1400, .len =3D 0x1dc, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x1600, .len =3D 0x1dc, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index 6d424a4fd60bd94ddc0374466d86770138b2831f..94dc8726199a3a48a64c7dff58b= c62e6fd097c99 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -29,7 +29,6 @@ static const struct dpu_ctl_cfg qcm2290_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x1000, .len =3D 0x1dc, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index aaf4b270f20dcc5fb91fbcb783c6d3bc673894f5..2b2b9417e23950425a72f6dd44b= af824b5a00061 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -30,7 +30,6 @@ static const struct dpu_ctl_cfg sm6375_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x1000, .len =3D 0x1dc, - .features =3D BIT(DPU_CTL_ACTIVE_CFG), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers= /gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index da9994a79ca293ec0265680c438835742102db2a..9d0b6397acbd41cc7c93df040be= 5c248b7ad3c05 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -67,7 +67,7 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( ctl->ops.setup_intf_cfg(ctl, &intf_cfg); =20 /* setup which pp blk will connect to this intf */ - if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) && phys_enc->hw_in= tf->ops.bind_pingpong_blk) + if (phys_enc->hw_intf->ops.bind_pingpong_blk) phys_enc->hw_intf->ops.bind_pingpong_blk( phys_enc->hw_intf, phys_enc->hw_pp->idx); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/= gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c index 849fea580a4ca55fc4a742c6b6dee7dfcdd788e4..c8f3516ae4faa709e3eda4c0efb= 050ca18b675e4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c @@ -218,7 +218,6 @@ static void dpu_encoder_phys_wb_setup_fb(struct dpu_enc= oder_phys *phys_enc, static void dpu_encoder_phys_wb_setup_ctl(struct dpu_encoder_phys *phys_en= c) { struct dpu_hw_wb *hw_wb; - struct dpu_hw_ctl *ctl; struct dpu_hw_cdm *hw_cdm; =20 if (!phys_enc) { @@ -227,10 +226,9 @@ static void dpu_encoder_phys_wb_setup_ctl(struct dpu_e= ncoder_phys *phys_enc) } =20 hw_wb =3D phys_enc->hw_wb; - ctl =3D phys_enc->hw_ctl; hw_cdm =3D phys_enc->hw_cdm; =20 - if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) && + if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >=3D 5 && (phys_enc->hw_ctl && phys_enc->hw_ctl->ops.setup_intf_cfg)) { struct dpu_hw_intf_cfg intf_cfg =3D {0}; @@ -534,7 +532,6 @@ static void dpu_encoder_phys_wb_enable(struct dpu_encod= er_phys *phys_enc) static void dpu_encoder_phys_wb_disable(struct dpu_encoder_phys *phys_enc) { struct dpu_hw_wb *hw_wb =3D phys_enc->hw_wb; - struct dpu_hw_ctl *hw_ctl =3D phys_enc->hw_ctl; =20 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0); =20 @@ -556,7 +553,7 @@ static void dpu_encoder_phys_wb_disable(struct dpu_enco= der_phys *phys_enc) * WB support is added to those targets will need to add * the legacy teardown sequence as well. */ - if (hw_ctl->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) + if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >=3D 5) dpu_encoder_helper_phys_cleanup(phys_enc); =20 phys_enc->enable_state =3D DPU_ENC_DISABLED; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index c3b659a12d58e18aaba65ba88ff5de131d712412..0fcc9fb975c0955f459ba4264b6= a114a4b17af52 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -111,8 +111,7 @@ (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) =20 #define CTL_SC7280_MASK \ - (BIT(DPU_CTL_ACTIVE_CFG) | \ - BIT(DPU_CTL_FETCH_ACTIVE) | \ + (BIT(DPU_CTL_FETCH_ACTIVE) | \ BIT(DPU_CTL_VM_CFG) | \ BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 81592cbdd5d234dacc154778492382faecfddb39..b6c45ed4fa3d18ed21c2a2547b0= d5af4debd974e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -141,7 +141,6 @@ enum { */ enum { DPU_CTL_SPLIT_DISPLAY =3D 0x1, - DPU_CTL_ACTIVE_CFG, DPU_CTL_FETCH_ACTIVE, DPU_CTL_VM_CFG, DPU_CTL_DSPP_SUB_BLOCK_FLUSH, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.c index 8a7408801bb59e8799e67115ee00cdfe87eba668..c63a6cbd07d94acae04b6edf534= b1a7f5d4119b1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -743,7 +743,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *d= ev, c->caps =3D cfg; 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54e7cb3987csm3852e87.59.2025.04.23.14.10.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Apr 2025 14:10:30 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 24 Apr 2025 00:10:06 +0300 Subject: [PATCH v2 10/33] drm/msm/dpu: get rid of DPU_CTL_FETCH_ACTIVE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-dpu-drop-features-v2-10-0a9a66a7b3a2@oss.qualcomm.com> References: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> In-Reply-To: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2516; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=DsDYyaEtmcEU0Q3DXm3LKbekIuXiOgkLRrmoNbxq0Rs=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoCVcrYuy68P+aFAst+64lDjz2r1QUnWPTC/ioG m+VsW9g8O2JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaAlXKwAKCRCLPIo+Aiko 1ZXFB/9Tg6zrWMlR/btCGy5hpZnnysbbj2S9t0oeK+N1SVTNATupVvE0v0ItHeJ/ukwiUP70xXl OX8fMKWtnEKpN5vpzpunp2YYa7Ylow/QePSZeT0eNE8C2gAZM1aVqftxmR6QirQFUyetFTJcJ44 H/sB40DGQeNdbu1YC+/NyqHiuerWa6ETpeLZ6qpifvKPmeGPRo5vYdIMk+tFBbfuDAs/ZJxCNUM mqgfXWEFuQbZwcCZuwnjj+ZRK01h5lSFMvqvq7ag1yio8TrY/WsjA3qaa4Iswj28PqdAPm7kKPW DuSr3Jssa0YqGaQPXyhrBLugW4nVAnHe/rPK4i86wJXtqpo/ X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDIzMDE0NCBTYWx0ZWRfX4W/52wUa+CJc CRz+4zXggtnrbDOi6TfVow5cUreLef4SabdjrYUX29Rn5e7AeUNEeSNPLscR+9r/XGzgODGY6r2 sKmeZJoA2TkU1VN7ePS4O3KBfQZWaTLYmv0WZpiA7zzU0+sPwPIIFnolaVAMlkWlPw8lHajvX+q gj8zYVrdVI/Hbk5STWwFo63HWBq120l0YC7yEVN9gDSZccSoHW6q8gOYPiQeR4QAtAXiKcphSMt DaubhkG4rO4m6eiAn9A7JlQH4T9akZ9VXU5hnE2VkkipukI+9/zuwtf6QFv1o0HmQnAzrv6wUhb wUAjDIyBPoS4EWPLe4jFmEQi6RtimSE9VmSwTt1OONNEDgrxRItOc6ed5DskRa5FGNTX9L5xn1I UgcOXw4j/Lc/JaD3+AnVaUFNwKWEv48ZpGHqSBYB3C6Og0I/zTXKUNNrM9C0lV2Z6jAh1NaS X-Authority-Analysis: v=2.4 cv=bs1MBFai c=1 sm=1 tr=0 ts=68095754 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=k2A94KsD3O5M_qN9siwA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: NEd983X_h5foyLQ_2AEh2SLBPHTaqIxv X-Proofpoint-GUID: NEd983X_h5foyLQ_2AEh2SLBPHTaqIxv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.680,FMLib:17.12.80.40 definitions=2025-04-23_11,2025-04-22_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 suspectscore=0 mlxlogscore=899 mlxscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 impostorscore=0 malwarescore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504230144 From: Dmitry Baryshkov Continue migration to the MDSS-revision based checks and replace DPU_CTL_FETCH_ACTIVE feature bit with the core_major_ver >=3D 7 check. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +- 3 files changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 0fcc9fb975c0955f459ba4264b6a114a4b17af52..3431b3c956486aee99664ea9b7c= 2e00f5c130b7f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -111,8 +111,7 @@ (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) =20 #define CTL_SC7280_MASK \ - (BIT(DPU_CTL_FETCH_ACTIVE) | \ - BIT(DPU_CTL_VM_CFG) | \ + (BIT(DPU_CTL_VM_CFG) | \ BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) =20 #define INTF_SC7180_MASK \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index b6c45ed4fa3d18ed21c2a2547b0d5af4debd974e..ae168e73026d8ebbe605397c6bb= d95552193498c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -134,14 +134,12 @@ enum { /** * CTL sub-blocks * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display - * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs) * @DPU_CTL_VM_CFG: CTL config to support multiple VMs * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush * @DPU_CTL_MAX */ enum { DPU_CTL_SPLIT_DISPLAY =3D 0x1, - DPU_CTL_FETCH_ACTIVE, DPU_CTL_VM_CFG, DPU_CTL_DSPP_SUB_BLOCK_FLUSH, DPU_CTL_MAX diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.c index c63a6cbd07d94acae04b6edf534b1a7f5d4119b1..593da532d40042ca31fb452679d= 3de04c3b0d1a7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -786,7 +786,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *d= ev, else c->ops.update_pending_flush_dspp =3D dpu_hw_ctl_update_pending_flush_dsp= p; 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Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +- 3 files changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 3431b3c956486aee99664ea9b7c2e00f5c130b7f..a2dc353151f3e1a4cb8a9f4644e= 7fc2e037356a2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -111,8 +111,7 @@ (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) =20 #define CTL_SC7280_MASK \ - (BIT(DPU_CTL_VM_CFG) | \ - BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH)) + (BIT(DPU_CTL_VM_CFG)) =20 #define INTF_SC7180_MASK \ (BIT(DPU_INTF_INPUT_CTRL) | \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index ae168e73026d8ebbe605397c6bbd95552193498c..1c6be8f93b54f28d370a379d1ed= ccd178fe3cf7b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -135,13 +135,11 @@ enum { * CTL sub-blocks * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display * @DPU_CTL_VM_CFG: CTL config to support multiple VMs - * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush * @DPU_CTL_MAX */ enum { DPU_CTL_SPLIT_DISPLAY =3D 0x1, DPU_CTL_VM_CFG, - DPU_CTL_DSPP_SUB_BLOCK_FLUSH, DPU_CTL_MAX }; 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54e7cb3987csm3852e87.59.2025.04.23.14.10.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Apr 2025 14:10:34 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 24 Apr 2025 00:10:08 +0300 Subject: [PATCH v2 12/33] drm/msm/dpu: get rid of DPU_CTL_VM_CFG Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-dpu-drop-features-v2-12-0a9a66a7b3a2@oss.qualcomm.com> References: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> In-Reply-To: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=15065; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=47KdKwzl6eJzgTGC1PmI4bMv2JSspbmc7E5cJjyGADw=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoCVcrj4H/9vgx8RDlqmDBtOgR/Z79pVvO5CMPI ToKAyR8MGuJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaAlXKwAKCRCLPIo+Aiko 1YPKB/4mwyvTxeKUS3DrSHFcJmt2qaBm/7qEzrakKoCHi7mLcujbsh/dWONGKJItujYwyICdlwr 8MQBRLBHaovNQ6CP3SV7VjQZKpEgKbIVWkH7fyvBHg8gvXMKgM0uO20ZT0UhtYgt+rHe56q2Dra rYnlx8bKg2CBitv0hcgb6x8rlZB4pDug2XZcLxoQ4DO4IWEKfm+vkk5rPu7OvfXiZR3+f+KcXBI +ecuhAuJGmhfuPoRrXcM04AoV6IE6Zu00vHsdNVVBuSv00LpUdovJRYRTbqM1ZDkJz7a110jDJ4 3IiDfYkP2j1mh+wnHypMTCXP7z5of231L1OaGclaorkCibKQ X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: tYupTA-Odn2FlO3fxdb3jenb-WY7vbcm X-Authority-Analysis: v=2.4 cv=OY6YDgTY c=1 sm=1 tr=0 ts=68095758 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=2tDT8zELnxangoEIUYcA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: tYupTA-Odn2FlO3fxdb3jenb-WY7vbcm X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDIzMDE0NCBTYWx0ZWRfX8YhpkQnybE+N lFOvVpJjV9YtEEDEgh+8ZhEcpLO80RoOLotp5bamekej5ZWXrexmEmpvc3bc3X1Rztt3fhWW9jV TCvz2icOZNvdifYQ8zViDDfcUc14fyqwBZg1d8j8Z2qbs52IXA3vz+ICzgQKd2EoT3TFpWpFRNz +T0H6fU1crFiwqv03Hf0wCImybzrapZ9Nsmn35k24tS//WzIzAkSFwQsDiiAiQCPPSOTiZ8PQfV nNRRsCWiWWxQIPOcIti+u/3fgAy4RgXvwu2vt6WWAZriPmAtqEjuQSYMmzS3kMibagK/em0bHVz FBGYnI33QrofR8yNn4nQrUkyPjo+79SscWZSL3x1Na95+C1+YksI0gbLKL3LBZsAGbbjddb/ZgA omWDTNHhUrEydBTKAxNRo7G2+3OIzq/F1atoXg+daxILivwmiuYjQzWh8g2f09KOebCBuY7C X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.680,FMLib:17.12.80.40 definitions=2025-04-23_11,2025-04-22_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 mlxscore=0 clxscore=1015 malwarescore=0 mlxlogscore=999 phishscore=0 priorityscore=1501 spamscore=0 adultscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504230144 From: Dmitry Baryshkov Continue migration to the MDSS-revision based checks and replace DPU_CTL_VM_CFG feature bit with the core_major_ver >=3D 7 check. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 8 ++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 8 ++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 8 ++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 8 ++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 8 ++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 8 ++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 8 ++------ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +- 11 files changed, 15 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index 922c9c6ebd82cdfc7f948df590091852282c9f64..4ab361b7c977c2c97927543154d= 5dcd00091879c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -32,32 +32,28 @@ static const struct dpu_ctl_cfg sm8650_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x1000, - .features =3D CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x1000, - .features =3D CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x17000, .len =3D 0x1000, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x18000, .len =3D 0x1000, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x19000, .len =3D 0x1000, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a000, .len =3D 0x1000, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 6fc6083607403be8ad2287952c99c7bd4d30f2e4..490ddf9880103fc853b5187256c= 4b960739820bc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -40,32 +40,28 @@ static const struct dpu_ctl_cfg sm8350_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x1e8, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x1e8, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x17000, .len =3D 0x1e8, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x18000, .len =3D 0x1e8, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x19000, .len =3D 0x1e8, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a000, .len =3D 0x1e8, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 281826170da082fc90a05c641060901ece0fbed3..2ee29c56224596b378610409029= 0b88cecf7b223 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -32,22 +32,18 @@ static const struct dpu_ctl_cfg sc7280_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x1e8, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x1e8, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x17000, .len =3D 0x1e8, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x18000, .len =3D 0x1e8, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 957e92d63f07723c8834bbb6e9c5a4d6449999a4..dac38e0ade971876c2ed73b6d46= cd4055cb77d2d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -40,32 +40,28 @@ static const struct dpu_ctl_cfg sc8280xp_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x204, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x204, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x17000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x18000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x19000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index ec0cf30306d2adbd5f07a2b6a6a443d29e11f712..db332286a0a92cfda434571a2a5= 82c45460e5300 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -41,32 +41,28 @@ static const struct dpu_ctl_cfg sm8450_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x204, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x204, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x17000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x18000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x19000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index 4bded17f2e371a48a5b21808b9f0c55c00efbecf..826cd366495139e0e4cf1862e92= 3ef0ece0d7184 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -40,32 +40,28 @@ static const struct dpu_ctl_cfg sa8775p_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x204, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x204, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x17000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x18000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x19000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a000, .len =3D 0x204, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index e17345d954f26b234ef6cd65843e1cb349376ed3..f5f018381b4f0f59c2751b18528= 994ff79555d58 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -32,32 +32,28 @@ static const struct dpu_ctl_cfg sm8550_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x17000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x18000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x19000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index 4d37587d6a6374d9e6ed6d8f13837aae0ef55c34..ecda48282f52e0fc33b68117650= b9f2b76c90276 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -31,32 +31,28 @@ static const struct dpu_ctl_cfg x1e80100_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), + .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x17000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, .base =3D 0x18000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name =3D "ctl_4", .id =3D CTL_4, .base =3D 0x19000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, { .name =3D "ctl_5", .id =3D CTL_5, .base =3D 0x1a000, .len =3D 0x290, - .features =3D CTL_SC7280_MASK, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index a2dc353151f3e1a4cb8a9f4644e7fc2e037356a2..22ca093419059600f0ad7e1e7a0= a4e443b977860 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -110,9 +110,6 @@ #define PINGPONG_SM8150_MASK \ (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) =20 -#define CTL_SC7280_MASK \ - (BIT(DPU_CTL_VM_CFG)) - #define INTF_SC7180_MASK \ (BIT(DPU_INTF_INPUT_CTRL) | \ BIT(DPU_INTF_STATUS_SUPPORTED) | \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 1c6be8f93b54f28d370a379d1edccd178fe3cf7b..27422a5a340b90ee02f36a87cf1= bab9d97504c76 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -134,12 +134,10 @@ enum { /** * CTL sub-blocks * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display - * @DPU_CTL_VM_CFG: CTL config to support multiple VMs * @DPU_CTL_MAX */ enum { DPU_CTL_SPLIT_DISPLAY =3D 0x1, - DPU_CTL_VM_CFG, DPU_CTL_MAX }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.c index 543fe12252b7887ce2bd28abafac3be7caf17ac4..7f6c548b626dbc5bcc3ddb27f18= 5f336354dcb37 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -568,7 +568,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *c= tx, * per VM. Explicitly disable it until VM support is * added in SW. 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Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 2 +- 3 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 22ca093419059600f0ad7e1e7a0a4e443b977860..20f4700ef9969003cfa4728049b= 9737cb9eb6229 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -112,8 +112,7 @@ =20 #define INTF_SC7180_MASK \ (BIT(DPU_INTF_INPUT_CTRL) | \ - BIT(DPU_INTF_STATUS_SUPPORTED) | \ - BIT(DPU_DATA_HCTL_EN)) + BIT(DPU_INTF_STATUS_SUPPORTED)) =20 #define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \ BIT(DPU_WB_UBWC) | \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 27422a5a340b90ee02f36a87cf1bab9d97504c76..36100e21135fba09fcafdd5d36a= c919cd17f63c0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -145,14 +145,11 @@ enum { * INTF sub-blocks * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from = which * pixel data arrives to this INTF - * @DPU_DATA_HCTL_EN Allows data to be transferred at diffe= rent rate - * than video timing * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register * @DPU_INTF_MAX */ enum { DPU_INTF_INPUT_CTRL =3D 0x1, - DPU_DATA_HCTL_EN, DPU_INTF_STATUS_SUPPORTED, DPU_INTF_MAX }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_intf.c index 1d56c21ac79095ab515aeb485346e1eb5793c260..8f9733aad2dec3a9b5464d55b00= f350348842911 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -237,7 +237,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_= hw_intf *intf, DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3); DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg); DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format); - if (intf->cap->features & BIT(DPU_DATA_HCTL_EN)) { + if (intf->mdss_ver->core_major_ver >=3D 5) { /* * DATA_HCTL_EN controls data timing which can be different from * video timing. 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Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 3 +-- 3 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 20f4700ef9969003cfa4728049b9737cb9eb6229..8808be27593b303a2a199a74082= 7c92ea5339b0d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -111,8 +111,7 @@ (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) =20 #define INTF_SC7180_MASK \ - (BIT(DPU_INTF_INPUT_CTRL) | \ - BIT(DPU_INTF_STATUS_SUPPORTED)) + (BIT(DPU_INTF_INPUT_CTRL)) =20 #define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \ BIT(DPU_WB_UBWC) | \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 36100e21135fba09fcafdd5d36ac919cd17f63c0..858fd73e0ac3a92fe402001d479= 6eb86945f61b0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -145,12 +145,10 @@ enum { * INTF sub-blocks * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from = which * pixel data arrives to this INTF - * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register * @DPU_INTF_MAX */ enum { DPU_INTF_INPUT_CTRL =3D 0x1, - DPU_INTF_STATUS_SUPPORTED, DPU_INTF_MAX }; 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Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 6 ------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 3 --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 3 --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 9 --------- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 8 -------- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 9 --------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 11 ----------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 2 +- 22 files changed, 1 insertion(+), 90 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index 4ab361b7c977c2c97927543154d5dcd00091879c..70c519b923f57f2ccae094eedf0= 3c4f313062de8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -367,7 +367,6 @@ static const struct dpu_intf_cfg sm8650_intf[] =3D { { .name =3D "intf_0", .id =3D INTF_0, .base =3D 0x34000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -376,7 +375,6 @@ static const struct dpu_intf_cfg sm8650_intf[] =3D { }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x35000, .len =3D 0x300, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -386,7 +384,6 @@ static const struct dpu_intf_cfg sm8650_intf[] =3D { }, { .name =3D "intf_2", .id =3D INTF_2, .base =3D 0x36000, .len =3D 0x300, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, @@ -396,7 +393,6 @@ static const struct dpu_intf_cfg sm8650_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x37000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index 3bb0749f931d7417f8e90bfe3736ce77dafccb57..6438a5a14e4b89462873b5c8177= 13b4ff67d7ccc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -304,7 +304,6 @@ static const struct dpu_intf_cfg sm8150_intf[] =3D { { .name =3D "intf_0", .id =3D INTF_0, .base =3D 0x6a000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -313,7 +312,6 @@ static const struct dpu_intf_cfg sm8150_intf[] =3D { }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x6a800, .len =3D 0x2bc, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -323,7 +321,6 @@ static const struct dpu_intf_cfg sm8150_intf[] =3D { }, { .name =3D "intf_2", .id =3D INTF_2, .base =3D 0x6b000, .len =3D 0x2bc, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, @@ -333,7 +330,6 @@ static const struct dpu_intf_cfg sm8150_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x6b800, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index 84114df5f072af16aeedd3aada8a106ca4369ddb..d08799471b85a882ecb151cb9b5= be2a098bfc003 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -311,7 +311,6 @@ static const struct dpu_intf_cfg sc8180x_intf[] =3D { { .name =3D "intf_0", .id =3D INTF_0, .base =3D 0x6a000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -320,7 +319,6 @@ static const struct dpu_intf_cfg sc8180x_intf[] =3D { }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x6a800, .len =3D 0x2bc, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -330,7 +328,6 @@ static const struct dpu_intf_cfg sc8180x_intf[] =3D { }, { .name =3D "intf_2", .id =3D INTF_2, .base =3D 0x6b000, .len =3D 0x2bc, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, @@ -342,7 +339,6 @@ static const struct dpu_intf_cfg sc8180x_intf[] =3D { { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x6b800, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D 999, .prog_fetch_lines_worst_case =3D 24, @@ -351,7 +347,6 @@ static const struct dpu_intf_cfg sc8180x_intf[] =3D { }, { .name =3D "intf_4", .id =3D INTF_4, .base =3D 0x6c000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, @@ -360,7 +355,6 @@ static const struct dpu_intf_cfg sc8180x_intf[] =3D { }, { .name =3D "intf_5", .id =3D INTF_5, .base =3D 0x6c800, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_2, .prog_fetch_lines_worst_case =3D 24, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h index 7a04eacb108bea33573cf75fb5537b80e8273039..acaa0b85ed1edd970dd17ae4d8d= 06a3dee6e8083 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h @@ -212,7 +212,6 @@ static const struct dpu_intf_cfg sm7150_intf[] =3D { { .name =3D "intf_0", .id =3D INTF_0, .base =3D 0x6a000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -221,7 +220,6 @@ static const struct dpu_intf_cfg sm7150_intf[] =3D { }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x6a800, .len =3D 0x2bc, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -231,7 +229,6 @@ static const struct dpu_intf_cfg sm7150_intf[] =3D { }, { .name =3D "intf_2", .id =3D INTF_2, .base =3D 0x6b000, .len =3D 0x2bc, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, @@ -241,7 +238,6 @@ static const struct dpu_intf_cfg sm7150_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x6b800, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h index d44db988a6e2f443803a422846f817779d382b2a..a99c99ca37703cc3a7d4403d3f0= 26f234b693319 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h @@ -175,7 +175,6 @@ static const struct dpu_intf_cfg sm6150_intf[] =3D { { .name =3D "intf_0", .id =3D INTF_0, .base =3D 0x6a000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -184,7 +183,6 @@ static const struct dpu_intf_cfg sm6150_intf[] =3D { }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x6a800, .len =3D 0x2c0, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -194,7 +192,6 @@ static const struct dpu_intf_cfg sm6150_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x6b800, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h index ba631cdbbff0cec7453685bc1028791eadbbb2d4..0dce5292fdfe7988504d51d701d= 3908adf9b596a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h @@ -152,7 +152,6 @@ static const struct dpu_intf_cfg sm6125_intf[] =3D { { .name =3D "intf_0", .id =3D INTF_0, .base =3D 0x6a000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -161,7 +160,6 @@ static const struct dpu_intf_cfg sm6125_intf[] =3D { }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x6a800, .len =3D 0x2c0, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D 0, .prog_fetch_lines_worst_case =3D 24, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 5f7bee25a7a4f80d1f2fb86f126863b721c41281..6fce6d382c959b7ae47591f52dd= 06bcf241ff4e2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -287,7 +287,6 @@ static const struct dpu_intf_cfg sm8250_intf[] =3D { { .name =3D "intf_0", .id =3D INTF_0, .base =3D 0x6a000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -296,7 +295,6 @@ static const struct dpu_intf_cfg sm8250_intf[] =3D { }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x6a800, .len =3D 0x2c0, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -306,7 +304,6 @@ static const struct dpu_intf_cfg sm8250_intf[] =3D { }, { .name =3D "intf_2", .id =3D INTF_2, .base =3D 0x6b000, .len =3D 0x2c0, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, @@ -316,7 +313,6 @@ static const struct dpu_intf_cfg sm8250_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x6b800, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index 0ede8223a3a85414f271de11b601b648ca865fbe..52b674fed71e57f82b778c13f67= 12a52a2a425a7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -129,7 +129,6 @@ static const struct dpu_intf_cfg sc7180_intf[] =3D { { .name =3D "intf_0", .id =3D INTF_0, .base =3D 0x6a000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -138,7 +137,6 @@ static const struct dpu_intf_cfg sc7180_intf[] =3D { }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x6a800, .len =3D 0x2c0, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index 01e398add3c45a8bc504da5ca268df0487462113..0178ce52e84f355919241435f58= c390234c16162 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -87,7 +87,6 @@ static const struct dpu_intf_cfg sm6115_intf[] =3D { { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x6a800, .len =3D 0x2c0, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index da04822327975aa70cab679f5e53d53f65fb749c..89db83a73bbeb15b99ac4324b76= 85baf0d724039 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -160,7 +160,6 @@ static const struct dpu_intf_cfg sm6350_intf[] =3D { { .name =3D "intf_0", .id =3D INTF_0, .base =3D 0x6a000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 35, @@ -169,7 +168,6 @@ static const struct dpu_intf_cfg sm6350_intf[] =3D { }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x6a800, .len =3D 0x2c0, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 35, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index 94dc8726199a3a48a64c7dff58bc62e6fd097c99..0b1740de2bff94f1818ab41c6bc= 713f16796c4a4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -87,7 +87,6 @@ static const struct dpu_intf_cfg qcm2290_intf[] =3D { { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x6a800, .len =3D 0x2c0, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index 2b2b9417e23950425a72f6dd44baf824b5a00061..19800f207bff3077c7ac57ad736= eea533674ae20 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -97,7 +97,6 @@ static const struct dpu_intf_cfg sm6375_intf[] =3D { { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x6a800, .len =3D 0x2c0, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 490ddf9880103fc853b5187256c4b960739820bc..94a9f33f008a13db09764882cb0= 42f71337b89d5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -311,7 +311,6 @@ static const struct dpu_intf_cfg sm8350_intf[] =3D { { .name =3D "intf_0", .id =3D INTF_0, .base =3D 0x34000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -320,7 +319,6 @@ static const struct dpu_intf_cfg sm8350_intf[] =3D { }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x35000, .len =3D 0x2c4, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -330,7 +328,6 @@ static const struct dpu_intf_cfg sm8350_intf[] =3D { }, { .name =3D "intf_2", .id =3D INTF_2, .base =3D 0x36000, .len =3D 0x2c4, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, @@ -340,7 +337,6 @@ static const struct dpu_intf_cfg sm8350_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x37000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 2ee29c56224596b3786104090290b88cecf7b223..d1dd895acbf666ceab39f9c38ae= 11bda100b5953 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -178,7 +178,6 @@ static const struct dpu_intf_cfg sc7280_intf[] =3D { { .name =3D "intf_0", .id =3D INTF_0, .base =3D 0x34000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -187,7 +186,6 @@ static const struct dpu_intf_cfg sc7280_intf[] =3D { }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x35000, .len =3D 0x2c4, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -197,7 +195,6 @@ static const struct dpu_intf_cfg sc7280_intf[] =3D { }, { .name =3D "intf_5", .id =3D INTF_5, .base =3D 0x39000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index dac38e0ade971876c2ed73b6d46cd4055cb77d2d..5b765620d6eff14327f8eff811e= e3b7b8fd404a5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -307,7 +307,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { { .name =3D "intf_0", .id =3D INTF_0, .base =3D 0x34000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -316,7 +315,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x35000, .len =3D 0x300, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -326,7 +324,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { }, { .name =3D "intf_2", .id =3D INTF_2, .base =3D 0x36000, .len =3D 0x300, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, @@ -336,7 +333,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x37000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_NONE, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -345,7 +341,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { }, { .name =3D "intf_4", .id =3D INTF_4, .base =3D 0x38000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, @@ -354,7 +349,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { }, { .name =3D "intf_5", .id =3D INTF_5, .base =3D 0x39000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_3, .prog_fetch_lines_worst_case =3D 24, @@ -363,7 +357,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { }, { .name =3D "intf_6", .id =3D INTF_6, .base =3D 0x3a000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_2, .prog_fetch_lines_worst_case =3D 24, @@ -372,7 +365,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { }, { .name =3D "intf_7", .id =3D INTF_7, .base =3D 0x3b000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_NONE, .controller_id =3D MSM_DP_CONTROLLER_2, .prog_fetch_lines_worst_case =3D 24, @@ -381,7 +373,6 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { }, { .name =3D "intf_8", .id =3D INTF_8, .base =3D 0x3c000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_NONE, .controller_id =3D MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index db332286a0a92cfda434571a2a582c45460e5300..770c2236afebe8b6bb38f2eab4d= 201fbf4256342 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -327,7 +327,6 @@ static const struct dpu_intf_cfg sm8450_intf[] =3D { { .name =3D "intf_0", .id =3D INTF_0, .base =3D 0x34000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -336,7 +335,6 @@ static const struct dpu_intf_cfg sm8450_intf[] =3D { }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x35000, .len =3D 0x300, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -346,7 +344,6 @@ static const struct dpu_intf_cfg sm8450_intf[] =3D { }, { .name =3D "intf_2", .id =3D INTF_2, .base =3D 0x36000, .len =3D 0x300, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, @@ -356,7 +353,6 @@ static const struct dpu_intf_cfg sm8450_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x37000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index 826cd366495139e0e4cf1862e923ef0ece0d7184..6f376b716690a8e144d2ad9c424= 232c7a535c45e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -337,7 +337,6 @@ static const struct dpu_intf_cfg sa8775p_intf[] =3D { { .name =3D "intf_0", .id =3D INTF_0, .base =3D 0x34000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -346,7 +345,6 @@ static const struct dpu_intf_cfg sa8775p_intf[] =3D { }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x35000, .len =3D 0x300, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -356,7 +354,6 @@ static const struct dpu_intf_cfg sa8775p_intf[] =3D { }, { .name =3D "intf_2", .id =3D INTF_2, .base =3D 0x36000, .len =3D 0x300, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, @@ -366,7 +363,6 @@ static const struct dpu_intf_cfg sa8775p_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x37000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_NONE, .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case =3D 24, @@ -375,7 +371,6 @@ static const struct dpu_intf_cfg sa8775p_intf[] =3D { }, { .name =3D "intf_4", .id =3D INTF_4, .base =3D 0x38000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, @@ -384,7 +379,6 @@ static const struct dpu_intf_cfg sa8775p_intf[] =3D { }, { .name =3D "intf_6", .id =3D INTF_6, .base =3D 0x3A000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_NONE, .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case =3D 24, @@ -393,7 +387,6 @@ static const struct dpu_intf_cfg sa8775p_intf[] =3D { }, { .name =3D "intf_7", .id =3D INTF_7, .base =3D 0x3b000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_NONE, .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case =3D 24, @@ -402,7 +395,6 @@ static const struct dpu_intf_cfg sa8775p_intf[] =3D { }, { .name =3D "intf_8", .id =3D INTF_8, .base =3D 0x3c000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_NONE, .controller_id =3D MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */ .prog_fetch_lines_worst_case =3D 24, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index f5f018381b4f0f59c2751b18528994ff79555d58..b03077865cd545219e814311bec= 4d8da4fd9974c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -322,7 +322,6 @@ static const struct dpu_intf_cfg sm8550_intf[] =3D { { .name =3D "intf_0", .id =3D INTF_0, .base =3D 0x34000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -331,7 +330,6 @@ static const struct dpu_intf_cfg sm8550_intf[] =3D { }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x35000, .len =3D 0x300, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -341,7 +339,6 @@ static const struct dpu_intf_cfg sm8550_intf[] =3D { }, { .name =3D "intf_2", .id =3D INTF_2, .base =3D 0x36000, .len =3D 0x300, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, @@ -351,7 +348,6 @@ static const struct dpu_intf_cfg sm8550_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x37000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index ecda48282f52e0fc33b68117650b9f2b76c90276..a587c6bba11c30d9090aa6c48d1= 1c7b65819a58e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -323,7 +323,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { { .name =3D "intf_0", .id =3D INTF_0, .base =3D 0x34000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -332,7 +331,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x35000, .len =3D 0x300, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, @@ -342,7 +340,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { }, { .name =3D "intf_2", .id =3D INTF_2, .base =3D 0x36000, .len =3D 0x300, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DSI, .controller_id =3D MSM_DSI_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, @@ -352,7 +349,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x37000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_NONE, .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case =3D 24, @@ -361,7 +357,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { }, { .name =3D "intf_4", .id =3D INTF_4, .base =3D 0x38000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, @@ -370,7 +365,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { }, { .name =3D "intf_5", .id =3D INTF_5, .base =3D 0x39000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_3, .prog_fetch_lines_worst_case =3D 24, @@ -379,7 +373,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { }, { .name =3D "intf_6", .id =3D INTF_6, .base =3D 0x3A000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_2, .prog_fetch_lines_worst_case =3D 24, @@ -388,7 +381,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { }, { .name =3D "intf_7", .id =3D INTF_7, .base =3D 0x3b000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_NONE, .controller_id =3D MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */ .prog_fetch_lines_worst_case =3D 24, @@ -397,7 +389,6 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { }, { .name =3D "intf_8", .id =3D INTF_8, .base =3D 0x3c000, .len =3D 0x280, - .features =3D INTF_SC7180_MASK, .type =3D INTF_NONE, .controller_id =3D MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */ .prog_fetch_lines_worst_case =3D 24, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 8808be27593b303a2a199a740827c92ea5339b0d..5e0123557a44fda1d250130e09e= 4968535927088 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -110,9 +110,6 @@ #define PINGPONG_SM8150_MASK \ (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) =20 -#define INTF_SC7180_MASK \ - (BIT(DPU_INTF_INPUT_CTRL)) - #define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \ BIT(DPU_WB_UBWC) | \ BIT(DPU_WB_YUV_CONFIG) | \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 858fd73e0ac3a92fe402001d4796eb86945f61b0..33506e3bba9fc51f9e99446cb7d= f6aa51d81a3b1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -141,17 +141,6 @@ enum { DPU_CTL_MAX }; =20 -/** - * INTF sub-blocks - * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from = which - * pixel data arrives to this INTF - * @DPU_INTF_MAX - */ -enum { - DPU_INTF_INPUT_CTRL =3D 0x1, - DPU_INTF_MAX -}; - /** * WB sub-blocks and features * @DPU_WB_LINE_MODE Writeback module supports line/linear mode diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_intf.c index 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Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 6 ++---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 10 ++-------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 2 +- 7 files changed, 5 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h index 78ade3e977108fe98dc63ed93535ae3d947d871b..c0b4db94777c42efd941fdd5299= 3b854ab54c694 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h @@ -100,14 +100,12 @@ static const struct dpu_pingpong_cfg msm8937_pp[] =3D= { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D PINGPONG_MSM8996_MASK, .sblk =3D &msm8996_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x70800, .len =3D 0xd4, - .features =3D PINGPONG_MSM8996_MASK, .sblk =3D &msm8996_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h index 63dd5afdb60b051f6d531257b2844920cc09ed80..d3e4c48be306a04b457cc002910= eb018a3f13154 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h @@ -93,7 +93,6 @@ static const struct dpu_pingpong_cfg msm8917_pp[] =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D PINGPONG_MSM8996_MASK, .sblk =3D &msm8996_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h index 4f09d483fbde29c74e3fd9bd0ba7a1a9c2638183..c488b88332d0e69cfb23bcf4e41= a2e4f4be6844d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h @@ -100,14 +100,12 @@ static const struct dpu_pingpong_cfg msm8953_pp[] =3D= { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D PINGPONG_MSM8996_MASK, .sblk =3D &msm8996_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x70800, .len =3D 0xd4, - .features =3D PINGPONG_MSM8996_MASK, .sblk =3D &msm8996_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h index 54477e300c273182172a78b81dd0274242689895..ac0d872ac06be7376b7b4111e1a= c5f4057b5fb76 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h @@ -181,28 +181,26 @@ static const struct dpu_pingpong_cfg msm8996_pp[] =3D= { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D PINGPONG_MSM8996_TE2_MASK, + .features =3D BIT(DPU_PINGPONG_TE2), .sblk =3D &msm8996_pp_sblk_te, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x70800, .len =3D 0xd4, - .features =3D PINGPONG_MSM8996_TE2_MASK, + .features =3D BIT(DPU_PINGPONG_TE2), .sblk =3D &msm8996_pp_sblk_te, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), }, { .name =3D "pingpong_2", .id =3D PINGPONG_2, .base =3D 0x71000, .len =3D 0xd4, - .features =3D PINGPONG_MSM8996_MASK, .sblk =3D &msm8996_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14), }, { .name =3D "pingpong_3", .id =3D PINGPONG_3, .base =3D 0x71800, .len =3D 0xd4, - .features =3D PINGPONG_MSM8996_MASK, .sblk =3D &msm8996_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15), diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 5e0123557a44fda1d250130e09e4968535927088..5dd486dd9bc77184d5e9cf5ca29= 22bb3d1671ea2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -95,20 +95,14 @@ #define MIXER_QCM2290_MASK \ (BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) =20 -#define PINGPONG_MSM8996_MASK \ - (BIT(DPU_PINGPONG_DSC)) - -#define PINGPONG_MSM8996_TE2_MASK \ - (PINGPONG_MSM8996_MASK | BIT(DPU_PINGPONG_TE2)) - #define PINGPONG_SDM845_MASK \ - (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) + (BIT(DPU_PINGPONG_DITHER)) =20 #define PINGPONG_SDM845_TE2_MASK \ (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) =20 #define PINGPONG_SM8150_MASK \ - (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) + (BIT(DPU_PINGPONG_DITHER)) =20 #define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \ BIT(DPU_WB_UBWC) | \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 33506e3bba9fc51f9e99446cb7df6aa51d81a3b1..3300897aebc9d6b38bcf4a0e0d5= 1095bcbb6fa9d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -119,7 +119,6 @@ enum { * @DPU_PINGPONG_SPLIT PP block supports split fifo * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo * @DPU_PINGPONG_DITHER Dither blocks - * @DPU_PINGPONG_DSC PP block supports DSC * @DPU_PINGPONG_MAX */ enum { @@ -127,7 +126,6 @@ enum { DPU_PINGPONG_SPLIT, DPU_PINGPONG_SLAVE, DPU_PINGPONG_DITHER, - DPU_PINGPONG_DSC, DPU_PINGPONG_MAX }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/= drm/msm/disp/dpu1/dpu_hw_pingpong.c index 36c0ec775b92036eaab26e1fa5331579651ac27c..49e03ecee9e8b567a3f809b977d= eb83731006ac0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c @@ -319,7 +319,7 @@ struct dpu_hw_pingpong *dpu_hw_pingpong_init(struct drm= _device *dev, c->ops.disable_autorefresh =3D dpu_hw_pp_disable_autorefresh; } =20 - if (test_bit(DPU_PINGPONG_DSC, &cfg->features)) { + if (mdss_rev->core_major_ver < 7) { c->ops.setup_dsc =3D dpu_hw_pp_setup_dsc; c->ops.enable_dsc =3D dpu_hw_pp_dsc_enable; c->ops.disable_dsc =3D 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54e7cb3987csm3852e87.59.2025.04.23.14.10.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Apr 2025 14:10:48 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 24 Apr 2025 00:10:13 +0300 Subject: [PATCH v2 17/33] drm/msm/dpu: get rid of DPU_PINGPONG_DITHER Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-dpu-drop-features-v2-17-0a9a66a7b3a2@oss.qualcomm.com> References: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> In-Reply-To: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=38840; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=3UfFt+IDDT9TeYfOXsppTGjO8YQkzT6Rn+lo0FBmcSI=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQwZnuM4zz7sv9zHXrjxVbbeDv7+l6IfhYlnLaeJnNtaXX toaWprRyWjMwsDIxSArpsjiU9AyNWZTctiHHVPrYQaxMoFMYeDiFICJLLVn/2dauMlC/HlKmlOb 0tQGWYsXxwU/1HHWVpv9FeC8t/vQDP19k3PNC7ilDlW1GExedv7wKafDGjPjo0zsBZ4dbj2i8vT qer7mHcJ9jMs/K2Ral77s2zrjvJLFS2tFP6lH4akpj0POMtTMDk2O8n2+XuJ24J87NixJk0w5ij XWpizbWbRbT4pRO4CDcY+X044XoZ8+/e/c9dp4RmbrZb5q8zuZmUnRggysmmGXD9idEQ35t5pTW f79xwUcTq6xC/gF7zlY7zNozcqYvfh4btKnEiY9BfPDGQ/Yg+rvMDzOW7KudnHot7CXMxgjZz2V kjBga5hXWyA17+ysil2HJQokcpgvtnP5PUh3mMO3/q4AAA== X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: a3XJlUIuKEm5eq2sMpYD0hvXgr6bY5kw X-Authority-Analysis: v=2.4 cv=OY6YDgTY c=1 sm=1 tr=0 ts=6809575c cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=7QmdccvAk3pR4y1ATDMA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: a3XJlUIuKEm5eq2sMpYD0hvXgr6bY5kw X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDIzMDE0NCBTYWx0ZWRfX2f6AXSW6S6au c94dAfqaiacnCiK21JnYPQbmjrirKia/mrqv2cBeIjbbc+uyjQvDJHjDmj9WkX++B+d4GihMuJy 32nf3nG6Brji/GaLIwlFVAh9ARzf95A6VK5xXgqqXLLhWiH7MKuv6C52GfiTeoacLU8eZLrWoFQ gakjqAmc6QL4znm/8Mf6rOHmMr6GVSURw0tG5vN1lEHVkHFijjyghhw4ZMZvCmS5cou7TNeyGi+ YpiqNSXQcnq7q4GpTGaydV20krgv95ZoHgvxZTbG0mvI+tuphBTT+pCLEna3qUOQxrNfho/y/tv nZT4IYdTJ+Km5drFMsOtIlS7fbWPm19R4UZBC1lb8TZ43XBUTd0EjHvXxv4m76OFDj1eDtTw5np q810BXCHinkAPiK/My6+9TJf8Wu88zHsQJIlyelzwX0QOSe6leWJZOu+Tt2oTjyHe753IHjf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.680,FMLib:17.12.80.40 definitions=2025-04-23_11,2025-04-22_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 mlxscore=0 clxscore=1015 malwarescore=0 mlxlogscore=999 phishscore=0 priorityscore=1501 spamscore=0 adultscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504230144 From: Dmitry Baryshkov Continue migration to the MDSS-revision based checks and replace DPU_PINGPONG_DITHER feature bit with the core_major_ver >=3D 3 check. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 10 ---------- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 6 ++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 6 ++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 3 +-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 6 ++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 6 ------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 6 ------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 3 --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 6 ------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 6 ------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 6 ------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 8 -------- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 8 -------- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 8 -------- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 8 -------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 9 --------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 2 +- 26 files changed, 8 insertions(+), 118 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index 70c519b923f57f2ccae094eedf03c4f313062de8..bc013fb6705d0e5b8e1f5304ebe= 9318227450cae 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -206,67 +206,57 @@ static const struct dpu_pingpong_cfg sm8650_pp[] =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x69000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x6a000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), }, { .name =3D "pingpong_2", .id =3D PINGPONG_2, .base =3D 0x6b000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_1, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), }, { .name =3D "pingpong_3", .id =3D PINGPONG_3, .base =3D 0x6c000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_1, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), }, { .name =3D "pingpong_4", .id =3D PINGPONG_4, .base =3D 0x6d000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_2, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), }, { .name =3D "pingpong_5", .id =3D PINGPONG_5, .base =3D 0x6e000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_2, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), }, { .name =3D "pingpong_cwb_0", .id =3D PINGPONG_CWB_0, .base =3D 0x66000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_3, }, { .name =3D "pingpong_cwb_1", .id =3D PINGPONG_CWB_1, .base =3D 0x66400, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_3, }, { .name =3D "pingpong_cwb_2", .id =3D PINGPONG_CWB_2, .base =3D 0x7e000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_4, }, { .name =3D "pingpong_cwb_3", .id =3D PINGPONG_CWB_3, .base =3D 0x7e400, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_4, }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index 9dc84c8dfb64c5f6642fe47ff9aa9ab16922687f..b171e26165f11185645ac5e6d22= c499a949d8271 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -170,28 +170,26 @@ static const struct dpu_pingpong_cfg msm8998_pp[] =3D= { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D PINGPONG_SDM845_TE2_MASK, + .features =3D BIT(DPU_PINGPONG_TE2), .sblk =3D &sdm845_pp_sblk_te, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x70800, .len =3D 0xd4, - .features =3D PINGPONG_SDM845_TE2_MASK, + .features =3D BIT(DPU_PINGPONG_TE2), .sblk =3D &sdm845_pp_sblk_te, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), }, { .name =3D "pingpong_2", .id =3D PINGPONG_2, .base =3D 0x71000, .len =3D 0xd4, - .features =3D PINGPONG_SDM845_MASK, .sblk =3D &sdm845_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14), }, { .name =3D "pingpong_3", .id =3D PINGPONG_3, .base =3D 0x71800, .len =3D 0xd4, - .features =3D PINGPONG_SDM845_MASK, .sblk =3D &sdm845_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h index 5ec81e3eb6c0902113b4ef1bf850b946d0ce4b1b..6308dece88db70932d55d1e2d4e= 8af713996d9e0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h @@ -141,28 +141,26 @@ static const struct dpu_pingpong_cfg sdm660_pp[] =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D PINGPONG_SDM845_TE2_MASK, + .features =3D BIT(DPU_PINGPONG_TE2), .sblk =3D &sdm845_pp_sblk_te, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x70800, .len =3D 0xd4, - .features =3D PINGPONG_SDM845_TE2_MASK, + .features =3D BIT(DPU_PINGPONG_TE2), .sblk =3D &sdm845_pp_sblk_te, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), }, { .name =3D "pingpong_2", .id =3D PINGPONG_2, .base =3D 0x71000, .len =3D 0xd4, - .features =3D PINGPONG_SDM845_MASK, .sblk =3D &sdm845_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14), }, { .name =3D "pingpong_3", .id =3D PINGPONG_3, .base =3D 0x71800, .len =3D 0xd4, - .features =3D PINGPONG_SDM845_MASK, .sblk =3D &sdm845_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h index 2a80a881a233f48aa7f0b8a9345386eb85e3157d..25954ae17cec5b141637e7c2eba= 29a1bc826b1fe 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h @@ -115,14 +115,13 @@ static const struct dpu_pingpong_cfg sdm630_pp[] =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D PINGPONG_SDM845_TE2_MASK, + .features =3D BIT(DPU_PINGPONG_TE2), .sblk =3D &sdm845_pp_sblk_te, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), }, { .name =3D "pingpong_2", .id =3D PINGPONG_2, .base =3D 0x71000, .len =3D 0xd4, - .features =3D PINGPONG_SDM845_MASK, .sblk =3D &sdm845_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 968076c5f2211552bec1bd750409e4be57dddeff..283e709065be31131f6bc515802= 96e836b8487ae 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -190,28 +190,26 @@ static const struct dpu_pingpong_cfg sdm845_pp[] =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D PINGPONG_SDM845_TE2_MASK, + .features =3D BIT(DPU_PINGPONG_TE2), .sblk =3D &sdm845_pp_sblk_te, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x70800, .len =3D 0xd4, - .features =3D PINGPONG_SDM845_TE2_MASK, + .features =3D BIT(DPU_PINGPONG_TE2), .sblk =3D &sdm845_pp_sblk_te, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), }, { .name =3D "pingpong_2", .id =3D PINGPONG_2, .base =3D 0x71000, .len =3D 0xd4, - .features =3D PINGPONG_SDM845_MASK, .sblk =3D &sdm845_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14), }, { .name =3D "pingpong_3", .id =3D PINGPONG_3, .base =3D 0x71800, .len =3D 0xd4, - .features =3D PINGPONG_SDM845_MASK, .sblk =3D &sdm845_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index 6438a5a14e4b89462873b5c817713b4ff67d7ccc..c93213682a5781bbd8ad137152c= 9be8bb1e6efbe 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -210,42 +210,36 @@ static const struct dpu_pingpong_cfg sm8150_pp[] =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D MERGE_3D_0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x70800, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D MERGE_3D_0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), }, { .name =3D "pingpong_2", .id =3D PINGPONG_2, .base =3D 0x71000, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D MERGE_3D_1, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), }, { .name =3D "pingpong_3", .id =3D PINGPONG_3, .base =3D 0x71800, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D MERGE_3D_1, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), }, { .name =3D "pingpong_4", .id =3D PINGPONG_4, .base =3D 0x72000, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D MERGE_3D_2, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), }, { .name =3D "pingpong_5", .id =3D PINGPONG_5, .base =3D 0x72800, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D MERGE_3D_2, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index d08799471b85a882ecb151cb9b5be2a098bfc003..5da17c288f66f4b7b5fef1550fc= c9793f524115e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -209,42 +209,36 @@ static const struct dpu_pingpong_cfg sc8180x_pp[] =3D= { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D MERGE_3D_0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x70800, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D MERGE_3D_0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), }, { .name =3D "pingpong_2", .id =3D PINGPONG_2, .base =3D 0x71000, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D MERGE_3D_1, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), }, { .name =3D "pingpong_3", .id =3D PINGPONG_3, .base =3D 0x71800, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D MERGE_3D_1, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), }, { .name =3D "pingpong_4", .id =3D PINGPONG_4, .base =3D 0x72000, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D MERGE_3D_2, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), }, { .name =3D "pingpong_5", .id =3D PINGPONG_5, .base =3D 0x72800, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D MERGE_3D_2, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h index acaa0b85ed1edd970dd17ae4d8d06a3dee6e8083..e388900623f0de4a1af10d22a6b= 9bdf4842e1f40 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h @@ -158,28 +158,24 @@ static const struct dpu_pingpong_cfg sm7150_pp[] =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D MERGE_3D_0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x70800, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D MERGE_3D_0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), }, { .name =3D "pingpong_2", .id =3D PINGPONG_2, .base =3D 0x71000, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D MERGE_3D_1, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), }, { .name =3D "pingpong_3", .id =3D PINGPONG_3, .base =3D 0x71800, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D MERGE_3D_1, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h index a99c99ca37703cc3a7d4403d3f026f234b693319..e2306d314ef8f8b59078a8ca8c5= 29f2e56385c98 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h @@ -138,19 +138,16 @@ static const struct dpu_pingpong_cfg sm6150_pp[] =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x70800, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), }, { .name =3D "pingpong_2", .id =3D PINGPONG_2, .base =3D 0x71000, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h index 0dce5292fdfe7988504d51d701d3908adf9b596a..c75d0d42b6d856f98580068a5ac= 7f82f90380ac9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h @@ -119,14 +119,12 @@ static const struct dpu_pingpong_cfg sm6125_pp[] =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .merge_3d =3D 0, .sblk =3D &sdm845_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x70800, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .merge_3d =3D 0, .sblk =3D &sdm845_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 6fce6d382c959b7ae47591f52dd06bcf241ff4e2..4da7445aa8019894b35b12ace18= c0bd6209b9148 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -208,42 +208,36 @@ static const struct dpu_pingpong_cfg sm8250_pp[] =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D MERGE_3D_0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x70800, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D MERGE_3D_0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), }, { .name =3D "pingpong_2", .id =3D PINGPONG_2, .base =3D 0x71000, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D MERGE_3D_1, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), }, { .name =3D "pingpong_3", .id =3D PINGPONG_3, .base =3D 0x71800, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D MERGE_3D_1, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), }, { .name =3D "pingpong_4", .id =3D PINGPONG_4, .base =3D 0x72000, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D MERGE_3D_2, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), }, { .name =3D "pingpong_5", .id =3D PINGPONG_5, .base =3D 0x72800, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D MERGE_3D_2, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index 52b674fed71e57f82b778c13f6712a52a2a425a7..77126039733bbb2941aa6698bb3= 53334efab3804 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -111,14 +111,12 @@ static const struct dpu_pingpong_cfg sc7180_pp[] =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D 0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x70800, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D 0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index 0178ce52e84f355919241435f58c390234c16162..842505ab5c4a6555e0a32238040= 65e68a5a4e680 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -76,7 +76,6 @@ static const struct dpu_pingpong_cfg sm6115_pp[] =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D 0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index 89db83a73bbeb15b99ac4324b7685baf0d724039..6563296190bb27b6cab1b03921a= f6cff34037cd2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -119,14 +119,12 @@ static struct dpu_pingpong_cfg sm6350_pp[] =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D 0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x70800, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D 0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index 0b1740de2bff94f1818ab41c6bc713f16796c4a4..7087c3c2e728c51f070b67ab0f8= 039f74eb7da6c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -76,7 +76,6 @@ static const struct dpu_pingpong_cfg qcm2290_pp[] =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D 0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index 19800f207bff3077c7ac57ad736eea533674ae20..a2fdbe39e4415c1da1da0517db2= 284f368bfa07b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -78,7 +78,6 @@ static const struct dpu_pingpong_cfg sm6375_pp[] =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D PINGPONG_SM8150_MASK, .sblk =3D &sdm845_pp_sblk, .merge_3d =3D 0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 94a9f33f008a13db09764882cb042f71337b89d5..62de32268ee5528ff0fb16a3ff7= c2baa5ea42466 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -208,42 +208,36 @@ static const struct dpu_pingpong_cfg sm8350_pp[] =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x69000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x6a000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), }, { .name =3D "pingpong_2", .id =3D PINGPONG_2, .base =3D 0x6b000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_1, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), }, { .name =3D "pingpong_3", .id =3D PINGPONG_3, .base =3D 0x6c000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_1, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), }, { .name =3D "pingpong_4", .id =3D PINGPONG_4, .base =3D 0x6d000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_2, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), }, { .name =3D "pingpong_5", .id =3D PINGPONG_5, .base =3D 0x6e000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_2, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index d1dd895acbf666ceab39f9c38ae11bda100b5953..202de6f9b0c65c6f2caa9e9d523= 2f5b92d8bdf01 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -121,28 +121,24 @@ static const struct dpu_pingpong_cfg sc7280_pp[] =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x69000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D 0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x6a000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D 0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), }, { .name =3D "pingpong_2", .id =3D PINGPONG_2, .base =3D 0x6b000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D 0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), }, { .name =3D "pingpong_3", .id =3D PINGPONG_3, .base =3D 0x6c000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D 0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 5b765620d6eff14327f8eff811ee3b7b8fd404a5..e16fa6d8a431f55643c9ed9c8b3= 845a790a7e268 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -208,42 +208,36 @@ static const struct dpu_pingpong_cfg sc8280xp_pp[] = =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x69000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x6a000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), }, { .name =3D "pingpong_2", .id =3D PINGPONG_2, .base =3D 0x6b000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_1, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), }, { .name =3D "pingpong_3", .id =3D PINGPONG_3, .base =3D 0x6c000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_1, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), }, { .name =3D "pingpong_4", .id =3D PINGPONG_4, .base =3D 0x6d000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_2, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), }, { .name =3D "pingpong_5", .id =3D PINGPONG_5, .base =3D 0x6e000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_2, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 770c2236afebe8b6bb38f2eab4d201fbf4256342..3059b9f88567c6f667ac456fa49= de73f3f212ad5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -209,55 +209,47 @@ static const struct dpu_pingpong_cfg sm8450_pp[] =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x69000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x6a000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), }, { .name =3D "pingpong_2", .id =3D PINGPONG_2, .base =3D 0x6b000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_1, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), }, { .name =3D "pingpong_3", .id =3D PINGPONG_3, .base =3D 0x6c000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_1, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), }, { .name =3D "pingpong_4", .id =3D PINGPONG_4, .base =3D 0x6d000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_2, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), }, { .name =3D "pingpong_5", .id =3D PINGPONG_5, .base =3D 0x6e000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_2, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), }, { .name =3D "pingpong_cwb_0", .id =3D PINGPONG_CWB_0, .base =3D 0x65800, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_3, }, { .name =3D "pingpong_cwb_1", .id =3D PINGPONG_CWB_1, .base =3D 0x65c00, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_3, }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index 6f376b716690a8e144d2ad9c424232c7a535c45e..786071b35b7b66e202899849b0e= 06762c8d1c57d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -208,55 +208,47 @@ static const struct dpu_pingpong_cfg sa8775p_pp[] =3D= { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x69000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x6a000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), }, { .name =3D "pingpong_2", .id =3D PINGPONG_2, .base =3D 0x6b000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_1, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), }, { .name =3D "pingpong_3", .id =3D PINGPONG_3, .base =3D 0x6c000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_1, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), }, { .name =3D "pingpong_4", .id =3D PINGPONG_4, .base =3D 0x6d000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_2, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), }, { .name =3D "pingpong_5", .id =3D PINGPONG_5, .base =3D 0x6e000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_2, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), }, { .name =3D "pingpong_6", .id =3D PINGPONG_CWB_0, .base =3D 0x65800, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_3, }, { .name =3D "pingpong_7", .id =3D PINGPONG_CWB_1, .base =3D 0x65c00, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_3, }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index b03077865cd545219e814311bec4d8da4fd9974c..fb31699cf5bf11036315984ab95= 240a312703afc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -205,55 +205,47 @@ static const struct dpu_pingpong_cfg sm8550_pp[] =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x69000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x6a000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), }, { .name =3D "pingpong_2", .id =3D PINGPONG_2, .base =3D 0x6b000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_1, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), }, { .name =3D "pingpong_3", .id =3D PINGPONG_3, .base =3D 0x6c000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_1, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), }, { .name =3D "pingpong_4", .id =3D PINGPONG_4, .base =3D 0x6d000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_2, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), }, { .name =3D "pingpong_5", .id =3D PINGPONG_5, .base =3D 0x6e000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_2, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), }, { .name =3D "pingpong_cwb_0", .id =3D PINGPONG_CWB_0, .base =3D 0x66000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_3, }, { .name =3D "pingpong_cwb_1", .id =3D PINGPONG_CWB_1, .base =3D 0x66400, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_3, }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index a587c6bba11c30d9090aa6c48d11c7b65819a58e..67fc0098836f72b6b67da68a6c4= 1c18f334afd94 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -205,55 +205,47 @@ static const struct dpu_pingpong_cfg x1e80100_pp[] = =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x69000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x6a000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_0, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), }, { .name =3D "pingpong_2", .id =3D PINGPONG_2, .base =3D 0x6b000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_1, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), }, { .name =3D "pingpong_3", .id =3D PINGPONG_3, .base =3D 0x6c000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_1, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), }, { .name =3D "pingpong_4", .id =3D PINGPONG_4, .base =3D 0x6d000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_2, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), }, { .name =3D "pingpong_5", .id =3D PINGPONG_5, .base =3D 0x6e000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_2, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), }, { .name =3D "pingpong_cwb_0", .id =3D PINGPONG_CWB_0, .base =3D 0x66000, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_3, }, { .name =3D "pingpong_cwb_1", .id =3D PINGPONG_CWB_1, .base =3D 0x66400, .len =3D 0, - .features =3D BIT(DPU_PINGPONG_DITHER), .sblk =3D &sc7280_pp_sblk, .merge_3d =3D MERGE_3D_3, }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 5dd486dd9bc77184d5e9cf5ca2922bb3d1671ea2..f205e2c967ddf5f437ac335585d= 43d75a0623e32 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -95,15 +95,6 @@ #define MIXER_QCM2290_MASK \ (BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) =20 -#define PINGPONG_SDM845_MASK \ - (BIT(DPU_PINGPONG_DITHER)) - -#define PINGPONG_SDM845_TE2_MASK \ - (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) - -#define PINGPONG_SM8150_MASK \ - (BIT(DPU_PINGPONG_DITHER)) - #define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \ BIT(DPU_WB_UBWC) | \ BIT(DPU_WB_YUV_CONFIG) | \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 3300897aebc9d6b38bcf4a0e0d51095bcbb6fa9d..530eb74b0548b0a257abc89c3e1= 2ab990addd550 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -118,14 +118,12 @@ enum { * @DPU_PINGPONG_TE2 Additional tear check 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Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 2 +- 10 files changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h index c0b4db94777c42efd941fdd52993b854ab54c694..29e0eba91930f96fb94c97c33b4= 490771c3a7c17 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h @@ -19,7 +19,6 @@ static const struct dpu_mdp_cfg msm8937_mdp[] =3D { { .name =3D "top_0", .base =3D 0x0, .len =3D 0x454, - .features =3D BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_RGB0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 4 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h index d3e4c48be306a04b457cc002910eb018a3f13154..cb1ee4b63f9fe8f0b069ad4a75b= 121d40e988d2b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h @@ -19,7 +19,6 @@ static const struct dpu_mdp_cfg msm8917_mdp[] =3D { { .name =3D "top_0", .base =3D 0x0, .len =3D 0x454, - .features =3D BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_RGB0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 4 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h index c488b88332d0e69cfb23bcf4e41a2e4f4be6844d..b44d02b48418f7bca50b0411954= 0122fb861b971 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h @@ -19,7 +19,6 @@ static const struct dpu_mdp_cfg msm8953_mdp[] =3D { { .name =3D "top_0", .base =3D 0x0, .len =3D 0x454, - .features =3D BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_RGB0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 4 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h index ac0d872ac06be7376b7b4111e1ac5f4057b5fb76..436fa56e2ba2d867b58b59ec6b0= 2d1d0f396c23b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h @@ -22,7 +22,6 @@ static const struct dpu_mdp_cfg msm8996_mdp[] =3D { { .name =3D "top_0", .base =3D 0x0, .len =3D 0x454, - .features =3D BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_VIG1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index b171e26165f11185645ac5e6d22c499a949d8271..38cdea019bf2b1391c242953e4c= 67d9dc4c2274c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -23,7 +23,6 @@ static const struct dpu_caps msm8998_dpu_caps =3D { static const struct dpu_mdp_cfg msm8998_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x458, - .features =3D BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_VIG1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h index 6308dece88db70932d55d1e2d4e8af713996d9e0..176640bff1214e89606286ce572= f74300f6f343f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h @@ -22,7 +22,6 @@ static const struct dpu_caps sdm660_dpu_caps =3D { static const struct dpu_mdp_cfg sdm660_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x458, - .features =3D BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_VIG1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h index 25954ae17cec5b141637e7c2eba29a1bc826b1fe..e6eb95173cfef2a52f5dc606ca4= 1a2f1f5650c2c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h @@ -22,7 +22,6 @@ static const struct dpu_caps sdm630_dpu_caps =3D { static const struct dpu_mdp_cfg sdm630_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x458, - .features =3D BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_DMA0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 8 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 283e709065be31131f6bc51580296e836b8487ae..9f04c7cd5539c012a9490556a57= 36d09aa0a10c1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -23,7 +23,7 @@ static const struct dpu_caps sdm845_dpu_caps =3D { static const struct dpu_mdp_cfg sdm845_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x45c, - .features =3D BIT(DPU_MDP_AUDIO_SELECT) | BIT(DPU_MDP_VSYNC_SEL), + .features =3D BIT(DPU_MDP_AUDIO_SELECT), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_VIG1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 530eb74b0548b0a257abc89c3e12ab990addd550..3a0de200cc5c9751adebe681f80= 679e0d527ab1c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -34,8 +34,6 @@ * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats * @DPU_MDP_PERIPH_0_REMOVED Indicates that access to periph top0 block re= sults * in a failure - * @DPU_MDP_VSYNC_SEL Enables vsync source selection via MDP_VSYNC_SE= L register - * (moved into INTF block since DPU 5.0.0) * @DPU_MDP_MAX Maximum value =20 */ @@ -44,7 +42,6 @@ enum { DPU_MDP_10BIT_SUPPORT, DPU_MDP_AUDIO_SELECT, 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Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +- 9 files changed, 2 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index bc013fb6705d0e5b8e1f5304ebe9318227450cae..d64366f608ea673422bbf4e5b6a= e7f4ad8570784 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -21,7 +21,6 @@ static const struct dpu_caps sm8650_dpu_caps =3D { static const struct dpu_mdp_cfg sm8650_mdp =3D { .name =3D "top_0", .base =3D 0, .len =3D 0x494, - .features =3D BIT(DPU_MDP_PERIPH_0_REMOVED), .clk_ctrls =3D { [DPU_CLK_CTRL_REG_DMA] =3D { .reg_off =3D 0x2bc, .bit_off =3D 20 }, }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index e16fa6d8a431f55643c9ed9c8b3845a790a7e268..43916752cfd5836718a3770df4c= 8767635f77ee9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -21,7 +21,6 @@ static const struct dpu_caps sc8280xp_dpu_caps =3D { static const struct dpu_mdp_cfg sc8280xp_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x494, - .features =3D BIT(DPU_MDP_PERIPH_0_REMOVED), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_VIG1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 3059b9f88567c6f667ac456fa49de73f3f212ad5..d58d5b7ce79b8c069d111c3c2aa= 3e9cdb2c1a435 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -21,7 +21,6 @@ static const struct dpu_caps sm8450_dpu_caps =3D { static const struct dpu_mdp_cfg sm8450_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x494, - .features =3D BIT(DPU_MDP_PERIPH_0_REMOVED), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_VIG1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index 786071b35b7b66e202899849b0e06762c8d1c57d..064546d4fd4538cd5a6b56fca3e= e12d482a7dbb6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -20,7 +20,6 @@ static const struct dpu_caps sa8775p_dpu_caps =3D { static const struct dpu_mdp_cfg sa8775p_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x494, - .features =3D BIT(DPU_MDP_PERIPH_0_REMOVED), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_VIG1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index fb31699cf5bf11036315984ab95240a312703afc..959f3e9dbc5455fe53c1bb240b5= db57212f2d4eb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -21,7 +21,6 @@ static const struct dpu_caps sm8550_dpu_caps =3D { static const struct dpu_mdp_cfg sm8550_mdp =3D { .name =3D "top_0", .base =3D 0, .len =3D 0x494, - .features =3D BIT(DPU_MDP_PERIPH_0_REMOVED), .clk_ctrls =3D { [DPU_CLK_CTRL_REG_DMA] =3D { .reg_off =3D 0x2bc, .bit_off =3D 20 }, }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index 67fc0098836f72b6b67da68a6c41c18f334afd94..174cfdfcfdf9860ea86c983c6b6= 591ba98da5400 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -20,7 +20,6 @@ static const struct dpu_caps x1e80100_dpu_caps =3D { static const struct dpu_mdp_cfg x1e80100_mdp =3D { .name =3D "top_0", .base =3D 0, .len =3D 0x494, - .features =3D BIT(DPU_MDP_PERIPH_0_REMOVED), .clk_ctrls =3D { [DPU_CLK_CTRL_REG_DMA] =3D { .reg_off =3D 0x2bc, .bit_off =3D 20 }, }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 3a0de200cc5c9751adebe681f80679e0d527ab1c..0f8c24ad346568464206eaaeeb1= 99955788ed505 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -32,8 +32,6 @@ * MDP TOP BLOCK features * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be done per pipe * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats - * @DPU_MDP_PERIPH_0_REMOVED Indicates that access to periph top0 block re= sults - * in a failure * @DPU_MDP_MAX Maximum value =20 */ @@ -41,7 +39,6 @@ enum { DPU_MDP_PANIC_PER_PIPE =3D 0x1, DPU_MDP_10BIT_SUPPORT, DPU_MDP_AUDIO_SELECT, - DPU_MDP_PERIPH_0_REMOVED, DPU_MDP_MAX }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_top.c index cebe7ce7b258fc178a687770906f7c4c20aa0d4c..c49a67da86b0d46d12c32466981= be7f00519974c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c @@ -272,7 +272,7 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops, =20 if (mdss_rev->core_major_ver < 5) ops->setup_vsync_source =3D dpu_hw_setup_vsync_sel; - else if (!(cap & BIT(DPU_MDP_PERIPH_0_REMOVED))) + else if (mdss_rev->core_major_ver < 8) ops->setup_vsync_source =3D dpu_hw_setup_wd_timer; =20 ops->get_safe_status =3D dpu_hw_get_safe_status; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 3305ad0623ca41882db0172e65a9beb7ebe00b6c..f3f84c8c302fb1bfe6e6d70e411= 0d0b89259e55c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1022,7 +1022,7 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_stat= e *disp_state, struct msm_k dpu_kms->mmio + cat->wb[i].base, "%s", cat->wb[i].name); =20 - if (cat->mdp[0].features & BIT(DPU_MDP_PERIPH_0_REMOVED)) { + if (dpu_kms->catalog->mdss_ver->core_major_ver >=3D 8) { msm_disp_snapshot_add_block(disp_state, MDP_PERIPH_TOP0, dpu_kms->mmio + cat->mdp[0].base, "top"); msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - MDP_PERIPH_TOP= 0_END, --=20 2.39.5 From nobody Sun Feb 8 20:34:34 2026 Received: from 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Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 3 ++- 7 files changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 9f04c7cd5539c012a9490556a5736d09aa0a10c1..21264184566493ab4e356a4e0c0= 32ee7780cabff 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -23,7 +23,6 @@ static const struct dpu_caps sdm845_dpu_caps =3D { static const struct dpu_mdp_cfg sdm845_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x45c, - .features =3D BIT(DPU_MDP_AUDIO_SELECT), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_VIG1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h index 3a60432a758a942eb1541f143018bd466b2bdf20..ce169a610e195cbb6f0fee1362b= caaf05df777cb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h @@ -11,7 +11,6 @@ static const struct dpu_mdp_cfg sdm670_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x45c, - .features =3D BIT(DPU_MDP_AUDIO_SELECT), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_VIG1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index c93213682a5781bbd8ad137152c9be8bb1e6efbe..634b7dc452839f994c948601fe9= a09581cb42a42 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -23,7 +23,6 @@ static const struct dpu_caps sm8150_dpu_caps =3D { static const struct dpu_mdp_cfg sm8150_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x45c, - .features =3D BIT(DPU_MDP_AUDIO_SELECT), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_VIG1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index 5da17c288f66f4b7b5fef1550fcc9793f524115e..59e280edcd508c14ee297857a19= e9974970566de 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -23,7 +23,6 @@ static const struct dpu_caps sc8180x_dpu_caps =3D { static const struct dpu_mdp_cfg sc8180x_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x45c, - .features =3D BIT(DPU_MDP_AUDIO_SELECT), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_VIG1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h index e388900623f0de4a1af10d22a6b9bdf4842e1f40..af0d789c47917e9b712282a542c= 3d0886313c049 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h @@ -23,7 +23,6 @@ static const struct dpu_caps sm7150_dpu_caps =3D { static const struct dpu_mdp_cfg sm7150_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x45c, - .features =3D BIT(DPU_MDP_AUDIO_SELECT), .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_VIG1] =3D { .reg_off =3D 0x2b4, .bit_off =3D 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 0f8c24ad346568464206eaaeeb199955788ed505..a493dfffa9e4981f4c3f6e05dbb= f14e1416f07e5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -38,7 +38,6 @@ enum { DPU_MDP_PANIC_PER_PIPE =3D 0x1, DPU_MDP_10BIT_SUPPORT, - DPU_MDP_AUDIO_SELECT, DPU_MDP_MAX }; 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54e7cb3987csm3852e87.59.2025.04.23.14.10.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Apr 2025 14:10:59 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 24 Apr 2025 00:10:17 +0300 Subject: [PATCH v2 21/33] drm/msm/dpu: get rid of DPU_MIXER_COMBINED_ALPHA Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-dpu-drop-features-v2-21-0a9a66a7b3a2@oss.qualcomm.com> References: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> In-Reply-To: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4640; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=Qx+tWXrswqotBVXqga7C6jCwYmZehbjfGnHTcmUatQs=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoCVct3qirea0FRfWcXU6SZh+pVaeOGVttmDTHq G9x+ecs24+JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaAlXLQAKCRCLPIo+Aiko 1cfJCACkjMgsmnorrOg22YwIcHL9QW/HybIbdmI4aLPwDtTrI0AIW8376jjps6b4EFdyDceZZcF 7jo5SAbPHhvsiGWUThUklWgA0qZlTfBWOCKBcZJZeqE76gNBANBWK0arMKf8kMHJ9lsPNVQk6eY 7+y/4SCq5CWrfGRnrF6biUyyWsASQhpt6o0aWFmgx8acuJ61clAZw8mSR7SZ6N1rhZgQsOnM6Bg n2DLzUR5Ycwn/FWgOTlubQFZmayqNxGWPy6or7sJYCzrex4bh8sjOOlIKwFM9CSoAlBfJsoKEei j76Vns9xPCPIY0Urx/rf77OF6tj6qaVJY5jOj6AC0YyNjRmw X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-ORIG-GUID: 3vOowtlz7u2lOXDGn1l94oQAkEDQLXi5 X-Authority-Analysis: v=2.4 cv=ftfcZE4f c=1 sm=1 tr=0 ts=68095765 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=TQSGqBnpyQA7SagL8QUA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: 3vOowtlz7u2lOXDGn1l94oQAkEDQLXi5 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDIzMDE0NCBTYWx0ZWRfX3//OqRV18Qon RSXd5gMAvQ0R6XCPoTQfxfBplmjYHzYkEG1PKLWDG8p3cSi1JyAYz5iryIsGKnU2O5yRVPHttwp Jfx83xXYPzCQ5lCyzN7NW6gbPOB3dL8Q3Jeu8FryrHRFF87chOfFkQVIezKv2pTidchQJg3XFxj 7Dbi3OYvbYAX/DgrpOR6obxIJx86i/wI2w6Y1osdKRcqXBCDypAvN3sCziuMN/qEt9Vf8ikCBJC +dXs+xS6Hjdt+pOyBa8j9UQAaDzU2bU1yH5zaK3LCUian0vqYVBu5fZwVZ9BcZpzMMcMA4WiEEp j/h+ZNOn1Qj0mQ3Kt/ch0KsqMDnV1+GK65wHX8xyMOhiRmAHvY1Rkt0f1toEHLV5RtXuQsJ0+oo ViGyjqpCX4dKxEbtdp4UxsCBQTrboshI0KaGJUatXBfdmSShX4v0kT7timvjRk9YXTHe3Nz6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.680,FMLib:17.12.80.40 definitions=2025-04-23_11,2025-04-22_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxscore=0 suspectscore=0 mlxlogscore=999 lowpriorityscore=0 phishscore=0 malwarescore=0 impostorscore=0 adultscore=0 spamscore=0 clxscore=1015 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504230144 From: Dmitry Baryshkov Continue migration to the MDSS-revision based checks and replace DPU_MIXER_COMBINED_ALPHA feature bit with the core_major_ver >=3D 4 check. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 6 ++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 3 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +- 5 files changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index f205e2c967ddf5f437ac335585d43d75a0623e32..e22ad69e451bb5ed38f056e95b0= 944fb5c21ec7b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -90,10 +90,10 @@ (BIT(DPU_MIXER_SOURCESPLIT)) =20 #define MIXER_SDM845_MASK \ - (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED= _ALPHA)) + (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER)) =20 #define MIXER_QCM2290_MASK \ - (BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) + (BIT(DPU_DIM_LAYER)) =20 #define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \ BIT(DPU_WB_UBWC) | \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index a493dfffa9e4981f4c3f6e05dbbf14e1416f07e5..e1fc6fdd8864b017bec35e448ef= 15420530e018b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -85,7 +85,6 @@ enum { * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configurat= ion * @DPU_MIXER_GC Gamma correction block * @DPU_DIM_LAYER Layer mixer supports dim layer - * @DPU_MIXER_COMBINED_ALPHA Layer mixer has combined alpha register * @DPU_MIXER_MAX maximum value */ enum { @@ -93,7 +92,6 @@ enum { DPU_MIXER_SOURCESPLIT, DPU_MIXER_GC, DPU_DIM_LAYER, - DPU_MIXER_COMBINED_ALPHA, DPU_MIXER_MAX }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_hw_lm.c index 4f57cfca89bd3962e7e512952809db0300cb9baf..3bfb61cb83672dca4236bdbbbfb= 1e442223576d2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -150,10 +150,12 @@ static void dpu_hw_lm_setup_color3(struct dpu_hw_mixe= r *ctx, * @dev: Corresponding device for devres management * @cfg: mixer catalog entry for which driver object is required * @addr: mapped register io address of MDP + * @mdss_ver: DPU core's major and minor versions */ struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev, const struct dpu_lm_cfg *cfg, - void __iomem *addr) + void __iomem *addr, + const struct dpu_mdss_version *mdss_ver) { struct dpu_hw_mixer *c; =20 @@ -173,7 +175,7 @@ struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *= dev, c->idx =3D cfg->id; c->cap =3D cfg; c->ops.setup_mixer_out =3D dpu_hw_lm_setup_out; - if (test_bit(DPU_MIXER_COMBINED_ALPHA, &c->cap->features)) + if (mdss_ver->core_major_ver >=3D 4) c->ops.setup_blend_config =3D dpu_hw_lm_setup_blend_config_combined_alph= a; else c->ops.setup_blend_config =3D dpu_hw_lm_setup_blend_config; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_hw_lm.h index 6f60fa9b3cd78160699a97dc7a86a5ec0b599281..fff1156add683fec8ce6785e7fe= 1d769d0de3fe0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h @@ -95,6 +95,7 @@ static inline struct dpu_hw_mixer *to_dpu_hw_mixer(struct= dpu_hw_blk *hw) =20 struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *dev, const struct dpu_lm_cfg *cfg, - void __iomem *addr); + void __iomem *addr, + const struct dpu_mdss_version *mdss_ver); =20 #endif /*_DPU_HW_LM_H */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.c index 1ed458aed2bc2c54f6e02acce43d88927100b99c..5d55b246b32f0757281d8743ae2= d1a23cc6e333d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -58,7 +58,7 @@ int dpu_rm_init(struct drm_device *dev, struct dpu_hw_mixer *hw; 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It is currently unused, but can be replaed with the core_major_ver >=3D 4 check. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 3 --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 +---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- 7 files changed, 1 insertion(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h index e2306d314ef8f8b59078a8ca8c529f2e56385c98..8fb926bff36d32fb4ce1036cb69= 513599dc7b6b7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h @@ -107,20 +107,17 @@ static const struct dpu_lm_cfg sm6150_lm[] =3D { { .name =3D "lm_0", .id =3D LM_0, .base =3D 0x44000, .len =3D 0x320, - .features =3D MIXER_QCM2290_MASK, .sblk =3D &sdm845_lm_sblk, .pingpong =3D PINGPONG_0, .dspp =3D DSPP_0, }, { .name =3D "lm_1", .id =3D LM_1, .base =3D 0x45000, .len =3D 0x320, - .features =3D MIXER_QCM2290_MASK, .sblk =3D &sdm845_lm_sblk, .pingpong =3D PINGPONG_1, }, { .name =3D "lm_2", .id =3D LM_2, .base =3D 0x46000, .len =3D 0x320, - .features =3D MIXER_QCM2290_MASK, .sblk =3D &sdm845_lm_sblk, .pingpong =3D PINGPONG_2, }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h index c75d0d42b6d856f98580068a5ac7f82f90380ac9..af7433fc6c128c2e29381ba6bf5= 6388bccdd93f8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h @@ -91,7 +91,6 @@ static const struct dpu_lm_cfg sm6125_lm[] =3D { { .name =3D "lm_0", .id =3D LM_0, .base =3D 0x44000, .len =3D 0x320, - .features =3D MIXER_QCM2290_MASK, .sblk =3D &sdm845_lm_sblk, .pingpong =3D PINGPONG_0, .dspp =3D DSPP_0, @@ -99,7 +98,6 @@ static const struct dpu_lm_cfg sm6125_lm[] =3D { }, { .name =3D "lm_1", .id =3D LM_1, .base =3D 0x45000, .len =3D 0x320, - .features =3D MIXER_QCM2290_MASK, .sblk =3D &sdm845_lm_sblk, .pingpong =3D PINGPONG_1, .dspp =3D 0, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index 842505ab5c4a6555e0a3223804065e68a5a4e680..155db203282f687e5632dcb0423= 93951bb03876f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -57,7 +57,6 @@ static const struct dpu_lm_cfg sm6115_lm[] =3D { { .name =3D "lm_0", .id =3D LM_0, .base =3D 0x44000, .len =3D 0x320, - .features =3D MIXER_QCM2290_MASK, .sblk =3D &qcm2290_lm_sblk, .pingpong =3D PINGPONG_0, .dspp =3D DSPP_0, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index 7087c3c2e728c51f070b67ab0f8039f74eb7da6c..708cf1544bd1d5c72a125b572e5= 1d628c53f5033 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -57,7 +57,6 @@ static const struct dpu_lm_cfg qcm2290_lm[] =3D { { .name =3D "lm_0", .id =3D LM_0, .base =3D 0x44000, .len =3D 0x320, - .features =3D MIXER_QCM2290_MASK, .sblk =3D &qcm2290_lm_sblk, .pingpong =3D PINGPONG_0, .dspp =3D DSPP_0, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index a2fdbe39e4415c1da1da0517db2284f368bfa07b..b5a3574e2ce43f7f5d47c42fe1b= dd0f084396a9f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -58,7 +58,6 @@ static const struct dpu_lm_cfg sm6375_lm[] =3D { { .name =3D "lm_0", .id =3D LM_0, .base =3D 0x44000, .len =3D 0x320, - .features =3D MIXER_QCM2290_MASK, .sblk =3D &qcm2290_lm_sblk, .lm_pair =3D 0, .pingpong =3D PINGPONG_0, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index e22ad69e451bb5ed38f056e95b0944fb5c21ec7b..5ca696b8cd92cefe295cc7e4597= 4e1da0d420cad 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -90,10 +90,7 @@ (BIT(DPU_MIXER_SOURCESPLIT)) =20 #define MIXER_SDM845_MASK \ - (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER)) - -#define MIXER_QCM2290_MASK \ - (BIT(DPU_DIM_LAYER)) + (BIT(DPU_MIXER_SOURCESPLIT)) =20 #define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \ BIT(DPU_WB_UBWC) | \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index e1fc6fdd8864b017bec35e448ef15420530e018b..8e6fcb51aad8278eb80570a44a4= 23c2443744c61 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -84,14 +84,12 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54e7cb3987csm3852e87.59.2025.04.23.14.11.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Apr 2025 14:11:05 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 24 Apr 2025 00:10:19 +0300 Subject: [PATCH v2 23/33] drm/msm/dpu: get rid of DPU_DSC_HW_REV_1_2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-dpu-drop-features-v2-23-0a9a66a7b3a2@oss.qualcomm.com> References: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> In-Reply-To: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=12855; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=Q3MTIf4rQy+am/uHf/BMkZYmbIwxtrhN/RYvyuNUjQI=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoCVctzKa9fJu4DotHY6EFC71m03848hAFtkbHi rTcVurxiAqJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaAlXLQAKCRCLPIo+Aiko 1Q3cB/0Sxn3FwqWTKfjpLAYxMM1PDjbruGyyi90Cw1OrkKBOEtRehZMQFpq+hlUgi08Thl0Y4k4 YY/qjFhTO7DXxtJxlAk7bVPl7HNVZksR/ANnV6OZgawU1VxszbPsmvD29UcABIraNq9lvpxXJyt 57EkE9bHworM6UiLTvj+2Y3enpWZ7hAkLXtGZGGoGXO/YRAwWOJkipmoO38gCmx3mOXK1D/yEy1 Ke+OQD5Qlb8v5Y7Oa5B9RgxHrUWAIkwK+8YtreOh4DyAzcPmJzYWp76OtJty6FAClJPKaba5b21 9mvA0R27BfQfRkNQocMhS1vlaJKsYJjss12wGzfWPtc8RKlF X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=EtLSrTcA c=1 sm=1 tr=0 ts=6809576e cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=C81KZioEkqZAcCmD564A:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: LzVHbE8NXdCA_UNo0bQNZqa1rEj-6dWi X-Proofpoint-ORIG-GUID: LzVHbE8NXdCA_UNo0bQNZqa1rEj-6dWi X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDIzMDE0NCBTYWx0ZWRfX+MY9pUa1Q6w8 DgYmbyhwpeuHNCFtME+eneaqKrDQBDSTTAWTZ7pUmTzzse3aptNUKrN8iyUs29/Y66xkrfaYw6G cb1iIfO/n/m0+fBw2VPZMT/UdKsocfzOUtlNN5DeeYWqn1P/DujjkcgDPYdv24vmCTM2pGHr/GH Ao18LCehvYbPIwVBDI2OWhVD5HSaYh5uDcBJNcr/vfJSoK2JwylHWJWG4jblxAMDgd2fz3ald8T CcMDyMfi/ymwdaQQre6G4AMvhwKqOxxNyHui3bowIUuWjKH6/a5OB5vrVl80R7Xp4rewFFGZQ1+ vDNx6cFO8977dUPjXp1pk7CG9cwrfN9SLiucNqe6HZ+CUTZhCjblxl0uXEJQSAhV0kDXQyYpBOL GYFtlBfW9tyT7sNwYb9z85nDaMvSjJQM/0G+58AxTDQBSOj/fXEAMhgbU/5qmQx9LfNEqOXh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.680,FMLib:17.12.80.40 definitions=2025-04-23_11,2025-04-22_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 suspectscore=0 mlxscore=0 clxscore=1015 spamscore=0 mlxlogscore=999 lowpriorityscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504230144 From: Dmitry Baryshkov Continue migration to the MDSS-revision based checks and replace DPU_DSC_HW_REV_1_2 feature bit with the core_major_ver >=3D 7 check. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 10 ++++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 6 ++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 8 ++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 6 ++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 8 ++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 6 ++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 6 ++---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +- 11 files changed, 19 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index d64366f608ea673422bbf4e5b6ae7f4ad8570784..5f6b1251f30f3c6dfb20261a0d1= bbf776ed5dd33 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -289,32 +289,30 @@ static const struct dpu_dsc_cfg sm8650_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_2_0", .id =3D DSC_4, .base =3D 0x82000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_2_1", .id =3D DSC_5, .base =3D 0x82000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 62de32268ee5528ff0fb16a3ff7c2baa5ea42466..bb35eea64a5af844965259cd96b= ef10d9955b493 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -266,22 +266,20 @@ static const struct dpu_dsc_cfg sm8350_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 202de6f9b0c65c6f2caa9e9d5232f5b92d8bdf01..d21b2266909050fd20bf55b6fab= e07351e445c5a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -150,7 +150,7 @@ static const struct dpu_dsc_cfg sc7280_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 43916752cfd5836718a3770df4c8767635f77ee9..72110b2a2770435ac886e992b1c= cce280c5ac3db 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -265,32 +265,28 @@ static const struct dpu_dsc_cfg sc8280xp_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_2_0", .id =3D DSC_4, .base =3D 0x82000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_2_1", .id =3D DSC_5, .base =3D 0x82000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index d58d5b7ce79b8c069d111c3c2aa3e9cdb2c1a435..305a798768c60a2ec409c1021a9= 1efc4eccc92fd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -279,22 +279,20 @@ static const struct dpu_dsc_cfg sm8450_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index 064546d4fd4538cd5a6b56fca3ee12d482a7dbb6..67aed1ebc78952c6dfce0cc9f16= 80fa75ec26e13 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -278,32 +278,28 @@ static const struct dpu_dsc_cfg sa8775p_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_2_0", .id =3D DSC_4, .base =3D 0x82000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_2_1", .id =3D DSC_5, .base =3D 0x82000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 959f3e9dbc5455fe53c1bb240b5db57212f2d4eb..b54a208e48a8508c39b4e4e95c9= e26ce28ba7c02 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -275,22 +275,20 @@ static const struct dpu_dsc_cfg sm8550_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index 174cfdfcfdf9860ea86c983c6b6591ba98da5400..da2fdf01a17d29fd9a7ea46890d= b7a33fedee31e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -275,22 +275,20 @@ static const struct dpu_dsc_cfg x1e80100_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2), .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 8e6fcb51aad8278eb80570a44a423c2443744c61..ee8dd66a68f421161961495dd68= d39dd4622ecf6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -178,13 +178,11 @@ enum { * DSC sub-blocks/features * @DPU_DSC_OUTPUT_CTRL Configure which PINGPONG block gets * the pixel output from this DSC. - * @DPU_DSC_HW_REV_1_2 DSC block supports DSC 1.1 and 1.2 * @DPU_DSC_NATIVE_42x_EN Supports NATIVE_422_EN and NATIVE_420_EN enc= oding * @DPU_DSC_MAX */ enum { DPU_DSC_OUTPUT_CTRL =3D 0x1, - DPU_DSC_HW_REV_1_2, DPU_DSC_NATIVE_42x_EN, DPU_DSC_MAX }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index f3f84c8c302fb1bfe6e6d70e4110d0b89259e55c..d44461e7e1641b25c5181bf7c0c= 9bbedffcc869d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1043,7 +1043,7 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_stat= e *disp_state, struct msm_k msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len, base, "%s", cat->dsc[i].name); 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54e7cb3987csm3852e87.59.2025.04.23.14.11.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Apr 2025 14:11:09 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 24 Apr 2025 00:10:20 +0300 Subject: [PATCH v2 24/33] drm/msm/dpu: get rid of DPU_DSC_OUTPUT_CTRL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-dpu-drop-features-v2-24-0a9a66a7b3a2@oss.qualcomm.com> References: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> In-Reply-To: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8937; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=HOkBs/6zBYjscOwL9t+s9f3+kkK5I+SwIYI8RcLTw34=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBoCVctmgVurNwAYEJFpA4Zw9ZG1w4hRQEdFFqVj kg93M3vUnaJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCaAlXLQAKCRCLPIo+Aiko 1f1NB/wMU4ysJvf0NiIhGNgq4avl1Ut1itt5HDEzi3JmSh23hMOp1Mi95CcfDn7Y1OW33FPWHdc nx6ddCXDHRKZdlFMiCiGc2VMaYuuoR7/7p2JTBY1gNE1ngmMgtY5ZXjMx4vk8dOUJSfCbo861vD sX9n+BTW9+bdNJ9cWt16iH6PsBwwe5In36Mucg2agXtnd43GeN+hkoNSghw4rG2sOvdRb9NlpQX yQLjmLcTDwbvMNTJOTO5xYSbptk5JkU7/qjtHaOloj2P7fgIjo4ocsC9QMoXWJSbgvBfrFvw3aw xq2aPY0IBBoUBGlJR40V7uY/kkIP0dK1IMlqQthz/WkiczpV X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: gJ3DsRLb_MqqPXq_I1VQWTTR7P3zsH8j X-Proofpoint-ORIG-GUID: gJ3DsRLb_MqqPXq_I1VQWTTR7P3zsH8j X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDIzMDE0NCBTYWx0ZWRfX9mjwEh4mzeAh VgdD1JxflG/wwl3Ia7wiDOwTjH6NqyKtEGrCaRAq2UDBqJpY4wz+03BUwE4DK82+5tWlW1v3sQB tYW9ykbd92Xiy/jXcl8K/PYNzlU519WsXK+IswiAzks7ZJCs7S2MUr2bYNPAzRLD0yl78cxtgSh AqcwZlFNU7av0HSXPQpbXb0+lheQY725el/yx6cvy/UBIqchMblQm4uHmB83C20IK7Ji8eV48YU ODycXEksHj8JQRa3k7jyykqdTImXkL4vrjcZTHh0PiqdQaIo++8Oq1YehNanl3BJP7iHjLERNo9 cLPrEIkJjX7iiY2Gdd3+9dP2zMW2WqER/jxcCAJlOXmvWv2noKp5fUghD2/rLoMzdKDx7/ZX11c LmCHjaV6xKrgvOpfsbF5OoPO6CaOAa6uCnTgbzUR5Rty57uxcxHnxe+fT2imSnufhEQB5bdz X-Authority-Analysis: v=2.4 cv=ZpjtK87G c=1 sm=1 tr=0 ts=68095772 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=s0E_TIProlikEKm38KMA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.680,FMLib:17.12.80.40 definitions=2025-04-23_11,2025-04-22_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 clxscore=1015 bulkscore=0 suspectscore=0 mlxlogscore=999 spamscore=0 impostorscore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504230144 From: Dmitry Baryshkov Continue migration to the MDSS-revision based checks and replace DPU_DSC_OUTPUT_CTRL feature bit with the core_major_ver >=3D 5 check. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 6 ------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 5 +---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 6 ++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 3 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +- 10 files changed, 8 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index 634b7dc452839f994c948601fe9a09581cb42a42..c5d964e915cdde1f8a83c2793b0= 020d7cecde672 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -262,19 +262,15 @@ static const struct dpu_dsc_cfg sm8150_dsc[] =3D { { .name =3D "dsc_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_1", .id =3D DSC_1, .base =3D 0x80400, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_2", .id =3D DSC_2, .base =3D 0x80800, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_3", .id =3D DSC_3, .base =3D 0x80c00, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index 59e280edcd508c14ee297857a19e9974970566de..dc21c5c232a7ce7d8c21d3a3f30= a5c1bc352ddd7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -261,27 +261,21 @@ static const struct dpu_dsc_cfg sc8180x_dsc[] =3D { { .name =3D "dsc_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_1", .id =3D DSC_1, .base =3D 0x80400, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_2", .id =3D DSC_2, .base =3D 0x80800, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_3", .id =3D DSC_3, .base =3D 0x80c00, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_4", .id =3D DSC_4, .base =3D 0x81000, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_5", .id =3D DSC_5, .base =3D 0x81400, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h index af0d789c47917e9b712282a542c3d0886313c049..c1e620ae9596f400655b64b47e6= b51a8d25e1428 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h @@ -195,11 +195,9 @@ static const struct dpu_dsc_cfg sm7150_dsc[] =3D { { .name =3D "dsc_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_1", .id =3D DSC_1, .base =3D 0x80400, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 4da7445aa8019894b35b12ace18c0bd6209b9148..81af11630202943b910cd5896f0= 7a32e53a23c6a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -261,19 +261,15 @@ static const struct dpu_dsc_cfg sm8250_dsc[] =3D { { .name =3D "dsc_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_1", .id =3D DSC_1, .base =3D 0x80400, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_2", .id =3D DSC_2, .base =3D 0x80800, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, { .name =3D "dsc_3", .id =3D DSC_3, .base =3D 0x80c00, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index 6563296190bb27b6cab1b03921af6cff34037cd2..8cdd601a5350e80a5324db42c23= bdeb474a59b0c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -135,7 +135,6 @@ static const struct dpu_dsc_cfg sm6350_dsc[] =3D { { .name =3D "dsc_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index b5a3574e2ce43f7f5d47c42fe1bdd0f084396a9f..c08d8bae3293d00ef7ff2894269= 9ae2a52e2cea9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -87,7 +87,6 @@ static const struct dpu_dsc_cfg sm6375_dsc[] =3D { { .name =3D "dsc_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x140, - .features =3D BIT(DPU_DSC_OUTPUT_CTRL), }, }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index ee8dd66a68f421161961495dd68d39dd4622ecf6..981d259c33631d31f0216f5cfae= 948b828d03592 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -176,14 +176,11 @@ enum { =20 /** * DSC sub-blocks/features - * @DPU_DSC_OUTPUT_CTRL Configure which PINGPONG block gets - * the pixel output from this DSC. * @DPU_DSC_NATIVE_42x_EN Supports NATIVE_422_EN and NATIVE_420_EN enc= oding * @DPU_DSC_MAX */ enum { - DPU_DSC_OUTPUT_CTRL =3D 0x1, - DPU_DSC_NATIVE_42x_EN, + DPU_DSC_NATIVE_42x_EN =3D 0x1, DPU_DSC_MAX }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_dsc.c index c7db917afd27e3daf1e8aad2ad671246bf6c8fbf..3a149caa7ff4f20dc7a902033cf= 29a168268839e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c @@ -186,11 +186,13 @@ static void dpu_hw_dsc_bind_pingpong_blk( * @dev: Corresponding device for devres management * @cfg: DSC catalog entry for which driver object is required * @addr: Mapped register io address of MDP + * @mdss_ver: dpu core's major and minor versions * Return: Error code or allocated dpu_hw_dsc context */ struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev, const struct dpu_dsc_cfg *cfg, - void __iomem *addr) + void __iomem *addr, + const struct dpu_mdss_version *mdss_ver) { struct dpu_hw_dsc *c; =20 @@ -207,7 +209,7 @@ struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *d= ev, c->ops.dsc_disable =3D dpu_hw_dsc_disable; c->ops.dsc_config =3D dpu_hw_dsc_config; c->ops.dsc_config_thresh =3D dpu_hw_dsc_config_thresh; - if (c->caps->features & BIT(DPU_DSC_OUTPUT_CTRL)) + if (mdss_ver->core_major_ver >=3D 5) c->ops.dsc_bind_pingpong_blk =3D dpu_hw_dsc_bind_pingpong_blk; =20 return c; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_dsc.h index fc171bdeca488f6287cf2ba7362ed330ad55b28f..b7013c9822d23238eb5411a5e28= 4bb072ecc3395 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h @@ -64,7 +64,8 @@ struct dpu_hw_dsc { =20 struct dpu_hw_dsc *dpu_hw_dsc_init(struct drm_device *dev, const struct dpu_dsc_cfg *cfg, - void __iomem *addr); + void __iomem *addr, + const struct dpu_mdss_version *mdss_ver); =20 struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(struct drm_device *dev, const struct dpu_dsc_cfg *cfg, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.c index f917ffb85d2f1b1a0ee826f125d02980b7a79052..f118c6caa1b9007eb03fa9b39ef= a87dfb46583ba 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -169,7 +169,7 @@ int dpu_rm_init(struct drm_device *dev, if (cat->mdss_ver->core_major_ver >=3D 7) hw =3D dpu_hw_dsc_init_1_2(dev, dsc, mmio); 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Signed-off-by: Dmitry Baryshkov Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 2 +- 18 files changed, 16 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index 5f6b1251f30f3c6dfb20261a0d1bbf776ed5dd33..02bb3d01e2dcfb881d089c68b51= 6abe1761f692d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -321,7 +321,7 @@ static const struct dpu_wb_cfg sm8650_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .xin_id =3D 6, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index c5d964e915cdde1f8a83c2793b0020d7cecde672..e1490dd6d0b35ef71b91b4b7dbc= 574b102e68652 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -278,7 +278,7 @@ static const struct dpu_wb_cfg sm8150_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl =3D DPU_CLK_CTRL_WB2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index dc21c5c232a7ce7d8c21d3a3f30a5c1bc352ddd7..c53a0376fc3d040b69a35896aad= 613ff8aec73b6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -283,7 +283,7 @@ static const struct dpu_wb_cfg sc8180x_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl =3D DPU_CLK_CTRL_WB2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h index c1e620ae9596f400655b64b47e6b51a8d25e1428..f72c986079803ec0d60f0bd6545= ee0812657b8f2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h @@ -243,7 +243,7 @@ static const struct dpu_wb_cfg sm7150_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl =3D DPU_CLK_CTRL_WB2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h index 8fb926bff36d32fb4ce1036cb69513599dc7b6b7..a065f102ce592311376f1186add= 7a47dca7fd84f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h @@ -154,7 +154,7 @@ static const struct dpu_wb_cfg sm6150_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl =3D DPU_CLK_CTRL_WB2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h index af7433fc6c128c2e29381ba6bf56388bccdd93f8..8c909c41b48a18fdc54753c68bc= 2ad19001cd3b4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h @@ -133,7 +133,7 @@ static const struct dpu_wb_cfg sm6125_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl =3D DPU_CLK_CTRL_WB2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 81af11630202943b910cd5896f07a32e53a23c6a..448ec3def8c7e3e77ce0740e245= 88a14b0a44da7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -315,7 +315,7 @@ static const struct dpu_wb_cfg sm8250_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl =3D DPU_CLK_CTRL_WB2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index 77126039733bbb2941aa6698bb353334efab3804..f091503840182b624471c62ada5= f8cb813a707bb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -148,7 +148,7 @@ static const struct dpu_wb_cfg sc7180_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl =3D DPU_CLK_CTRL_WB2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index 8cdd601a5350e80a5324db42c23bdeb474a59b0c..f4cd9405cc1f0589bce7ec68db6= 8989bd24b2faa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -142,7 +142,7 @@ static const struct dpu_wb_cfg sm6350_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl =3D DPU_CLK_CTRL_WB2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index bb35eea64a5af844965259cd96bef10d9955b493..f4572433f352fb2c939b80c31e9= 0bc2bfaa2a057 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -288,7 +288,7 @@ static const struct dpu_wb_cfg sm8350_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl =3D DPU_CLK_CTRL_WB2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index d21b2266909050fd20bf55b6fabe07351e445c5a..d312b7ff375ebb0bb5159c4d26e= adc6eb3094103 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -159,7 +159,7 @@ static const struct dpu_wb_cfg sc7280_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl =3D DPU_CLK_CTRL_WB2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 305a798768c60a2ec409c1021a91efc4eccc92fd..72b2f67bb70eb09a3340097da60= 20a40cfbf87fb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -301,7 +301,7 @@ static const struct dpu_wb_cfg sm8450_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl =3D DPU_CLK_CTRL_WB2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index 67aed1ebc78952c6dfce0cc9f1680fa75ec26e13..de7e79680a7353e73bb2c761276= edd9ddc25ce97 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -308,7 +308,7 @@ static const struct dpu_wb_cfg sa8775p_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .clk_ctrl =3D DPU_CLK_CTRL_WB2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index b54a208e48a8508c39b4e4e95c9e26ce28ba7c02..674192923d8c184386e46870afc= 508e53917ff6c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -297,7 +297,7 @@ static const struct dpu_wb_cfg sm8550_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .xin_id =3D 6, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index da2fdf01a17d29fd9a7ea46890db7a33fedee31e..6cd7ddeb2b1fceed4cebc1f8679= 3831b1cb75945 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -297,7 +297,7 @@ static const struct dpu_wb_cfg x1e80100_wb[] =3D { { .name =3D "wb_2", .id =3D WB_2, .base =3D 0x65000, .len =3D 0x2c8, - .features =3D WB_SM8250_MASK, + .features =3D WB_SDM845_MASK, .format_list =3D wb2_formats_rgb_yuv, .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), .xin_id =3D 6, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 5ca696b8cd92cefe295cc7e45974e1da0d420cad..6a96fa529508673493712d7cb72= 846c29d0f5a07 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -101,9 +101,6 @@ BIT(DPU_WB_QOS_8LVL) | \ BIT(DPU_WB_CDP)) =20 -#define WB_SM8250_MASK (WB_SDM845_MASK | \ - BIT(DPU_WB_INPUT_CTRL)) - #define DEFAULT_PIXEL_RAM_SIZE (50 * 1024) #define DEFAULT_DPU_LINE_WIDTH 2048 #define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 981d259c33631d31f0216f5cfae948b828d03592..e0efa65afd0b734234f1080baf2= d91e348882dcf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -142,8 +142,6 @@ enum { * @DPU_WB_QOS, Writeback supports QoS control, danger/safe/c= req * @DPU_WB_QOS_8LVL, Writeback supports 8-level QoS control * @DPU_WB_CDP Writeback supports client driven prefetch - * @DPU_WB_INPUT_CTRL Writeback supports from which pp block input = pixel - * data arrives. * @DPU_WB_CROP CWB supports cropping * @DPU_WB_MAX maximum value */ @@ -157,7 +155,6 @@ enum { DPU_WB_QOS, DPU_WB_QOS_8LVL, DPU_WB_CDP, - DPU_WB_INPUT_CTRL, DPU_WB_CROP, DPU_WB_MAX }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_hw_wb.c index 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Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 5 ++++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 2 ++ 4 files changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 6a96fa529508673493712d7cb72846c29d0f5a07..8496a44e2f04edeec884e1bac02= 9c513022bf79a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -35,12 +35,12 @@ (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE)) =20 #define VIG_SDM845_MASK \ - (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBL= E)) + (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE)) =20 #define VIG_SDM845_MASK_SDMA \ (VIG_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) =20 -#define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL)) +#define VIG_QCM2290_MASK (VIG_BASE_MASK) =20 #define DMA_MSM8953_MASK \ (BIT(DPU_SSPP_QOS)) @@ -60,7 +60,7 @@ (VIG_SC7280_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) =20 #define DMA_SDM845_MASK \ - (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ + (BIT(DPU_SSPP_QOS) | \ BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index e0efa65afd0b734234f1080baf2d91e348882dcf..01763e0bf1359527b0c441ca36b= 27264dad636c0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -50,7 +50,6 @@ enum { * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion * @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer * @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq - * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support @@ -68,7 +67,6 @@ enum { DPU_SSPP_CSC_10BIT, DPU_SSPP_CURSOR, DPU_SSPP_QOS, - DPU_SSPP_QOS_8LVL, DPU_SSPP_EXCL_RECT, DPU_SSPP_SMART_DMA_V1, DPU_SSPP_SMART_DMA_V2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_sspp.c index 32c7c80845533d720683dbcde3978d98f4972cce..7dfd0e0a779535e1f6b003f4818= 8bc90d29d6853 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -543,7 +543,7 @@ static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_ssp= p *ctx, return; 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Other feature bits are completely unused. Drop them from the current codebase. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 14 -------------- 6 files changed, 23 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h index 436fa56e2ba2d867b58b59ec6b02d1d0f396c23b..7f606be1f79fe83568b467c47e7= 280537f1ce091 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h @@ -180,14 +180,12 @@ static const struct dpu_pingpong_cfg msm8996_pp[] =3D= { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D BIT(DPU_PINGPONG_TE2), .sblk =3D &msm8996_pp_sblk_te, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x70800, .len =3D 0xd4, - .features =3D BIT(DPU_PINGPONG_TE2), .sblk =3D &msm8996_pp_sblk_te, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index 38cdea019bf2b1391c242953e4c67d9dc4c2274c..a10ca16d2d63d8b6e2e2165dcd4= bf0cf915f8e3d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -169,14 +169,12 @@ static const struct dpu_pingpong_cfg msm8998_pp[] =3D= { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D BIT(DPU_PINGPONG_TE2), .sblk =3D &sdm845_pp_sblk_te, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x70800, .len =3D 0xd4, - .features =3D BIT(DPU_PINGPONG_TE2), .sblk =3D &sdm845_pp_sblk_te, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h index 176640bff1214e89606286ce572f74300f6f343f..c1fc91b3f6f85af18cf6a6c1690= ec69074fc3545 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h @@ -140,14 +140,12 @@ static const struct dpu_pingpong_cfg sdm660_pp[] =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D BIT(DPU_PINGPONG_TE2), .sblk =3D &sdm845_pp_sblk_te, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x70800, .len =3D 0xd4, - .features =3D BIT(DPU_PINGPONG_TE2), .sblk =3D &sdm845_pp_sblk_te, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h index e6eb95173cfef2a52f5dc606ca41a2f1f5650c2c..65975e7ebd9ba1970b48d8753a8= 7835677d58df7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h @@ -114,7 +114,6 @@ static const struct dpu_pingpong_cfg sdm630_pp[] =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D BIT(DPU_PINGPONG_TE2), .sblk =3D &sdm845_pp_sblk_te, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 21264184566493ab4e356a4e0c032ee7780cabff..8d5b7033f12f740fe7b9226e93f= cece8ed54b890 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -189,14 +189,12 @@ static const struct dpu_pingpong_cfg sdm845_pp[] =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D BIT(DPU_PINGPONG_TE2), .sblk =3D &sdm845_pp_sblk_te, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x70800, .len =3D 0xd4, - .features =3D BIT(DPU_PINGPONG_TE2), .sblk =3D &sdm845_pp_sblk_te, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= 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Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 ------ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 12 ++---------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 3 +-- 23 files changed, 96 insertions(+), 111 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index 02bb3d01e2dcfb881d089c68b516abe1761f692d..2007aedc0526854d3d8c4eface5= b507dc5c62c58 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -135,7 +135,7 @@ static const struct dpu_lm_cfg sm8650_lm[] =3D { { .name =3D "lm_0", .id =3D LM_0, .base =3D 0x44000, .len =3D 0x400, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_1, .pingpong =3D PINGPONG_0, @@ -143,7 +143,7 @@ static const struct dpu_lm_cfg sm8650_lm[] =3D { }, { .name =3D "lm_1", .id =3D LM_1, .base =3D 0x45000, .len =3D 0x400, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_0, .pingpong =3D PINGPONG_1, @@ -151,7 +151,7 @@ static const struct dpu_lm_cfg sm8650_lm[] =3D { }, { .name =3D "lm_2", .id =3D LM_2, .base =3D 0x46000, .len =3D 0x400, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_3, .pingpong =3D PINGPONG_2, @@ -159,7 +159,7 @@ static const struct dpu_lm_cfg sm8650_lm[] =3D { }, { .name =3D "lm_3", .id =3D LM_3, .base =3D 0x47000, .len =3D 0x400, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_2, .pingpong =3D PINGPONG_3, @@ -167,14 +167,14 @@ static const struct dpu_lm_cfg sm8650_lm[] =3D { }, { .name =3D "lm_4", .id =3D LM_4, .base =3D 0x48000, .len =3D 0x400, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_5, .pingpong =3D PINGPONG_4, }, { .name =3D "lm_5", .id =3D LM_5, .base =3D 0x49000, .len =3D 0x400, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_4, .pingpong =3D PINGPONG_5, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h index 7f606be1f79fe83568b467c47e7280537f1ce091..4cebdaddd797eb052acf087b1cd= 1a1302ff42fc7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h @@ -146,7 +146,7 @@ static const struct dpu_lm_cfg msm8996_lm[] =3D { { .name =3D "lm_0", .id =3D LM_0, .base =3D 0x44000, .len =3D 0x320, - .features =3D MIXER_MSM8998_MASK, + .sourcesplit =3D 1, .sblk =3D &msm8998_lm_sblk, .lm_pair =3D LM_1, .pingpong =3D PINGPONG_0, @@ -154,7 +154,7 @@ static const struct dpu_lm_cfg msm8996_lm[] =3D { }, { .name =3D "lm_1", .id =3D LM_1, .base =3D 0x45000, .len =3D 0x320, - .features =3D MIXER_MSM8998_MASK, + .sourcesplit =3D 1, .sblk =3D &msm8998_lm_sblk, .lm_pair =3D LM_0, .pingpong =3D PINGPONG_1, @@ -162,14 +162,14 @@ static const struct dpu_lm_cfg msm8996_lm[] =3D { }, { .name =3D "lm_2", .id =3D LM_2, .base =3D 0x46000, .len =3D 0x320, - .features =3D MIXER_MSM8998_MASK, + .sourcesplit =3D 1, .sblk =3D &msm8998_lm_sblk, .lm_pair =3D LM_5, .pingpong =3D PINGPONG_2, }, { .name =3D "lm_5", .id =3D LM_5, .base =3D 0x49000, .len =3D 0x320, - .features =3D MIXER_MSM8998_MASK, + .sourcesplit =3D 1, .sblk =3D &msm8998_lm_sblk, .lm_pair =3D LM_2, .pingpong =3D PINGPONG_3, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index a10ca16d2d63d8b6e2e2165dcd4bf0cf915f8e3d..1f119f79545eb1f4c6d27fe9fcb= 2a22d038cc571 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -135,7 +135,7 @@ static const struct dpu_lm_cfg msm8998_lm[] =3D { { .name =3D "lm_0", .id =3D LM_0, .base =3D 0x44000, .len =3D 0x320, - .features =3D MIXER_MSM8998_MASK, + .sourcesplit =3D 1, .sblk =3D &msm8998_lm_sblk, .lm_pair =3D LM_1, .pingpong =3D PINGPONG_0, @@ -143,7 +143,7 @@ static const struct dpu_lm_cfg msm8998_lm[] =3D { }, { .name =3D "lm_1", .id =3D LM_1, .base =3D 0x45000, .len =3D 0x320, - .features =3D MIXER_MSM8998_MASK, + .sourcesplit =3D 1, .sblk =3D &msm8998_lm_sblk, .lm_pair =3D LM_0, .pingpong =3D PINGPONG_1, @@ -151,14 +151,14 @@ static const struct dpu_lm_cfg msm8998_lm[] =3D { }, { .name =3D "lm_2", .id =3D LM_2, .base =3D 0x46000, .len =3D 0x320, - .features =3D MIXER_MSM8998_MASK, + .sourcesplit =3D 1, .sblk =3D &msm8998_lm_sblk, .lm_pair =3D LM_5, .pingpong =3D PINGPONG_2, }, { .name =3D "lm_5", .id =3D LM_5, .base =3D 0x49000, .len =3D 0x320, - .features =3D MIXER_MSM8998_MASK, + .sourcesplit =3D 1, .sblk =3D &msm8998_lm_sblk, .lm_pair =3D LM_2, .pingpong =3D PINGPONG_3, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h index c1fc91b3f6f85af18cf6a6c1690ec69074fc3545..c8008db5772498d3bb85596518a= 3a21395fc9491 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h @@ -106,7 +106,7 @@ static const struct dpu_lm_cfg sdm660_lm[] =3D { { .name =3D "lm_0", .id =3D LM_0, .base =3D 0x44000, .len =3D 0x320, - .features =3D MIXER_MSM8998_MASK, + .sourcesplit =3D 1, .sblk =3D &msm8998_lm_sblk, .lm_pair =3D LM_1, .pingpong =3D PINGPONG_0, @@ -114,7 +114,7 @@ static const struct dpu_lm_cfg sdm660_lm[] =3D { }, { .name =3D "lm_1", .id =3D LM_1, .base =3D 0x45000, .len =3D 0x320, - .features =3D MIXER_MSM8998_MASK, + .sourcesplit =3D 1, .sblk =3D &msm8998_lm_sblk, .lm_pair =3D LM_0, .pingpong =3D PINGPONG_1, @@ -122,14 +122,14 @@ static const struct dpu_lm_cfg sdm660_lm[] =3D { }, { .name =3D "lm_2", .id =3D LM_2, .base =3D 0x46000, .len =3D 0x320, - .features =3D MIXER_MSM8998_MASK, + .sourcesplit =3D 1, .sblk =3D &msm8998_lm_sblk, .lm_pair =3D LM_5, .pingpong =3D PINGPONG_2, }, { .name =3D "lm_5", .id =3D LM_5, .base =3D 0x49000, .len =3D 0x320, - .features =3D MIXER_MSM8998_MASK, + .sourcesplit =3D 1, .sblk =3D &msm8998_lm_sblk, .lm_pair =3D LM_2, .pingpong =3D PINGPONG_3, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h index 65975e7ebd9ba1970b48d8753a87835677d58df7..70d7751831b738d40ab7e736ddb= 442c4d44e982e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h @@ -97,14 +97,14 @@ static const struct dpu_lm_cfg sdm630_lm[] =3D { { .name =3D "lm_0", .id =3D LM_0, .base =3D 0x44000, .len =3D 0x320, - .features =3D MIXER_MSM8998_MASK, + .sourcesplit =3D 1, .sblk =3D &msm8998_lm_sblk, .pingpong =3D PINGPONG_0, .dspp =3D DSPP_0, }, { .name =3D "lm_2", .id =3D LM_2, .base =3D 0x46000, .len =3D 0x320, - .features =3D MIXER_MSM8998_MASK, + .sourcesplit =3D 1, .sblk =3D &msm8998_lm_sblk, .pingpong =3D PINGPONG_2, }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 8d5b7033f12f740fe7b9226e93fcece8ed54b890..1218a3585cbc8664194692cdd26= 39af1c7888c39 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -133,7 +133,7 @@ static const struct dpu_lm_cfg sdm845_lm[] =3D { { .name =3D "lm_0", .id =3D LM_0, .base =3D 0x44000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_1, .pingpong =3D PINGPONG_0, @@ -141,7 +141,7 @@ static const struct dpu_lm_cfg sdm845_lm[] =3D { }, { .name =3D "lm_1", .id =3D LM_1, .base =3D 0x45000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_0, .pingpong =3D PINGPONG_1, @@ -149,7 +149,7 @@ static const struct dpu_lm_cfg sdm845_lm[] =3D { }, { .name =3D "lm_2", .id =3D LM_2, .base =3D 0x46000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_5, .pingpong =3D PINGPONG_2, @@ -157,7 +157,7 @@ static const struct dpu_lm_cfg sdm845_lm[] =3D { }, { .name =3D "lm_5", .id =3D LM_5, .base =3D 0x49000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_2, .pingpong =3D PINGPONG_3, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h index ce169a610e195cbb6f0fee1362bcaaf05df777cb..fd95933a41f0d604b7abb9cebb9= 5520905211d33 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h @@ -68,7 +68,7 @@ static const struct dpu_lm_cfg sdm670_lm[] =3D { { .name =3D "lm_0", .id =3D LM_0, .base =3D 0x44000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_1, .pingpong =3D PINGPONG_0, @@ -76,7 +76,7 @@ static const struct dpu_lm_cfg sdm670_lm[] =3D { }, { .name =3D "lm_1", .id =3D LM_1, .base =3D 0x45000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_0, .pingpong =3D PINGPONG_1, @@ -84,14 +84,14 @@ static const struct dpu_lm_cfg sdm670_lm[] =3D { }, { .name =3D "lm_2", .id =3D LM_2, .base =3D 0x46000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_5, .pingpong =3D PINGPONG_2, }, { .name =3D "lm_5", .id =3D LM_5, .base =3D 0x49000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_2, .pingpong =3D PINGPONG_3, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index e1490dd6d0b35ef71b91b4b7dbc574b102e68652..520f5cd122dd331ca1a1d9cc1eb= d7654264f3e52 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -139,7 +139,7 @@ static const struct dpu_lm_cfg sm8150_lm[] =3D { { .name =3D "lm_0", .id =3D LM_0, .base =3D 0x44000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_1, .pingpong =3D PINGPONG_0, @@ -147,7 +147,7 @@ static const struct dpu_lm_cfg sm8150_lm[] =3D { }, { .name =3D "lm_1", .id =3D LM_1, .base =3D 0x45000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_0, .pingpong =3D PINGPONG_1, @@ -155,7 +155,7 @@ static const struct dpu_lm_cfg sm8150_lm[] =3D { }, { .name =3D "lm_2", .id =3D LM_2, .base =3D 0x46000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_3, .pingpong =3D PINGPONG_2, @@ -163,7 +163,7 @@ static const struct dpu_lm_cfg sm8150_lm[] =3D { }, { .name =3D "lm_3", .id =3D LM_3, .base =3D 0x47000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_2, .pingpong =3D PINGPONG_3, @@ -171,14 +171,14 @@ static const struct dpu_lm_cfg sm8150_lm[] =3D { }, { .name =3D "lm_4", .id =3D LM_4, .base =3D 0x48000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_5, .pingpong =3D PINGPONG_4, }, { .name =3D "lm_5", .id =3D LM_5, .base =3D 0x49000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_4, .pingpong =3D PINGPONG_5, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index c53a0376fc3d040b69a35896aad613ff8aec73b6..c1827c80e7efef9c57757e0b535= 35d9fbba30c05 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -138,7 +138,7 @@ static const struct dpu_lm_cfg sc8180x_lm[] =3D { { .name =3D "lm_0", .id =3D LM_0, .base =3D 0x44000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_1, .pingpong =3D PINGPONG_0, @@ -146,7 +146,7 @@ static const struct dpu_lm_cfg sc8180x_lm[] =3D { }, { .name =3D "lm_1", .id =3D LM_1, .base =3D 0x45000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_0, .pingpong =3D PINGPONG_1, @@ -154,7 +154,7 @@ static const struct dpu_lm_cfg sc8180x_lm[] =3D { }, { .name =3D "lm_2", .id =3D LM_2, .base =3D 0x46000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_3, .pingpong =3D PINGPONG_2, @@ -162,7 +162,7 @@ static const struct dpu_lm_cfg sc8180x_lm[] =3D { }, { .name =3D "lm_3", .id =3D LM_3, .base =3D 0x47000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_2, .pingpong =3D PINGPONG_3, @@ -170,14 +170,14 @@ static const struct dpu_lm_cfg sc8180x_lm[] =3D { }, { .name =3D "lm_4", .id =3D LM_4, .base =3D 0x48000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_5, .pingpong =3D PINGPONG_4, }, { .name =3D "lm_5", .id =3D LM_5, .base =3D 0x49000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_4, .pingpong =3D PINGPONG_5, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h index f72c986079803ec0d60f0bd6545ee0812657b8f2..d4c7c59e1ba845e087bcbc3394f= c972a9058943d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h @@ -111,7 +111,7 @@ static const struct dpu_lm_cfg sm7150_lm[] =3D { { .name =3D "lm_0", .id =3D LM_0, .base =3D 0x44000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_1, .pingpong =3D PINGPONG_0, @@ -119,7 +119,7 @@ static const struct dpu_lm_cfg sm7150_lm[] =3D { }, { .name =3D "lm_1", .id =3D LM_1, .base =3D 0x45000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_0, .pingpong =3D PINGPONG_1, @@ -127,14 +127,14 @@ static const struct dpu_lm_cfg sm7150_lm[] =3D { }, { .name =3D "lm_2", .id =3D LM_2, .base =3D 0x46000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_3, .pingpong =3D PINGPONG_2, }, { .name =3D "lm_3", .id =3D LM_3, .base =3D 0x47000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_2, .pingpong =3D PINGPONG_3, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 448ec3def8c7e3e77ce0740e24588a14b0a44da7..50eea89a885ecf0d4ff4f478e6d= 356d86285bb3e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -138,7 +138,7 @@ static const struct dpu_lm_cfg sm8250_lm[] =3D { { .name =3D "lm_0", .id =3D LM_0, .base =3D 0x44000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_1, .pingpong =3D PINGPONG_0, @@ -146,7 +146,7 @@ static const struct dpu_lm_cfg sm8250_lm[] =3D { }, { .name =3D "lm_1", .id =3D LM_1, .base =3D 0x45000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_0, .pingpong =3D PINGPONG_1, @@ -154,7 +154,7 @@ static const struct dpu_lm_cfg sm8250_lm[] =3D { }, { .name =3D "lm_2", .id =3D LM_2, .base =3D 0x46000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_3, .pingpong =3D PINGPONG_2, @@ -162,7 +162,7 @@ static const struct dpu_lm_cfg sm8250_lm[] =3D { }, { .name =3D "lm_3", .id =3D LM_3, .base =3D 0x47000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_2, .pingpong =3D PINGPONG_3, @@ -170,14 +170,14 @@ static const struct dpu_lm_cfg sm8250_lm[] =3D { }, { .name =3D "lm_4", .id =3D LM_4, .base =3D 0x48000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_5, .pingpong =3D PINGPONG_4, }, { .name =3D "lm_5", .id =3D LM_5, .base =3D 0x49000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_4, .pingpong =3D PINGPONG_5, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index f091503840182b624471c62ada5f8cb813a707bb..f7f949d2b0b3068e74bb974f4a7= f2a46257a53d3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -84,7 +84,7 @@ static const struct dpu_lm_cfg sc7180_lm[] =3D { { .name =3D "lm_0", .id =3D LM_0, .base =3D 0x44000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sc7180_lm_sblk, .lm_pair =3D LM_1, .pingpong =3D PINGPONG_0, @@ -92,7 +92,7 @@ static const struct dpu_lm_cfg sc7180_lm[] =3D { }, { .name =3D "lm_1", .id =3D LM_1, .base =3D 0x45000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sc7180_lm_sblk, .lm_pair =3D LM_0, .pingpong =3D PINGPONG_1, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index f4cd9405cc1f0589bce7ec68db68989bd24b2faa..2d9a20568f6956368c5efbe154c= f2ce1d3a559e8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -91,7 +91,7 @@ static const struct dpu_lm_cfg sm6350_lm[] =3D { { .name =3D "lm_0", .id =3D LM_0, .base =3D 0x44000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sc7180_lm_sblk, .lm_pair =3D LM_1, .pingpong =3D PINGPONG_0, @@ -99,7 +99,7 @@ static const struct dpu_lm_cfg sm6350_lm[] =3D { }, { .name =3D "lm_1", .id =3D LM_1, .base =3D 0x45000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sc7180_lm_sblk, .lm_pair =3D LM_0, .pingpong =3D PINGPONG_1, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index f4572433f352fb2c939b80c31e90bc2bfaa2a057..2c59f0b77a75880df18900fa406= f1ea7006927a1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -138,7 +138,7 @@ static const struct dpu_lm_cfg sm8350_lm[] =3D { { .name =3D "lm_0", .id =3D LM_0, .base =3D 0x44000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_1, .pingpong =3D PINGPONG_0, @@ -146,7 +146,7 @@ static const struct dpu_lm_cfg sm8350_lm[] =3D { }, { .name =3D "lm_1", .id =3D LM_1, .base =3D 0x45000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_0, .pingpong =3D PINGPONG_1, @@ -154,7 +154,7 @@ static const struct dpu_lm_cfg sm8350_lm[] =3D { }, { .name =3D "lm_2", .id =3D LM_2, .base =3D 0x46000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_3, .pingpong =3D PINGPONG_2, @@ -162,7 +162,7 @@ static const struct dpu_lm_cfg sm8350_lm[] =3D { }, { .name =3D "lm_3", .id =3D LM_3, .base =3D 0x47000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_2, .pingpong =3D PINGPONG_3, @@ -170,14 +170,14 @@ static const struct dpu_lm_cfg sm8350_lm[] =3D { }, { .name =3D "lm_4", .id =3D LM_4, .base =3D 0x48000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_5, .pingpong =3D PINGPONG_4, }, { .name =3D "lm_5", .id =3D LM_5, .base =3D 0x49000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_4, .pingpong =3D PINGPONG_5, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index d312b7ff375ebb0bb5159c4d26eadc6eb3094103..cbc7e9081288fb8125438ad1cc0= 016042bf70661 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -88,21 +88,21 @@ static const struct dpu_lm_cfg sc7280_lm[] =3D { { .name =3D "lm_0", .id =3D LM_0, .base =3D 0x44000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sc7180_lm_sblk, .pingpong =3D PINGPONG_0, .dspp =3D DSPP_0, }, { .name =3D "lm_2", .id =3D LM_2, .base =3D 0x46000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sc7180_lm_sblk, .lm_pair =3D LM_3, .pingpong =3D PINGPONG_2, }, { .name =3D "lm_3", .id =3D LM_3, .base =3D 0x47000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sc7180_lm_sblk, .lm_pair =3D LM_2, .pingpong =3D PINGPONG_3, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 72110b2a2770435ac886e992b1ccce280c5ac3db..0238eb019d98ad5599cc301e47b= da43de762b24d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -137,7 +137,7 @@ static const struct dpu_lm_cfg sc8280xp_lm[] =3D { { .name =3D "lm_0", .id =3D LM_0, .base =3D 0x44000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_1, .pingpong =3D PINGPONG_0, @@ -145,7 +145,7 @@ static const struct dpu_lm_cfg sc8280xp_lm[] =3D { }, { .name =3D "lm_1", .id =3D LM_1, .base =3D 0x45000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_0, .pingpong =3D PINGPONG_1, @@ -153,7 +153,7 @@ static const struct dpu_lm_cfg sc8280xp_lm[] =3D { }, { .name =3D "lm_2", .id =3D LM_2, .base =3D 0x46000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_3, .pingpong =3D PINGPONG_2, @@ -161,7 +161,7 @@ static const struct dpu_lm_cfg sc8280xp_lm[] =3D { }, { .name =3D "lm_3", .id =3D LM_3, .base =3D 0x47000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_2, .pingpong =3D PINGPONG_3, @@ -169,14 +169,14 @@ static const struct dpu_lm_cfg sc8280xp_lm[] =3D { }, { .name =3D "lm_4", .id =3D LM_4, .base =3D 0x48000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_5, .pingpong =3D PINGPONG_4, }, { .name =3D "lm_5", .id =3D LM_5, .base =3D 0x49000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_4, .pingpong =3D PINGPONG_5, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 72b2f67bb70eb09a3340097da6020a40cfbf87fb..3b2d99de20621a5c47a31212d7f= b236e0b784d0a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -138,7 +138,7 @@ static const struct dpu_lm_cfg sm8450_lm[] =3D { { .name =3D "lm_0", .id =3D LM_0, .base =3D 0x44000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_1, .pingpong =3D PINGPONG_0, @@ -146,7 +146,7 @@ static const struct dpu_lm_cfg sm8450_lm[] =3D { }, { .name =3D "lm_1", .id =3D LM_1, .base =3D 0x45000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_0, .pingpong =3D PINGPONG_1, @@ -154,7 +154,7 @@ static const struct dpu_lm_cfg sm8450_lm[] =3D { }, { .name =3D "lm_2", .id =3D LM_2, .base =3D 0x46000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_3, .pingpong =3D PINGPONG_2, @@ -162,7 +162,7 @@ static const struct dpu_lm_cfg sm8450_lm[] =3D { }, { .name =3D "lm_3", .id =3D LM_3, .base =3D 0x47000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_2, .pingpong =3D PINGPONG_3, @@ -170,14 +170,14 @@ static const struct dpu_lm_cfg sm8450_lm[] =3D { }, { .name =3D "lm_4", .id =3D LM_4, .base =3D 0x48000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_5, .pingpong =3D PINGPONG_4, }, { .name =3D "lm_5", .id =3D LM_5, .base =3D 0x49000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_4, .pingpong =3D PINGPONG_5, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index de7e79680a7353e73bb2c761276edd9ddc25ce97..14a1781c19bd8060d338ea52684= f756258526996 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -137,7 +137,7 @@ static const struct dpu_lm_cfg sa8775p_lm[] =3D { { .name =3D "lm_0", .id =3D LM_0, .base =3D 0x44000, .len =3D 0x400, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_1, .pingpong =3D PINGPONG_0, @@ -145,7 +145,7 @@ static const struct dpu_lm_cfg sa8775p_lm[] =3D { }, { .name =3D "lm_1", .id =3D LM_1, .base =3D 0x45000, .len =3D 0x400, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_0, .pingpong =3D PINGPONG_1, @@ -153,7 +153,7 @@ static const struct dpu_lm_cfg sa8775p_lm[] =3D { }, { .name =3D "lm_2", .id =3D LM_2, .base =3D 0x46000, .len =3D 0x400, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_3, .pingpong =3D PINGPONG_2, @@ -161,7 +161,7 @@ static const struct dpu_lm_cfg sa8775p_lm[] =3D { }, { .name =3D "lm_3", .id =3D LM_3, .base =3D 0x47000, .len =3D 0x400, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_2, .pingpong =3D PINGPONG_3, @@ -169,14 +169,14 @@ static const struct dpu_lm_cfg sa8775p_lm[] =3D { }, { .name =3D "lm_4", .id =3D LM_4, .base =3D 0x48000, .len =3D 0x400, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_5, .pingpong =3D PINGPONG_4, }, { .name =3D "lm_5", .id =3D LM_5, .base =3D 0x49000, .len =3D 0x400, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_4, .pingpong =3D PINGPONG_5, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 674192923d8c184386e46870afc508e53917ff6c..f6893c7ea13bc0ac84b46d50a13= 2e18e1c575a3d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -135,7 +135,7 @@ static const struct dpu_lm_cfg sm8550_lm[] =3D { { .name =3D "lm_0", .id =3D LM_0, .base =3D 0x44000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_1, .pingpong =3D PINGPONG_0, @@ -143,7 +143,7 @@ static const struct dpu_lm_cfg sm8550_lm[] =3D { }, { .name =3D "lm_1", .id =3D LM_1, .base =3D 0x45000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_0, .pingpong =3D PINGPONG_1, @@ -151,7 +151,7 @@ static const struct dpu_lm_cfg sm8550_lm[] =3D { }, { .name =3D "lm_2", .id =3D LM_2, .base =3D 0x46000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_3, .pingpong =3D PINGPONG_2, @@ -159,7 +159,7 @@ static const struct dpu_lm_cfg sm8550_lm[] =3D { }, { .name =3D "lm_3", .id =3D LM_3, .base =3D 0x47000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_2, .pingpong =3D PINGPONG_3, @@ -167,14 +167,14 @@ static const struct dpu_lm_cfg sm8550_lm[] =3D { }, { .name =3D "lm_4", .id =3D LM_4, .base =3D 0x48000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_5, .pingpong =3D PINGPONG_4, }, { .name =3D "lm_5", .id =3D LM_5, .base =3D 0x49000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_4, .pingpong =3D PINGPONG_5, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index 6cd7ddeb2b1fceed4cebc1f86793831b1cb75945..f2a09026abf324a3c66c17264c8= a5d8f2d75a580 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -134,7 +134,7 @@ static const struct dpu_lm_cfg x1e80100_lm[] =3D { { .name =3D "lm_0", .id =3D LM_0, .base =3D 0x44000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_1, .pingpong =3D PINGPONG_0, @@ -142,7 +142,7 @@ static const struct dpu_lm_cfg x1e80100_lm[] =3D { }, { .name =3D "lm_1", .id =3D LM_1, .base =3D 0x45000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_0, .pingpong =3D PINGPONG_1, @@ -150,7 +150,7 @@ static const struct dpu_lm_cfg x1e80100_lm[] =3D { }, { .name =3D "lm_2", .id =3D LM_2, .base =3D 0x46000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_3, .pingpong =3D PINGPONG_2, @@ -158,7 +158,7 @@ static const struct dpu_lm_cfg x1e80100_lm[] =3D { }, { .name =3D "lm_3", .id =3D LM_3, .base =3D 0x47000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_2, .pingpong =3D PINGPONG_3, @@ -166,14 +166,14 @@ static const struct dpu_lm_cfg x1e80100_lm[] =3D { }, { .name =3D "lm_4", .id =3D LM_4, .base =3D 0x48000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_5, .pingpong =3D PINGPONG_4, }, { .name =3D "lm_5", .id =3D LM_5, .base =3D 0x49000, .len =3D 0x320, - .features =3D MIXER_SDM845_MASK, + .sourcesplit =3D 1, .sblk =3D &sdm845_lm_sblk, .lm_pair =3D LM_4, .pingpong =3D PINGPONG_5, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 8496a44e2f04edeec884e1bac029c513022bf79a..2db27c55787791309962acf796d= 5c49aaf018fc1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -86,12 +86,6 @@ (BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_CDP) |\ BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_SCALER_RGB)) =20 -#define MIXER_MSM8998_MASK \ - (BIT(DPU_MIXER_SOURCESPLIT)) - -#define MIXER_SDM845_MASK \ - (BIT(DPU_MIXER_SOURCESPLIT)) - #define WB_SDM845_MASK (BIT(DPU_WB_LINE_MODE) | \ BIT(DPU_WB_UBWC) | \ BIT(DPU_WB_YUV_CONFIG) | \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index beffb92adf5d8a150e049811bf2caa212dace1a6..51b330f37c901b99c7db640a0b7= 7149c7ac8cdd7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -64,16 +64,6 @@ enum { DPU_SSPP_MAX }; =20 -/* - * MIXER sub-blocks/features - * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configurat= ion - * @DPU_MIXER_MAX maximum value - */ -enum { - DPU_MIXER_SOURCESPLIT =3D 0x1, - DPU_MIXER_MAX, -}; - /** * DSPP sub-blocks * @DPU_DSPP_PCC Panel color correction block @@ -423,6 +413,7 @@ struct dpu_sspp_cfg { * @sblk: LM Sub-blocks information * @pingpong: ID of connected PingPong, PINGPONG_NONE if unsuppor= ted * @lm_pair: ID of LM that can be controlled by same CTL + * @sourcesplit Layer mixer supports source-split configuration */ struct dpu_lm_cfg { DPU_HW_BLK_INFO; @@ -430,6 +421,7 @@ struct dpu_lm_cfg { u32 pingpong; u32 dspp; unsigned long lm_pair; + unsigned long sourcesplit : 1; }; =20 /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.c index 7f6c548b626dbc5bcc3ddb27f185f336354dcb37..7b32bacb5b9cd61727a2d596c65= ac1b14eda942c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -505,8 +505,7 @@ static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_c= tl *ctx, if (stages < 0) return; =20 - if (test_bit(DPU_MIXER_SOURCESPLIT, - &ctx->mixer_hw_caps->features)) + if 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Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 12 ++---------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c | 2 +- 10 files changed, 20 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index 2007aedc0526854d3d8c4eface5b507dc5c62c58..b8cac2dbec3c963b1a15337c648= 10a23ac6afc9e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -289,22 +289,22 @@ static const struct dpu_dsc_cfg sm8650_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_0_1", .id =3D DSC_1, .base =3D 0x80000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x6, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_2_0", .id =3D DSC_4, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 2c59f0b77a75880df18900fa406f1ea7006927a1..26266d36520e7499feb26da0f33= 51405bbd2f87a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -274,12 +274,12 @@ static const struct dpu_dsc_cfg sm8350_dsc[] =3D { }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index cbc7e9081288fb8125438ad1cc0016042bf70661..3881dc839db71dd798863067a84= 69cdf3045719c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -150,7 +150,7 @@ static const struct dpu_dsc_cfg sc7280_dsc[] =3D { { .name =3D "dce_0_0", .id =3D DSC_0, .base =3D 0x80000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_0, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 0238eb019d98ad5599cc301e47bda43de762b24d..f9c572be7fea9660d03284d8150= 67a17ac4abe4a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -273,12 +273,12 @@ static const struct dpu_dsc_cfg sc8280xp_dsc[] =3D { }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_2_0", .id =3D DSC_4, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 3b2d99de20621a5c47a31212d7fb236e0b784d0a..08d5273554500a00a55adbe144b= 50fb4f8296ce7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -287,12 +287,12 @@ static const struct dpu_dsc_cfg sm8450_dsc[] =3D { }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index 14a1781c19bd8060d338ea52684f756258526996..d4eaf89821722bfccefe930e834= cbd83d52123e0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -286,12 +286,12 @@ static const struct dpu_dsc_cfg sa8775p_dsc[] =3D { }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_1, }, { .name =3D "dce_2_0", .id =3D DSC_4, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index f6893c7ea13bc0ac84b46d50a132e18e1c575a3d..83dce1aef9d991afb7f30f75724= a822854be3e78 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -283,12 +283,12 @@ static const struct dpu_dsc_cfg sm8550_dsc[] =3D { }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index f2a09026abf324a3c66c17264c8a5d8f2d75a580..2938ff15299ecc5002aa1bffd02= 292212fe51f03 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -283,12 +283,12 @@ static const struct dpu_dsc_cfg x1e80100_dsc[] =3D { }, { .name =3D "dce_1_0", .id =3D DSC_2, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_0, }, { .name =3D "dce_1_1", .id =3D DSC_3, .base =3D 0x81000, .len =3D 0x4, - .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .have_native_42x =3D 1, .sblk =3D &dsc_sblk_1, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 51b330f37c901b99c7db640a0b77149c7ac8cdd7..0f78958ac4476de414d07b727c0= 8feec1c2e9f44 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -128,16 +128,6 @@ enum { DPU_VBIF_MAX }; =20 -/** - * DSC sub-blocks/features - * @DPU_DSC_NATIVE_42x_EN Supports NATIVE_422_EN and NATIVE_420_EN enc= oding - * @DPU_DSC_MAX - */ -enum { - DPU_DSC_NATIVE_42x_EN =3D 0x1, - DPU_DSC_MAX -}; - /** * MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU * @name: string name for debug purposes @@ -474,10 +464,12 @@ struct dpu_merge_3d_cfg { * @len: length of hardware block * @features bit mask identifying sub-blocks/features * @sblk: sub-blocks information + * @have_native_42x: Supports NATIVE_422 and NATIVE_420 encoding */ struct dpu_dsc_cfg { DPU_HW_BLK_INFO; const struct dpu_dsc_sub_blks *sblk; + unsigned long have_native_42x : 1; }; =20 /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_dsc_1_2.c index b9c433567262a954b7f02233f6670ee6a8476846..42b4a5dbc2442ae0f2adab80a5a= 3df96b35e62b0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c @@ -62,7 +62,7 @@ static int _dsc_calc_output_buf_max_addr(struct dpu_hw_ds= c *hw_dsc, int num_soft { int max_addr =3D 2400 / num_softslice; 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Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 12 ++---------- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 9 +++------ 17 files changed, 44 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h index b8cac2dbec3c963b1a15337c64810a23ac6afc9e..f1adbf0db64716bba09bf88e59c= 516418c57214d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h @@ -26,17 +26,17 @@ static const struct dpu_mdp_cfg sm8650_mdp =3D { }, }; =20 -/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL = support */ +/* FIXME: get rid of .has_split_display in favour of proper ACTIVE_CTL sup= port */ static const struct dpu_ctl_cfg sm8650_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x1000, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x1000, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index 1f119f79545eb1f4c6d27fe9fcb2a22d038cc571..9a4040921db78e13c04199d0c53= 3be47c9d77f30 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -41,7 +41,7 @@ static const struct dpu_ctl_cfg msm8998_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x1000, .len =3D 0x94, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, @@ -50,7 +50,7 @@ static const struct dpu_ctl_cfg msm8998_ctl[] =3D { }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x1400, .len =3D 0x94, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h index c8008db5772498d3bb85596518a3a21395fc9491..04301d2ba34f3275deee2b0e891= 05ff4616a7c2a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h @@ -36,7 +36,7 @@ static const struct dpu_ctl_cfg sdm660_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x1000, .len =3D 0x94, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, @@ -45,7 +45,7 @@ static const struct dpu_ctl_cfg sdm660_ctl[] =3D { }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x1400, .len =3D 0x94, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h index 70d7751831b738d40ab7e736ddb442c4d44e982e..35d2feea79e8c8673fafd1be83d= 554efdf21b32a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h @@ -35,7 +35,7 @@ static const struct dpu_ctl_cfg sdm630_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x1000, .len =3D 0x94, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, @@ -44,7 +44,7 @@ static const struct dpu_ctl_cfg sdm630_ctl[] =3D { }, { .name =3D "ctl_2", .id =3D CTL_2, .base =3D 0x1400, .len =3D 0x94, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name =3D "ctl_3", .id =3D CTL_3, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 1218a3585cbc8664194692cdd2639af1c7888c39..2f3564c6672ae86203629194981= e911f7ebf8bef 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -39,12 +39,12 @@ static const struct dpu_ctl_cfg sdm845_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x1000, .len =3D 0xe4, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x1200, .len =3D 0xe4, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index 520f5cd122dd331ca1a1d9cc1ebd7654264f3e52..63ff6e9549b6289534cd41efc98= 91c5a1cb2672e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -36,17 +36,17 @@ static const struct dpu_mdp_cfg sm8150_mdp =3D { }, }; =20 -/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL = support */ +/* FIXME: get rid of .has_split_display in favour of proper ACTIVE_CTL sup= port */ static const struct dpu_ctl_cfg sm8150_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x1000, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x1200, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index c1827c80e7efef9c57757e0b53535d9fbba30c05..47c2757e47a0a18350f13c57fab= 401dd5439bf08 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -40,12 +40,12 @@ static const struct dpu_ctl_cfg sc8180x_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x1000, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x1200, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h index d4c7c59e1ba845e087bcbc3394fc972a9058943d..9a7b0de857db2d13b7a4415e345= 2c1ad4140df36 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h @@ -37,12 +37,12 @@ static const struct dpu_ctl_cfg sm7150_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x1000, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x1200, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 50eea89a885ecf0d4ff4f478e6d356d86285bb3e..cbf8e1f7314ee15b6f78917e2a3= 6006f6e9d9245 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -35,17 +35,17 @@ static const struct dpu_mdp_cfg sm8250_mdp =3D { }, }; =20 -/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL = support */ +/* FIXME: get rid of .has_split_display in favour of proper ACTIVE_CTL sup= port */ static const struct dpu_ctl_cfg sm8250_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x1000, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x1200, .len =3D 0x1e0, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 26266d36520e7499feb26da0f3351405bbd2f87a..774fe5e1c513e0cb8cb3ff4dad9= 5b03311350c61 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -35,17 +35,17 @@ static const struct dpu_mdp_cfg sm8350_mdp =3D { }, }; =20 -/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL = support */ +/* FIXME: get rid of .has_split_display in favour of proper ACTIVE_CTL sup= port */ static const struct dpu_ctl_cfg sm8350_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x1e8, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x1e8, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index f9c572be7fea9660d03284d815067a17ac4abe4a..443500970f669ea6f38dd11d4d0= c90fe92bdb455 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -34,17 +34,17 @@ static const struct dpu_mdp_cfg sc8280xp_mdp =3D { }, }; =20 -/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL = support */ +/* FIXME: get rid of .has_split_display in favour of proper ACTIVE_CTL sup= port */ static const struct dpu_ctl_cfg sc8280xp_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x204, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x204, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 08d5273554500a00a55adbe144b50fb4f8296ce7..82df68fd01dc64fcb95cbb0bd70= 991b428829479 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -35,17 +35,17 @@ static const struct dpu_mdp_cfg sm8450_mdp =3D { }, }; =20 -/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL = support */ +/* FIXME: get rid of .has_split_display in favour of proper ACTIVE_CTL sup= port */ static const struct dpu_ctl_cfg sm8450_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x204, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x204, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index d4eaf89821722bfccefe930e834cbd83d52123e0..f3fe68587dee21f059b68c1cecf= e3f68c2bf48a1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -34,17 +34,17 @@ static const struct dpu_mdp_cfg sa8775p_mdp =3D { }, }; =20 -/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL = support */ +/* FIXME: get rid of .has_split_display in favour of proper ACTIVE_CTL sup= port */ static const struct dpu_ctl_cfg sa8775p_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x204, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x204, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 83dce1aef9d991afb7f30f75724a822854be3e78..97c4e3b74c5bcefd0d9535b9356= bc2010841597b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -26,17 +26,17 @@ static const struct dpu_mdp_cfg sm8550_mdp =3D { }, }; =20 -/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL = support */ +/* FIXME: get rid of .has_split_display in favour of proper ACTIVE_CTL sup= port */ static const struct dpu_ctl_cfg sm8550_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x290, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x290, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index 2938ff15299ecc5002aa1bffd02292212fe51f03..18773f318131265aadc6cca9b17= a73ebf2f091b7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -25,17 +25,17 @@ static const struct dpu_mdp_cfg x1e80100_mdp =3D { }, }; =20 -/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL = support */ +/* FIXME: get rid of .has_split_display in favour of proper ACTIVE_CTL sup= port */ static const struct dpu_ctl_cfg x1e80100_ctl[] =3D { { .name =3D "ctl_0", .id =3D CTL_0, .base =3D 0x15000, .len =3D 0x290, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, { .name =3D "ctl_1", .id =3D CTL_1, .base =3D 0x16000, .len =3D 0x290, - .features =3D BIT(DPU_CTL_SPLIT_DISPLAY), + .has_split_display =3D 1, .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { .name =3D "ctl_2", .id =3D CTL_2, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 0f78958ac4476de414d07b727c08feec1c2e9f44..ffc54f77fe5c8883e926e0c6382= 5c9424904cf2d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -73,16 +73,6 @@ enum { DPU_DSPP_MAX }; =20 -/** - * CTL sub-blocks - * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display - * @DPU_CTL_MAX - */ -enum { - DPU_CTL_SPLIT_DISPLAY =3D 0x1, - DPU_CTL_MAX -}; - /** * WB sub-blocks and features * @DPU_WB_LINE_MODE Writeback module supports line/linear mode @@ -371,10 +361,12 @@ struct dpu_mdp_cfg { * @base: register base offset to mdss * @features bit mask identifying sub-blocks/features * @intr_start: interrupt index for CTL_START + * @has_split_display: CTL supports video mode split display */ struct dpu_ctl_cfg { DPU_HW_BLK_INFO; unsigned int intr_start; + unsigned long has_split_display : 1; }; =20 /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.c index f118c6caa1b9007eb03fa9b39efa87dfb46583ba..1698c5a4447c22c57c3ce9327b9= c81559a6fd921 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -451,8 +451,6 @@ static int _dpu_rm_reserve_ctls( =20 for (j =3D 0; j < ARRAY_SIZE(rm->ctl_blks); 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54e7cb3987csm3852e87.59.2025.04.23.14.11.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Apr 2025 14:11:35 -0700 (PDT) From: Dmitry Baryshkov Date: Thu, 24 Apr 2025 00:10:29 +0300 Subject: [PATCH v2 33/33] drm/msm/dpu: move features out of the DPU_HW_BLK_INFO Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250424-dpu-drop-features-v2-33-0a9a66a7b3a2@oss.qualcomm.com> References: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> In-Reply-To: <20250424-dpu-drop-features-v2-0-0a9a66a7b3a2@oss.qualcomm.com> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10025; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=8tb1+qRLI7JpcBUvNssngnuycT2/Ign7Y6I5ypwrc4k=; b=owGbwMvMwMXYbdNlx6SpcZXxtFoSQwZnuP4rUTHzovqnLryuz41W/Vt+IWLZKr0Ay3+cLBbTV ixq59XsZDRmYWDkYpAVU2TxKWiZGrMpOezDjqn1MINYmUCmMHBxCsBEBGo4GPrEVu+U+reho3Ve tZ/Rqyfu9omHFU1i1cxYtT7r3LgsHrgwws17lpzYJJul72u6ROQnrp139qXA7qPqp+IUlSq5pPi /Lit+EsL8X6H75mG/L99X1m+K1vq8zI1xzsHLrC4xz3gNV/k4uGR9DV22JN2l0Nf04638MxJRFT tMM7bl5511L3KKnPIqwP+o2sn3/7cWcfK9WO260uZ1/KY7h5mYA6q77fXutWT/5xSeyaL57HJS2 ovNXLwSxiYzL7W415tmtsqrC557vWy9T3xVT0tGnXZtsjBDSWO+kLRgb3Zi8hS+BKbnTWGn1op6 zbzkdPNWjkNPyq/IXPFViuuivHVkGOyWubE/qDJ6EgkA X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Proofpoint-GUID: VQyns-peou5-EpvtoWGV81xCHgbjiBc6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDIzMDE0NCBTYWx0ZWRfX8EsRRQt7/uu3 c9oLmcKBsCUwIToh+7TOEAxd0lkgR59UX4yxuKKQ5EssbJ6ahl3CxGJWCbtUH9xL+dEd+Me59HV 6/6MvvHhUOUmFTYjViiS8ErYOJIjIoEZxQGGbbACUTkLBucQRstLRxLlyPfBKuRWZw5TqA95mQd Zz36P1ZM9kagkJuBOsw79YiVG9hLA04+RPVHYZCkKlE75evmy9d+1vW2E3ir3YLteDkQFfbWC+V jfnzssDW4ORGRa8d73YnWvFt4XJ37aZ7tLZ+SwMZrMu4XncIOBJWIw1dw8ewyoDYk8Xr9zYIrL7 M4kWOptOdGzr7f7DgraNM/F001qPT96FTshJMKPCNLYCpHWqxv1mYEPh+VeS3Wn6FgbGP5QNHPe Kjh8n4DszAi8yF/EOsOJh1gLeOqMxRtbDNMkAL+RO3I6aisQkgnJ0vYWOqqoPzjACxurK0uH X-Authority-Analysis: v=2.4 cv=Tu/mhCXh c=1 sm=1 tr=0 ts=6809578b cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=cFriiCX7-o5b7acnli0A:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: VQyns-peou5-EpvtoWGV81xCHgbjiBc6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.680,FMLib:17.12.80.40 definitions=2025-04-23_11,2025-04-22_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 phishscore=0 mlxlogscore=999 bulkscore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504230144 From: Dmitry Baryshkov Only SSPP, WB and VBIF still have feature bits remaining, all other hardware blocks don't have feature bits anymore. Remove the 'features' from the DPU_HW_BLK_INFO so that it doesn't get included into hw info structures by default and only include it when necessary. Signed-off-by: Dmitry Baryshkov Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 17 ++++----------= --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c | 5 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c | 5 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 4 ++-- 6 files changed, 10 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h index a065f102ce592311376f1186add7a47dca7fd84f..26883f6b66b3e506d14eeb1c0bd= 64f556d19fef8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h @@ -20,7 +20,6 @@ static const struct dpu_caps sm6150_dpu_caps =3D { static const struct dpu_mdp_cfg sm6150_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x45c, - .features =3D 0, .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_DMA0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 8 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h index 8c909c41b48a18fdc54753c68bc2ad19001cd3b4..1884371736bfcf78a99661baeda= dc0450bb4376e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h @@ -22,7 +22,6 @@ static const struct dpu_caps sm6125_dpu_caps =3D { static const struct dpu_mdp_cfg sm6125_mdp =3D { .name =3D "top_0", .base =3D 0x0, .len =3D 0x45c, - .features =3D 0, .clk_ctrls =3D { [DPU_CLK_CTRL_VIG0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 0 }, [DPU_CLK_CTRL_DMA0] =3D { .reg_off =3D 0x2ac, .bit_off =3D 8 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index ffc54f77fe5c8883e926e0c63825c9424904cf2d..f5ce35cd966459f0edf2dbdd2db= c2693779fac73 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -124,14 +124,12 @@ enum { * @id: enum identifying this block * @base: register base offset to mdss * @len: length of hardware block - * @features bit mask identifying sub-blocks/features */ #define DPU_HW_BLK_INFO \ char name[DPU_HW_BLK_NAME_LEN]; \ u32 id; \ u32 base; \ - u32 len; \ - unsigned long features + u32 len =20 /** * struct dpu_scaler_blk: Scaler information @@ -348,7 +346,6 @@ struct dpu_clk_ctrl_reg { /* struct dpu_mdp_cfg : MDP TOP-BLK instance info * @id: index identifying this block * @base: register base offset to mdss - * @features bit mask identifying sub-blocks/features * @clk_ctrls clock control register definition */ struct dpu_mdp_cfg { @@ -359,7 +356,6 @@ struct dpu_mdp_cfg { /* struct dpu_ctl_cfg : MDP CTL instance info * @id: index identifying this block * @base: register base offset to mdss - * @features bit mask identifying sub-blocks/features * @intr_start: interrupt index for CTL_START * @has_split_display: CTL supports video mode split display */ @@ -381,6 +377,7 @@ struct dpu_ctl_cfg { */ struct dpu_sspp_cfg { DPU_HW_BLK_INFO; + unsigned long features; const struct dpu_sspp_sub_blks *sblk; u32 xin_id; enum dpu_clk_ctrl_type clk_ctrl; @@ -391,7 +388,6 @@ struct dpu_sspp_cfg { * struct dpu_lm_cfg - information of layer mixer blocks * @id: index identifying this block * @base register offset of this block - * @features bit mask identifying sub-blocks/features * @sblk: LM Sub-blocks information * @pingpong: ID of connected PingPong, PINGPONG_NONE if unsuppor= ted * @lm_pair: ID of LM that can be controlled by same CTL @@ -410,7 +406,6 @@ struct dpu_lm_cfg { * struct dpu_dspp_cfg - information of DSPP blocks * @id enum identifying this block * @base register offset of this block - * @features bit mask identifying sub-blocks/features * supported by this block * @sblk sub-blocks information */ @@ -423,7 +418,6 @@ struct dpu_dspp_cfg { * struct dpu_pingpong_cfg - information of PING-PONG blocks * @id enum identifying this block * @base register offset of this block - * @features bit mask identifying sub-blocks/features * @intr_done: index for PINGPONG done interrupt * @intr_rdptr: index for PINGPONG readpointer done interrupt * @sblk sub-blocks information @@ -440,8 +434,6 @@ struct dpu_pingpong_cfg { * struct dpu_merge_3d_cfg - information of DSPP blocks * @id enum identifying this block * @base register offset of this block - * @features bit mask identifying sub-blocks/features - * supported by this block * @sblk sub-blocks information */ struct dpu_merge_3d_cfg { @@ -454,7 +446,6 @@ struct dpu_merge_3d_cfg { * @id enum identifying this block * @base register offset of this block * @len: length of hardware block - * @features bit mask identifying sub-blocks/features * @sblk: sub-blocks information * @have_native_42x: Supports NATIVE_422 and NATIVE_420 encoding */ @@ -468,7 +459,6 @@ struct dpu_dsc_cfg { * struct dpu_intf_cfg - information of timing engine blocks * @id enum identifying this block * @base register offset of this block - * @features bit mask identifying sub-blocks/features * @type: Interface type(DSI, DP, HDMI) * @controller_id: Controller Instance ID in case of multiple of intf = type * @prog_fetch_lines_worst_case Worst case latency num lines needed to pre= fetch @@ -499,6 +489,7 @@ struct dpu_intf_cfg { */ struct dpu_wb_cfg { DPU_HW_BLK_INFO; + unsigned long features; u8 vbif_idx; u32 maxlinewidth; u32 xin_id; @@ -567,6 +558,7 @@ struct dpu_vbif_qos_tbl { */ struct dpu_vbif_cfg { DPU_HW_BLK_INFO; + unsigned long features; u32 default_ot_rd_limit; u32 default_ot_wr_limit; u32 xin_halt_timeout; @@ -584,7 +576,6 @@ struct dpu_vbif_cfg { * @name string name for debug purposes * @id enum identifying this block * @base register offset of this block - * @features bit mask identifying sub-blocks/features */ struct dpu_cdm_cfg { DPU_HW_BLK_INFO; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_dsc_1_2.c index 42b4a5dbc2442ae0f2adab80a5a3df96b35e62b0..df6e43672422f1d796e38c32256= 582900f58523e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c @@ -360,8 +360,7 @@ static void dpu_hw_dsc_bind_pingpong_blk_1_2(struct dpu= _hw_dsc *hw_dsc, DPU_REG_WRITE(hw, sblk->ctl.base + DSC_CTL, mux_cfg); } =20 -static void _setup_dcs_ops_1_2(struct dpu_hw_dsc_ops *ops, - const unsigned long features) +static void _setup_dcs_ops_1_2(struct dpu_hw_dsc_ops *ops) { ops->dsc_disable =3D dpu_hw_dsc_disable_1_2; ops->dsc_config =3D dpu_hw_dsc_config_1_2; @@ -391,7 +390,7 @@ struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(struct drm_devic= e *dev, =20 c->idx =3D cfg->id; c->caps =3D cfg; - _setup_dcs_ops_1_2(&c->ops, c->caps->features); + _setup_dcs_ops_1_2(&c->ops); =20 return c; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_merge3d.c index 0b3325f9c8705999e1003e5c88872562e880229b..83b1dbecddd2b30402f47155fa2= f9a148ead02c1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c @@ -33,8 +33,7 @@ static void dpu_hw_merge_3d_setup_3d_mode(struct dpu_hw_m= erge_3d *merge_3d, } } =20 -static void _setup_merge_3d_ops(struct dpu_hw_merge_3d *c, - unsigned long features) +static void _setup_merge_3d_ops(struct dpu_hw_merge_3d *c) { c->ops.setup_3d_mode =3D dpu_hw_merge_3d_setup_3d_mode; }; @@ -62,7 +61,7 @@ struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(struct drm_d= evice *dev, =20 c->idx =3D cfg->id; c->caps =3D cfg; - _setup_merge_3d_ops(c, c->caps->features); + _setup_merge_3d_ops(c); =20 return c; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_top.c index 5c811f0142d5e2a012d7e9b3a918818f22ec11cf..96dc10589bee6cf144eabaecf9f= 8ec5777431ac3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c @@ -264,7 +264,7 @@ static void dpu_hw_dp_phy_intf_sel(struct dpu_hw_mdp *m= dp, } =20 static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops, - unsigned long cap, const struct dpu_mdss_version *mdss_rev) + const struct dpu_mdss_version *mdss_rev) { ops->setup_split_pipe =3D dpu_hw_setup_split_pipe; ops->setup_clk_force_ctrl =3D dpu_hw_setup_clk_force_ctrl; @@ -313,7 +313,7 @@ struct dpu_hw_mdp *dpu_hw_mdptop_init(struct drm_device= *dev, * Assign ops */ mdp->caps =3D cfg; - _setup_mdp_ops(&mdp->ops, mdp->caps->features, mdss_rev); + _setup_mdp_ops(&mdp->ops, mdss_rev); =20 return mdp; } --=20 2.39.5