From nobody Sun Apr 26 21:38:00 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) by smtp.subspace.kernel.org (Postfix) with ESMTP id F2AD81A08A4; Wed, 23 Apr 2025 15:33:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745422432; cv=none; b=fH9v9InmG+rwVHTw0X4oTn8noUqydtHVOfsFLf5wfQdM6AVeRoE1cz9zmvDkd7QbW6S6dVGQxNhc+6DBdTmxP/gk0ZggkUO3FctBrxEaFncXc+Odu2u081dI4QO80yxl5s4OYERnTjfGF0Y1ZQLi7Wuoa3PC2t2COuQ0Cmj6c80= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745422432; c=relaxed/simple; bh=HKLmHV0ZtG/a4Tkd0yHHJS/176AZM+g1/tCMQTabZzk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=P3ZRLhlUo+Nnc6OwYmYzW5OctZk4oapgkshkkjmZeBHwm7SHaMgeZz3ZxfZuBsVYrY7LsctJWsoGb2MZe6hhEXpcwB5luwgfFUHjfT9NPx9GOZtt4a3WOOYKiX2osfwONU9CFeh/19dLJ+2TY6paGPsnYopZm0cyigruCQsPTZs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=ncaZrwL5; arc=none smtp.client-ip=117.135.210.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="ncaZrwL5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=EY9gG G+ynYNdnB1j3/6lY26zStHwpPSt9Msjmy1Whvk=; b=ncaZrwL59hzIp0+ge+E0O 21ImkguoI3jiNwf6M03zCOVeA1Qr2/j03j49kF53eQc5Y95yKEN0tyND4Nso5iwW O6WaIetY+zY1U4VcCxKcPmvaNkSb+xWD7BzvwQqpR2bEnrD4lOTfidVZ2giP6dSW uInkZC3qjQJfWEHQVvc7ko= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g0-2 (Coremail) with SMTP id _____wCnosAACAlogeYfCA--.9428S3; Wed, 23 Apr 2025 23:32:19 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, heiko@sntech.de Cc: manivannan.sadhasivam@linaro.org, robh@kernel.org, jingoohan1@gmail.com, shawn.lin@rock-chips.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Hans Zhang <18255117159@163.com>, Niklas Cassel Subject: [PATCH v3 1/3] PCI: dw-rockchip: Remove unused PCIE_CLIENT_GENERAL_DEBUG Date: Wed, 23 Apr 2025 23:32:12 +0800 Message-Id: <20250423153214.16405-2-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250423153214.16405-1-18255117159@163.com> References: <20250423153214.16405-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wCnosAACAlogeYfCA--.9428S3 X-Coremail-Antispam: 1Uf129KBjvdXoWruw1kCw48Gw15WrykXrW8WFg_yoWkXrXE9r yUuF4xXryDKrWSk392yw4xZFn0yas7ur1xGFZYgFsIva47Kr4rXry8ZrWrX3WDGr43JFyf t34vyF4ruayxtjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7sR_66wJUUUUU== X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWxg4o2gJAM7G6gAAsb Content-Type: text/plain; charset="utf-8" The PCIE_CLIENT_GENERAL_DEBUG register offset is defined but never used in the driver. Its presence adds noise to the register map and may mislead future developers. Remove this redundant definition to keep the register list minimal and aligned with actual hardware usage. Signed-off-by: Hans Zhang <18255117159@163.com> Reviewed-by: Niklas Cassel Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index 0e0c09bafd63..fd5827bbfae3 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -54,7 +54,6 @@ #define PCIE_CLIENT_GENERAL_CONTROL 0x0 #define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 #define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c -#define PCIE_CLIENT_GENERAL_DEBUG 0x104 #define PCIE_CLIENT_HOT_RESET_CTRL 0x180 #define PCIE_CLIENT_LTSSM_STATUS 0x300 #define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) --=20 2.25.1 From nobody Sun Apr 26 21:38:00 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2A81B2BD5B0; Wed, 23 Apr 2025 15:33:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745422385; cv=none; b=QkFAgFK8O8Cb0GrspnO5eqKPdUTtdwx09wdESuNRrCyW9XhaYJ4Rrg5gZcdfOE0/taY+1RZWWqqBOyzr0XDn9r3akb0y/ABOcyRi1L6Chj5VVIZAsh8ZjRln7PybxoFzjJd/DfBT5PiNna7LW+Pffek8Xv3V8WcH00gzmHl3f6Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745422385; c=relaxed/simple; bh=svfuyLBCEv8k1uCrOACXnEv5v6T38vEtpARUGCx9ehU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=W/CEuEVhIHESqM1B34XS8FrloTMxWDvoxJ6e4tD48IMHxzkbslKJ+HFkJR0sdw8oYv4FKFiP4Hxaj4ZYUgLLI0V9R56xeE1CkGPn0XNxOma1QKXAfI2OTA67DnzCS9uQ8Wvpbg1syH54MKNYxLcMAKkGNuVFjFhoSe3BZbazzt4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=hVNDd8sK; arc=none smtp.client-ip=117.135.210.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="hVNDd8sK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=A0sm3 yCG2xo4YaewR2G18cCyYOO9P0b4G0YtDHiuAyI=; b=hVNDd8sKMYhY//m9OFMlC Q+APhnrx2ekOH6gOkXFBZVPFc/a58sBgixTqDFcP13mEnaewT1tO6WRyVd/HOE+R Tv94vEqlnvSvLGJrO+JrMEwTIAu8i9iybBzGoPQX9kX4qmv7OfKMZhqCom0jxxGP 5Qo5gYoGPTBZKeTA4kZeaI= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g0-2 (Coremail) with SMTP id _____wCnosAACAlogeYfCA--.9428S4; Wed, 23 Apr 2025 23:32:20 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, heiko@sntech.de Cc: manivannan.sadhasivam@linaro.org, robh@kernel.org, jingoohan1@gmail.com, shawn.lin@rock-chips.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v3 2/3] PCI: dw-rockchip: Reorganize register and bitfield definitions Date: Wed, 23 Apr 2025 23:32:13 +0800 Message-Id: <20250423153214.16405-3-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250423153214.16405-1-18255117159@163.com> References: <20250423153214.16405-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wCnosAACAlogeYfCA--.9428S4 X-Coremail-Antispam: 1Uf129KBjvJXoW3Ar48Cr4Duw1kAFy5Kr13twb_yoW7tF47p3 yDAFyakr45ta17u3s5CFZ8ZFWxtrnxKFWUGrsag3yUu3Z5A3y8Kw1UWF95Wry7Gr4kuFy3 uwn8C342gFyakrUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zEZ2-5UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiOg44o2gJB+UC-QABsS Content-Type: text/plain; charset="utf-8" Register definitions were scattered with ambiguous names (e.g., PCIE_RDLH_LINK_UP_CHGED in PCIE_CLIENT_INTR_STATUS_MISC) and lacked hierarchical grouping. Magic values for bit operations reduced code clarity. Group registers and their associated bitfields logically. This improves maintainability and aligns the code with hardware documentation. Signed-off-by: Hans Zhang <18255117159@163.com> Reviewed-by: Manivannan Sadhasivam Reviewed-by: Niklas Cassel --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 71 ++++++++++++------- 1 file changed, 45 insertions(+), 26 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index fd5827bbfae3..96ca394da42c 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -34,30 +34,49 @@ =20 #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev) =20 -#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40) -#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0) -#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc) -#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8) -#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x04 -#define PCIE_CLIENT_INTR_STATUS_MISC 0x10 -#define PCIE_CLIENT_INTR_MASK_MISC 0x24 -#define PCIE_CLIENT_POWER 0x2c -#define PCIE_CLIENT_MSG_GEN 0x34 -#define PME_READY_ENTER_L23 BIT(3) -#define PME_TURN_OFF (BIT(4) | BIT(20)) -#define PME_TO_ACK (BIT(9) | BIT(25)) -#define PCIE_SMLH_LINKUP BIT(16) -#define PCIE_RDLH_LINKUP BIT(17) -#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) -#define PCIE_RDLH_LINK_UP_CHGED BIT(1) -#define PCIE_LINK_REQ_RST_NOT_INT BIT(2) -#define PCIE_CLIENT_GENERAL_CONTROL 0x0 +/* General Control Register */ +#define PCIE_CLIENT_GENERAL_CON 0x0 +#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40) +#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0) +#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc) +#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8) + +/* Interrupt Status Register Related to Message Reception */ +#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x4 + +/* Interrupt Status Register Related to Legacy Interrupt */ #define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 + +/* Interrupt Status Register Related to Miscellaneous Operation */ +#define PCIE_CLIENT_INTR_STATUS_MISC 0x10 +#define PCIE_RDLH_LINK_UP_CHGED BIT(1) +#define PCIE_LINK_REQ_RST_NOT_INT BIT(2) + +/* Interrupt Mask Register Related to Legacy Interrupt */ #define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c + +/* Interrupt Mask Register Related to Miscellaneous Operation */ +#define PCIE_CLIENT_INTR_MASK_MISC 0x24 + +/* Power Management Control Register */ +#define PCIE_CLIENT_POWER_CON 0x2c +#define PME_READY_ENTER_L23 BIT(3) + +/* Message Generation Control Register */ +#define PCIE_CLIENT_MSG_GEN_CON 0x34 +#define PME_TURN_OFF HIWORD_UPDATE_BIT(BIT(4)) +#define PME_TO_ACK HIWORD_UPDATE_BIT(BIT(9)) + +/* Hot Reset Control Register */ #define PCIE_CLIENT_HOT_RESET_CTRL 0x180 +#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) + +/* LTSSM Status Register */ #define PCIE_CLIENT_LTSSM_STATUS 0x300 -#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) -#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) +#define PCIE_SMLH_LINKUP BIT(16) +#define PCIE_RDLH_LINKUP BIT(17) +#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) +#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) =20 struct rockchip_pcie { struct dw_pcie pci; @@ -176,13 +195,13 @@ static u32 rockchip_pcie_get_pure_ltssm(struct dw_pci= e *pci) static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip) { rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM, - PCIE_CLIENT_GENERAL_CONTROL); + PCIE_CLIENT_GENERAL_CON); } =20 static void rockchip_pcie_disable_ltssm(struct rockchip_pcie *rockchip) { rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DISABLE_LTSSM, - PCIE_CLIENT_GENERAL_CONTROL); + PCIE_CLIENT_GENERAL_CON); } =20 static int rockchip_pcie_link_up(struct dw_pcie *pci) @@ -274,8 +293,8 @@ static void rockchip_pcie_pme_turn_off(struct dw_pcie_r= p *pp) u32 status; =20 /* 1. Broadcast PME_Turn_Off Message, bit 4 self-clear once done */ - rockchip_pcie_writel_apb(rockchip, PME_TURN_OFF, PCIE_CLIENT_MSG_GEN); - ret =3D readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_MSG_GEN, + rockchip_pcie_writel_apb(rockchip, PME_TURN_OFF, PCIE_CLIENT_MSG_GEN_CON); + ret =3D readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_MSG_GEN_CON, status, !(status & BIT(4)), PCIE_PME_TO_L2_TIMEOUT_US / 10, PCIE_PME_TO_L2_TIMEOUT_US); if (ret) { @@ -294,7 +313,7 @@ static void rockchip_pcie_pme_turn_off(struct dw_pcie_r= p *pp) =20 /* 3. Clear PME_TO_Ack and Wait for ready to enter L23 message */ rockchip_pcie_writel_apb(rockchip, PME_TO_ACK, PCIE_CLIENT_INTR_STATUS_MS= G_RX); - ret =3D readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_POWER, + ret =3D readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_POWER_CON, status, status & PME_READY_ENTER_L23, PCIE_PME_TO_L2_TIMEOUT_US / 10, PCIE_PME_TO_L2_TIMEOUT_US); @@ -552,7 +571,7 @@ static void rockchip_pcie_ltssm_enable_control_mode(str= uct rockchip_pcie *rockch val =3D HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); =20 - rockchip_pcie_writel_apb(rockchip, mode, PCIE_CLIENT_GENERAL_CONTROL); + rockchip_pcie_writel_apb(rockchip, mode, PCIE_CLIENT_GENERAL_CON); } =20 static void rockchip_pcie_unmask_dll_indicator(struct rockchip_pcie *rockc= hip) --=20 2.25.1 From nobody Sun Apr 26 21:38:00 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E65F528B500; Wed, 23 Apr 2025 15:32:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745422378; cv=none; b=WFRpPK5Gvev/XQtJSpYoyhmswM3okHpjf6BmEQsUNNH6mnmfMaL5xhup8X7Kj67zrNymWSFrkHCZh1MpnHM8j0CZq095lfjkxNEz1AcU6RgC0K4emRIgpBLgjCWRYUivTRj2HF25LdqedbIn6/K6/wuT8d7v0j6ZhQ2l8vGbJHw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745422378; c=relaxed/simple; bh=3VAiVAHCp1vHdSdVTqT36/jt7ereGJkrgxXxnPlhCZs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fesTw7cbaiz3EfSjQ7eN4LGdFJuVfjaC5FQVt9rdulRgu1isGN7qNl4NdHJDba+rjwgjzJtvee9YEXm7Ee8y1obc1u12y9hD6JBl54Be54OKWAbMgeZQmCC7TvSPxlVbQQDjtXASOuEs2NjWjJDZtbYAky9Cxlx1CAkArhyZtRk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=oRzss+Wz; arc=none smtp.client-ip=220.197.31.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="oRzss+Wz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=07Izf NBu1xhQHrsnGgppuuGY1X6HZdMLmQTtLGRKKp0=; b=oRzss+Wz1k5lbli1WBxum yJyHpSixOdQjZO41gx7IWhskzjCEOn333pQQl79wsu990Z1O5emy8hVeYAsm5Wb1 K5KPIuEQ5fWJLE5+PIkYA5+m9hbmhRiDH6fH0jT3uZkNx//JFKv2/vKrSdznbJ1+ Q5uZmrgCkgrRREo1YlSBxg= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g0-2 (Coremail) with SMTP id _____wCnosAACAlogeYfCA--.9428S5; Wed, 23 Apr 2025 23:32:21 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, heiko@sntech.de Cc: manivannan.sadhasivam@linaro.org, robh@kernel.org, jingoohan1@gmail.com, shawn.lin@rock-chips.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Hans Zhang <18255117159@163.com>, Niklas Cassel Subject: [PATCH v3 3/3] PCI: dw-rockchip: Unify link status checks with FIELD_GET Date: Wed, 23 Apr 2025 23:32:14 +0800 Message-Id: <20250423153214.16405-4-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250423153214.16405-1-18255117159@163.com> References: <20250423153214.16405-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wCnosAACAlogeYfCA--.9428S5 X-Coremail-Antispam: 1Uf129KBjvJXoWxCF15Jw4kKFykCw1UKrWxZwb_yoW5uw4Dpa 98Aa4vkr48Gw4j9F1kCFZ8ZFW5tFnxuayUCrn7K3WxW3ZIyw1UG3WUWr9xtr1xJr4rCFy3 Cw48ta4xJr43ZwUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zRBOJxUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbBDxY4o2gJB2IPvAAAs1 Content-Type: text/plain; charset="utf-8" Link-up detection manually checked PCIE_LINKUP bits across RC/EP modes, leading to code duplication. Centralize the logic using FIELD_GET. This removes redundancy and abstracts hardware-specific bit masking, ensuring consistent link state handling. Signed-off-by: Hans Zhang <18255117159@163.com> Reviewed-by: Niklas Cassel Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 21 +++++++------------ 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index 96ca394da42c..f2f8d8ada7a5 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -8,6 +8,7 @@ * Author: Simon Xue */ =20 +#include #include #include #include @@ -73,9 +74,8 @@ =20 /* LTSSM Status Register */ #define PCIE_CLIENT_LTSSM_STATUS 0x300 -#define PCIE_SMLH_LINKUP BIT(16) -#define PCIE_RDLH_LINKUP BIT(17) -#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) +#define PCIE_LINKUP 0x3 +#define PCIE_LINKUP_MASK GENMASK(17, 16) #define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) =20 struct rockchip_pcie { @@ -209,10 +209,7 @@ static int rockchip_pcie_link_up(struct dw_pcie *pci) struct rockchip_pcie *rockchip =3D to_rockchip_pcie(pci); u32 val =3D rockchip_pcie_get_ltssm(rockchip); =20 - if ((val & PCIE_LINKUP) =3D=3D PCIE_LINKUP) - return 1; - - return 0; + return FIELD_GET(PCIE_LINKUP_MASK, val) =3D=3D PCIE_LINKUP; } =20 static void rockchip_pcie_enable_l0s(struct dw_pcie *pci) @@ -512,7 +509,7 @@ static irqreturn_t rockchip_pcie_rc_sys_irq_thread(int = irq, void *arg) struct dw_pcie *pci =3D &rockchip->pci; struct dw_pcie_rp *pp =3D &pci->pp; struct device *dev =3D pci->dev; - u32 reg, val; + u32 reg; =20 reg =3D rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC); rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC); @@ -521,8 +518,7 @@ static irqreturn_t rockchip_pcie_rc_sys_irq_thread(int = irq, void *arg) dev_dbg(dev, "LTSSM_STATUS: %#x\n", rockchip_pcie_get_ltssm(rockchip)); =20 if (reg & PCIE_RDLH_LINK_UP_CHGED) { - val =3D rockchip_pcie_get_ltssm(rockchip); - if ((val & PCIE_LINKUP) =3D=3D PCIE_LINKUP) { + if (rockchip_pcie_link_up(pci)) { dev_dbg(dev, "Received Link up event. Starting enumeration!\n"); /* Rescan the bus to enumerate endpoint devices */ pci_lock_rescan_remove(); @@ -539,7 +535,7 @@ static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int = irq, void *arg) struct rockchip_pcie *rockchip =3D arg; struct dw_pcie *pci =3D &rockchip->pci; struct device *dev =3D pci->dev; - u32 reg, val; + u32 reg; =20 reg =3D rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC); rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC); @@ -553,8 +549,7 @@ static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int = irq, void *arg) } =20 if (reg & PCIE_RDLH_LINK_UP_CHGED) { - val =3D rockchip_pcie_get_ltssm(rockchip); - if ((val & PCIE_LINKUP) =3D=3D PCIE_LINKUP) { + if (rockchip_pcie_link_up(pci)) { dev_dbg(dev, "link up\n"); dw_pcie_ep_linkup(&pci->ep); } --=20 2.25.1