From nobody Tue Feb 10 10:08:02 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3BEC826D4C6; Wed, 23 Apr 2025 10:55:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745405711; cv=none; b=c9uJ+L1LMr4TlTGcGddIIaVowpjChQLryKlusnNP8Q2i83tvlj+J+bNmoXbsMHbNtjkRiMHtVD15s9I5BQaazqblbtuQ+9pomUVlg9piW9OOjGcoRogSkNU6KKrL/O6YZ/7RK3jmBUJ77O9TWn+gdR75SF10TFGgTI9d3f+9hK8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745405711; c=relaxed/simple; bh=wvUZeNvbPTQtNmJGim0FkGS4BcohX3rf0yyLJJKnivc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Nr1VAGj0yFc+ShGgUmnO8AgjXu22AdUwjkFqq5yXEW5ajMg2OrEEXM6O7JvYjJJUdm/KkyJxcTFTsIJjZqTTMcg6heuEtnicD/GVd6cwgqxq76+hQN7SznuKJTNvraFrkwoTwM8Fkvnx9/knFiVxR/hWZiTqc2StWYnnhdSKN6g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=GpmujaI8; arc=none smtp.client-ip=220.197.31.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="GpmujaI8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=BwcYZ 3QAYUzjwMBUPfQj13lIgXFp+SqbT5MeM2baqWQ=; b=GpmujaI8FCZcKvs82Yh3z zYps0LtQ7AUYKfvsrt4o+w9MeEgsfcFMpON4kByy8qL/8vOB0Ha4cu5bQIMBVX9C snluvgaim8xQ4FfgXhZNtyfWlaIEkNRjT1BUiC7BYQWFC6xXlsV+3TKIWvYbb14F eFT81BmbPVGms5iUa1+OGc= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-2 (Coremail) with SMTP id _____wAnRTjYxghozJctBw--.58909S5; Wed, 23 Apr 2025 18:54:22 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, heiko@sntech.de Cc: manivannan.sadhasivam@linaro.org, robh@kernel.org, jingoohan1@gmail.com, shawn.lin@rock-chips.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Hans Zhang <18255117159@163.com> Subject: [PATCH v2 3/3] PCI: dw-rockchip: Unify link status checks with FIELD_GET Date: Wed, 23 Apr 2025 18:54:15 +0800 Message-Id: <20250423105415.305556-4-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250423105415.305556-1-18255117159@163.com> References: <20250423105415.305556-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wAnRTjYxghozJctBw--.58909S5 X-Coremail-Antispam: 1Uf129KBjvJXoWxCF15Gr13Cw17GFW7Zw18Zrb_yoW5uF4xpa 98Aa4vkr48Gw4j9F1kCFZ5ZFW5tFnI9ayUCrn7K3WxW3ZIyw1UG3WUWr9Iqr4xJr4rCFy3 Cw4rta4xJr43ZwUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07UoBTwUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbBDwI4o2gIwTqyAgAAs9 Content-Type: text/plain; charset="utf-8" Link-up detection manually checked PCIE_LINKUP bits across RC/EP modes, leading to code duplication. Centralize the logic using FIELD_GET. This removes redundancy and abstracts hardware-specific bit masking, ensuring consistent link state handling. Signed-off-by: Hans Zhang <18255117159@163.com> Reviewed-by: Niklas Cassel --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 21 +++++++------------ 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index 6cf75160fb1c..8c2b2b642ba7 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -8,6 +8,7 @@ * Author: Simon Xue */ =20 +#include #include #include #include @@ -73,9 +74,8 @@ =20 /* LTSSM Status Register */ #define PCIE_CLIENT_LTSSM_STATUS 0x300 -#define PCIE_SMLH_LINKUP BIT(16) -#define PCIE_RDLH_LINKUP BIT(17) -#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) +#define PCIE_LINKUP 0x3 +#define PCIE_LINKUP_MASK GENMASK(17, 16) #define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) =20 struct rockchip_pcie { @@ -209,10 +209,7 @@ static int rockchip_pcie_link_up(struct dw_pcie *pci) struct rockchip_pcie *rockchip =3D to_rockchip_pcie(pci); u32 val =3D rockchip_pcie_get_ltssm(rockchip); =20 - if ((val & PCIE_LINKUP) =3D=3D PCIE_LINKUP) - return 1; - - return 0; + return FIELD_GET(PCIE_LINKUP_MASK, val) =3D=3D PCIE_LINKUP; } =20 static void rockchip_pcie_enable_l0s(struct dw_pcie *pci) @@ -512,7 +509,7 @@ static irqreturn_t rockchip_pcie_rc_sys_irq_thread(int = irq, void *arg) struct dw_pcie *pci =3D &rockchip->pci; struct dw_pcie_rp *pp =3D &pci->pp; struct device *dev =3D pci->dev; - u32 reg, val; + u32 reg; =20 reg =3D rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC); rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC); @@ -521,8 +518,7 @@ static irqreturn_t rockchip_pcie_rc_sys_irq_thread(int = irq, void *arg) dev_dbg(dev, "LTSSM_STATUS: %#x\n", rockchip_pcie_get_ltssm(rockchip)); =20 if (reg & PCIE_RDLH_LINK_UP_CHGED) { - val =3D rockchip_pcie_get_ltssm(rockchip); - if ((val & PCIE_LINKUP) =3D=3D PCIE_LINKUP) { + if (rockchip_pcie_link_up(pci)) { dev_dbg(dev, "Received Link up event. Starting enumeration!\n"); /* Rescan the bus to enumerate endpoint devices */ pci_lock_rescan_remove(); @@ -539,7 +535,7 @@ static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int = irq, void *arg) struct rockchip_pcie *rockchip =3D arg; struct dw_pcie *pci =3D &rockchip->pci; struct device *dev =3D pci->dev; - u32 reg, val; + u32 reg; =20 reg =3D rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC); rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC); @@ -553,8 +549,7 @@ static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int = irq, void *arg) } =20 if (reg & PCIE_RDLH_LINK_UP_CHGED) { - val =3D rockchip_pcie_get_ltssm(rockchip); - if ((val & PCIE_LINKUP) =3D=3D PCIE_LINKUP) { + if (rockchip_pcie_link_up(pci)) { dev_dbg(dev, "link up\n"); dw_pcie_ep_linkup(&pci->ep); } --=20 2.25.1