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charset="utf-8" Add new compatible for the QPIC NAND controller v2.1.1 used for SDX75 SoC. SDX75 NAND controller has iommu support so define it in the properties section. Reviewed-by: Rob Herring (Arm) Signed-off-by: Kaushal Kumar --- .../devicetree/bindings/mtd/qcom,nandc.yaml | 30 +++++++++++++++---- 1 file changed, 24 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml b/Docume= ntation/devicetree/bindings/mtd/qcom,nandc.yaml index 35b4206ea918..5511389960f0 100644 --- a/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml +++ b/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml @@ -11,12 +11,18 @@ maintainers: =20 properties: compatible: - enum: - - qcom,ipq806x-nand - - qcom,ipq4019-nand - - qcom,ipq6018-nand - - qcom,ipq8074-nand - - qcom,sdx55-nand + oneOf: + - items: + - enum: + - qcom,sdx75-nand + - const: qcom,sdx55-nand + - items: + - enum: + - qcom,ipq806x-nand + - qcom,ipq4019-nand + - qcom,ipq6018-nand + - qcom,ipq8074-nand + - qcom,sdx55-nand =20 reg: maxItems: 1 @@ -95,6 +101,18 @@ allOf: items: - const: rxtx =20 + - if: + properties: + compatible: + contains: + enum: + - qcom,sdx75-nand + + then: + properties: + iommus: + maxItems: 1 + - if: properties: compatible: --=20 2.17.1 From nobody Thu Dec 18 07:16:58 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A51701DFE20; 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charset="utf-8" Qualcomm BAM DMA controller has DMA-coherent support so define it in the properties section. Acked-by: Rob Herring (Arm) Signed-off-by: Kaushal Kumar --- Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml b/Docu= mentation/devicetree/bindings/dma/qcom,bam-dma.yaml index 3ad0d9b1fbc5..f2f87f0f545b 100644 --- a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml @@ -42,6 +42,8 @@ properties: interrupts: maxItems: 1 =20 + dma-coherent: true + iommus: minItems: 1 maxItems: 6 --=20 2.17.1 From nobody Thu Dec 18 07:16:58 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F08125D537; Wed, 23 Apr 2025 06:32:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; 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charset="utf-8" Add devicetree node to enable support for QPIC BAM DMA controller on Qualcomm SDX75 platform. Reviewed-by: Konrad Dybcio Signed-off-by: Kaushal Kumar --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom= /sdx75.dtsi index b0a8a0fe5f39..638e07b00733 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -880,6 +880,20 @@ qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + qpic_bam: dma-controller@1c9c000 { + compatible =3D "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg =3D <0x0 0x01c9c000 0x0 0x1c000>; + interrupts =3D ; + clocks =3D <&rpmhcc RPMH_QPIC_CLK>; + clock-names =3D "bam_clk"; + #dma-cells =3D <1>; + qcom,ee =3D <0>; + qcom,controlled-remotely; + iommus =3D <&apps_smmu 0x100 0x3>; + dma-coherent; + status =3D "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible =3D "qcom,tcsr-mutex"; reg =3D <0x0 0x01f40000 0x0 0x40000>; --=20 2.17.1 From nobody Thu Dec 18 07:16:58 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD53A266F1C; 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charset="utf-8" Add devicetree node to enable support for QPIC NAND controller on Qualcomm SDX75 platform. Reviewed-by: Konrad Dybcio Signed-off-by: Kaushal Kumar --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom= /sdx75.dtsi index 638e07b00733..3e86b1d67130 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -894,6 +894,25 @@ status =3D "disabled"; }; =20 + qpic_nand: nand-controller@1cc8000 { + compatible =3D "qcom,sdx75-nand", "qcom,sdx55-nand"; + reg =3D <0x0 0x01cc8000 0x0 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&rpmhcc RPMH_QPIC_CLK>, + <&sleep_clk>; + clock-names =3D "core", + "aon"; + dmas =3D <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names =3D "tx", + "rx", + "cmd"; + iommus =3D <&apps_smmu 0x100 0x3>; + status =3D "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible =3D "qcom,tcsr-mutex"; reg =3D <0x0 0x01f40000 0x0 0x40000>; --=20 2.17.1 From nobody Thu Dec 18 07:16:58 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 844F1268689; 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charset="utf-8" Enable QPIC BAM and QPIC NAND devicetree nodes for Qualcomm SDX75-IDP board. Reviewed-by: Konrad Dybcio Signed-off-by: Kaushal Kumar --- arch/arm64/boot/dts/qcom/sdx75-idp.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75-idp.dts b/arch/arm64/boot/dts/q= com/sdx75-idp.dts index f1bbe7ab01ab..06cacec3461f 100644 --- a/arch/arm64/boot/dts/qcom/sdx75-idp.dts +++ b/arch/arm64/boot/dts/qcom/sdx75-idp.dts @@ -278,6 +278,24 @@ vdd3-supply =3D <&vreg_l10b_3p08>; }; =20 +&qpic_bam { + status =3D "okay"; +}; + +&qpic_nand { + status =3D "okay"; + + nand@0 { + reg =3D <0>; + + nand-ecc-strength =3D <8>; + nand-ecc-step-size =3D <512>; + nand-bus-width =3D <8>; + /* efs2 partition is secured */ + secure-regions =3D /bits/ 64 <0x680000 0xb00000>; + }; +}; + &qupv3_id_0 { status =3D "okay"; }; --=20 2.17.1