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([2.196.40.29]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-acb6ef9e7e6sm745234366b.162.2025.04.22.23.03.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 23:03:18 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Abel Vesa , Peng Fan , Stephen Boyd , Shawn Guo , Dario Binacchi , Krzysztof Kozlowski , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Michael Turquette , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v11 15/18] dt-bindings: clock: imx8m-clock: add PLLs Date: Wed, 23 Apr 2025 08:02:32 +0200 Message-ID: <20250423060241.95521-16-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250423060241.95521-1-dario.binacchi@amarulasolutions.com> References: <20250423060241.95521-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Though adding the PLLs to clocks and clock-names properties will break the ABI, it is required to accurately describe the hardware. Indeed, the Clock Control Module (CCM) receives clocks from the PLLs and oscillators and generates clocks for on-chip peripherals. Signed-off-by: Dario Binacchi Reviewed-by: Krzysztof Kozlowski --- Changes in v11: - Fix conflict while rebasing on master Changes in v7: - Add 'Reviewed-by' tag of Krzysztof Kozlowski Changes in v6: - New .../bindings/clock/imx8m-clock.yaml | 27 ++++++++++++++----- 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml b/Doc= umentation/devicetree/bindings/clock/imx8m-clock.yaml index 4fec55832702..e83f08abd44c 100644 --- a/Documentation/devicetree/bindings/clock/imx8m-clock.yaml +++ b/Documentation/devicetree/bindings/clock/imx8m-clock.yaml @@ -29,12 +29,12 @@ properties: maxItems: 2 =20 clocks: - minItems: 6 - maxItems: 7 + minItems: 7 + maxItems: 10 =20 clock-names: - minItems: 6 - maxItems: 7 + minItems: 7 + maxItems: 10 =20 '#clock-cells': const: 1 @@ -93,6 +93,10 @@ allOf: - description: ext2 clock input - description: ext3 clock input - description: ext4 clock input + - description: audio1 PLL input + - description: audio2 PLL input + - description: dram PLL input + - description: video PLL input =20 clock-names: items: @@ -102,20 +106,31 @@ allOf: - const: clk_ext2 - const: clk_ext3 - const: clk_ext4 + - const: audio_pll1 + - const: audio_pll2 + - const: dram_pll + - const: video_pll =20 additionalProperties: false =20 examples: # Clock Control Module node: - | + #include + clock-controller@30380000 { compatible =3D "fsl,imx8mm-ccm"; reg =3D <0x30380000 0x10000>; #clock-cells =3D <1>; clocks =3D <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, - <&clk_ext3>, <&clk_ext4>; + <&clk_ext3>, <&clk_ext4>, + <&anatop IMX8MM_ANATOP_AUDIO_PLL1>, + <&anatop IMX8MM_ANATOP_AUDIO_PLL2>, + <&anatop IMX8MM_ANATOP_DRAM_PLL>, + <&anatop IMX8MM_ANATOP_VIDEO_PLL>; clock-names =3D "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", - "clk_ext3", "clk_ext4"; + "clk_ext3", "clk_ext4", "audio_pll1", "audio_pll2", + "dram_pll", "video_pll"; fsl,operating-mode =3D "nominal"; }; =20 --=20 2.43.0