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([2.196.40.29]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-acb6ef9e7e6sm745234366b.162.2025.04.22.23.03.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 23:03:17 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Abel Vesa , Peng Fan , Stephen Boyd , Shawn Guo , Dario Binacchi , Fabio Estevam , Michael Turquette , Pengutronix Kernel Team , Sascha Hauer , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v11 14/18] clk: imx8mp: rename ccm_base to base Date: Wed, 23 Apr 2025 08:02:31 +0200 Message-ID: <20250423060241.95521-15-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250423060241.95521-1-dario.binacchi@amarulasolutions.com> References: <20250423060241.95521-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The old code also accessed the anatop address space and therefore used the variables anatop_base and ccm_base to distinguish between the two address spaces. However, now that a specific anatop driver exists for the i.MX8MP platform, the variable ccm_base can be renamed to base, as is usually the case for the variable pointing to the memory region managed by a Linux driver. The patch does not introduce any functional changes. Signed-off-by: Dario Binacchi Reviewed-by: Peng Fan --- Changes in v11: - Add 'Reviewed-by' tag of Peng Fan - Fix conflict while rebasing on master drivers/clk/imx/clk-imx8mp.c | 378 +++++++++++++++++------------------ 1 file changed, 189 insertions(+), 189 deletions(-) diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 3fa6241dede9..f90533664953 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -532,13 +532,13 @@ static int imx8mp_clocks_probe(struct platform_device= *pdev) { struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node, *anp; - void __iomem *ccm_base; + void __iomem *base; const char *opmode; int err; =20 - ccm_base =3D devm_platform_ioremap_resource(pdev, 0); - if (WARN_ON(IS_ERR(ccm_base))) - return PTR_ERR(ccm_base); + base =3D devm_platform_ioremap_resource(pdev, 0); + if (WARN_ON(IS_ERR(base))) + return PTR_ERR(base); =20 clk_hw_data =3D devm_kzalloc(dev, struct_size(clk_hw_data, hws, IMX8MP_CL= K_END), GFP_KERNEL); if (WARN_ON(!clk_hw_data)) @@ -634,198 +634,198 @@ static int imx8mp_clocks_probe(struct platform_devi= ce *pdev) hws[IMX8MP_CLK_CLKOUT2_DIV] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_= CLK_CLKOUT2_DIV); hws[IMX8MP_CLK_CLKOUT2] =3D imx_anatop_get_clk_hw(anp, IMX8MP_ANATOP_CLK_= CLKOUT2); =20 - hws[IMX8MP_CLK_A53_DIV] =3D imx8m_clk_hw_composite_core("arm_a53_div", im= x8mp_a53_sels, ccm_base + 0x8000); + hws[IMX8MP_CLK_A53_DIV] =3D imx8m_clk_hw_composite_core("arm_a53_div", im= x8mp_a53_sels, base + 0x8000); hws[IMX8MP_CLK_A53_SRC] =3D hws[IMX8MP_CLK_A53_DIV]; hws[IMX8MP_CLK_A53_CG] =3D hws[IMX8MP_CLK_A53_DIV]; - hws[IMX8MP_CLK_M7_CORE] =3D imx8m_clk_hw_composite_core("m7_core", imx8mp= _m7_sels, ccm_base + 0x8080); - hws[IMX8MP_CLK_ML_CORE] =3D imx8m_clk_hw_composite_core("ml_core", imx8mp= _ml_sels, ccm_base + 0x8100); - hws[IMX8MP_CLK_GPU3D_CORE] =3D imx8m_clk_hw_composite_core("gpu3d_core", = imx8mp_gpu3d_core_sels, ccm_base + 0x8180); - hws[IMX8MP_CLK_GPU3D_SHADER_CORE] =3D imx8m_clk_hw_composite("gpu3d_shade= r_core", imx8mp_gpu3d_shader_sels, ccm_base + 0x8200); - hws[IMX8MP_CLK_GPU2D_CORE] =3D imx8m_clk_hw_composite("gpu2d_core", imx8m= p_gpu2d_sels, ccm_base + 0x8280); - hws[IMX8MP_CLK_AUDIO_AXI] =3D imx8m_clk_hw_composite("audio_axi", imx8mp_= audio_axi_sels, ccm_base + 0x8300); + hws[IMX8MP_CLK_M7_CORE] =3D imx8m_clk_hw_composite_core("m7_core", imx8mp= _m7_sels, base + 0x8080); + hws[IMX8MP_CLK_ML_CORE] =3D imx8m_clk_hw_composite_core("ml_core", imx8mp= _ml_sels, base + 0x8100); + hws[IMX8MP_CLK_GPU3D_CORE] =3D imx8m_clk_hw_composite_core("gpu3d_core", = imx8mp_gpu3d_core_sels, base + 0x8180); + hws[IMX8MP_CLK_GPU3D_SHADER_CORE] =3D imx8m_clk_hw_composite("gpu3d_shade= r_core", imx8mp_gpu3d_shader_sels, base + 0x8200); + hws[IMX8MP_CLK_GPU2D_CORE] =3D imx8m_clk_hw_composite("gpu2d_core", imx8m= p_gpu2d_sels, base + 0x8280); + hws[IMX8MP_CLK_AUDIO_AXI] =3D imx8m_clk_hw_composite("audio_axi", imx8mp_= audio_axi_sels, base + 0x8300); hws[IMX8MP_CLK_AUDIO_AXI_SRC] =3D hws[IMX8MP_CLK_AUDIO_AXI]; - hws[IMX8MP_CLK_HSIO_AXI] =3D imx8m_clk_hw_composite("hsio_axi", imx8mp_hs= io_axi_sels, ccm_base + 0x8380); - hws[IMX8MP_CLK_MEDIA_ISP] =3D imx8m_clk_hw_composite("media_isp", imx8mp_= media_isp_sels, ccm_base + 0x8400); + hws[IMX8MP_CLK_HSIO_AXI] =3D imx8m_clk_hw_composite("hsio_axi", imx8mp_hs= io_axi_sels, base + 0x8380); + hws[IMX8MP_CLK_MEDIA_ISP] =3D imx8m_clk_hw_composite("media_isp", imx8mp_= media_isp_sels, base + 0x8400); =20 /* CORE SEL */ - hws[IMX8MP_CLK_A53_CORE] =3D imx_clk_hw_mux2("arm_a53_core", ccm_base + 0= x9880, 24, 1, imx8mp_a53_core_sels, ARRAY_SIZE(imx8mp_a53_core_sels)); - - hws[IMX8MP_CLK_MAIN_AXI] =3D imx8m_clk_hw_composite_bus_critical("main_ax= i", imx8mp_main_axi_sels, ccm_base + 0x8800); - hws[IMX8MP_CLK_ENET_AXI] =3D imx8m_clk_hw_composite_bus("enet_axi", imx8m= p_enet_axi_sels, ccm_base + 0x8880); - hws[IMX8MP_CLK_NAND_USDHC_BUS] =3D imx8m_clk_hw_composite("nand_usdhc_bus= ", imx8mp_nand_usdhc_sels, ccm_base + 0x8900); - hws[IMX8MP_CLK_VPU_BUS] =3D imx8m_clk_hw_composite_bus("vpu_bus", imx8mp_= vpu_bus_sels, ccm_base + 0x8980); - hws[IMX8MP_CLK_MEDIA_AXI] =3D imx8m_clk_hw_composite_bus("media_axi", imx= 8mp_media_axi_sels, ccm_base + 0x8a00); - hws[IMX8MP_CLK_MEDIA_APB] =3D imx8m_clk_hw_composite_bus("media_apb", imx= 8mp_media_apb_sels, ccm_base + 0x8a80); - hws[IMX8MP_CLK_HDMI_APB] =3D imx8m_clk_hw_composite_bus("hdmi_apb", imx8m= p_media_apb_sels, ccm_base + 0x8b00); - hws[IMX8MP_CLK_HDMI_AXI] =3D imx8m_clk_hw_composite_bus("hdmi_axi", imx8m= p_media_axi_sels, ccm_base + 0x8b80); - hws[IMX8MP_CLK_GPU_AXI] =3D imx8m_clk_hw_composite_bus("gpu_axi", imx8mp_= gpu_axi_sels, ccm_base + 0x8c00); - hws[IMX8MP_CLK_GPU_AHB] =3D imx8m_clk_hw_composite_bus("gpu_ahb", imx8mp_= gpu_ahb_sels, ccm_base + 0x8c80); - hws[IMX8MP_CLK_NOC] =3D imx8m_clk_hw_composite_bus_critical("noc", imx8mp= _noc_sels, ccm_base + 0x8d00); - hws[IMX8MP_CLK_NOC_IO] =3D imx8m_clk_hw_composite_bus_critical("noc_io", = imx8mp_noc_io_sels, ccm_base + 0x8d80); - hws[IMX8MP_CLK_ML_AXI] =3D imx8m_clk_hw_composite_bus("ml_axi", imx8mp_ml= _axi_sels, ccm_base + 0x8e00); - hws[IMX8MP_CLK_ML_AHB] =3D imx8m_clk_hw_composite_bus("ml_ahb", imx8mp_ml= _ahb_sels, ccm_base + 0x8e80); - - hws[IMX8MP_CLK_AHB] =3D imx8m_clk_hw_composite_bus_critical("ahb_root", i= mx8mp_ahb_sels, ccm_base + 0x9000); - hws[IMX8MP_CLK_AUDIO_AHB] =3D imx8m_clk_hw_composite_bus("audio_ahb", imx= 8mp_audio_ahb_sels, ccm_base + 0x9100); - hws[IMX8MP_CLK_MIPI_DSI_ESC_RX] =3D imx8m_clk_hw_composite_bus("mipi_dsi_= esc_rx", imx8mp_mipi_dsi_esc_rx_sels, ccm_base + 0x9200); - hws[IMX8MP_CLK_MEDIA_DISP2_PIX] =3D imx8m_clk_hw_composite_bus_flags("med= ia_disp2_pix", imx8mp_media_disp_pix_sels, ccm_base + 0x9300, CLK_SET_RATE_= PARENT); - - hws[IMX8MP_CLK_IPG_ROOT] =3D imx_clk_hw_divider2("ipg_root", "ahb_root", = ccm_base + 0x9080, 0, 1); - - hws[IMX8MP_CLK_DRAM_ALT] =3D imx8m_clk_hw_fw_managed_composite("dram_alt"= , imx8mp_dram_alt_sels, ccm_base + 0xa000); - hws[IMX8MP_CLK_DRAM_APB] =3D imx8m_clk_hw_fw_managed_composite_critical("= dram_apb", imx8mp_dram_apb_sels, ccm_base + 0xa080); - hws[IMX8MP_CLK_VPU_G1] =3D imx8m_clk_hw_composite("vpu_g1", imx8mp_vpu_g1= _sels, ccm_base + 0xa100); - hws[IMX8MP_CLK_VPU_G2] =3D imx8m_clk_hw_composite("vpu_g2", imx8mp_vpu_g2= _sels, ccm_base + 0xa180); - hws[IMX8MP_CLK_CAN1] =3D imx8m_clk_hw_composite("can1", imx8mp_can1_sels,= ccm_base + 0xa200); - hws[IMX8MP_CLK_CAN2] =3D imx8m_clk_hw_composite("can2", imx8mp_can2_sels,= ccm_base + 0xa280); - hws[IMX8MP_CLK_PCIE_AUX] =3D imx8m_clk_hw_composite("pcie_aux", imx8mp_pc= ie_aux_sels, ccm_base + 0xa400); - hws[IMX8MP_CLK_I2C5] =3D imx8m_clk_hw_composite("i2c5", imx8mp_i2c5_sels,= ccm_base + 0xa480); - hws[IMX8MP_CLK_I2C6] =3D imx8m_clk_hw_composite("i2c6", imx8mp_i2c6_sels,= ccm_base + 0xa500); - hws[IMX8MP_CLK_SAI1] =3D imx8m_clk_hw_composite("sai1", imx8mp_sai1_sels,= ccm_base + 0xa580); - hws[IMX8MP_CLK_SAI2] =3D imx8m_clk_hw_composite("sai2", imx8mp_sai2_sels,= ccm_base + 0xa600); - hws[IMX8MP_CLK_SAI3] =3D imx8m_clk_hw_composite("sai3", imx8mp_sai3_sels,= ccm_base + 0xa680); - hws[IMX8MP_CLK_SAI5] =3D imx8m_clk_hw_composite("sai5", imx8mp_sai5_sels,= ccm_base + 0xa780); - hws[IMX8MP_CLK_SAI6] =3D imx8m_clk_hw_composite("sai6", imx8mp_sai6_sels,= ccm_base + 0xa800); - hws[IMX8MP_CLK_ENET_QOS] =3D imx8m_clk_hw_composite("enet_qos", imx8mp_en= et_qos_sels, ccm_base + 0xa880); - hws[IMX8MP_CLK_ENET_QOS_TIMER] =3D imx8m_clk_hw_composite("enet_qos_timer= ", imx8mp_enet_qos_timer_sels, ccm_base + 0xa900); - hws[IMX8MP_CLK_ENET_REF] =3D imx8m_clk_hw_composite("enet_ref", imx8mp_en= et_ref_sels, ccm_base + 0xa980); - hws[IMX8MP_CLK_ENET_TIMER] =3D imx8m_clk_hw_composite("enet_timer", imx8m= p_enet_timer_sels, ccm_base + 0xaa00); - hws[IMX8MP_CLK_ENET_PHY_REF] =3D imx8m_clk_hw_composite("enet_phy_ref", i= mx8mp_enet_phy_ref_sels, ccm_base + 0xaa80); - hws[IMX8MP_CLK_NAND] =3D imx8m_clk_hw_composite("nand", imx8mp_nand_sels,= ccm_base + 0xab00); - hws[IMX8MP_CLK_QSPI] =3D imx8m_clk_hw_composite("qspi", imx8mp_qspi_sels,= ccm_base + 0xab80); - hws[IMX8MP_CLK_USDHC1] =3D imx8m_clk_hw_composite("usdhc1", imx8mp_usdhc1= _sels, ccm_base + 0xac00); - hws[IMX8MP_CLK_USDHC2] =3D imx8m_clk_hw_composite("usdhc2", imx8mp_usdhc2= _sels, ccm_base + 0xac80); - hws[IMX8MP_CLK_I2C1] =3D imx8m_clk_hw_composite("i2c1", imx8mp_i2c1_sels,= ccm_base + 0xad00); - hws[IMX8MP_CLK_I2C2] =3D imx8m_clk_hw_composite("i2c2", imx8mp_i2c2_sels,= ccm_base + 0xad80); - hws[IMX8MP_CLK_I2C3] =3D imx8m_clk_hw_composite("i2c3", imx8mp_i2c3_sels,= ccm_base + 0xae00); - hws[IMX8MP_CLK_I2C4] =3D imx8m_clk_hw_composite("i2c4", imx8mp_i2c4_sels,= ccm_base + 0xae80); - - hws[IMX8MP_CLK_UART1] =3D imx8m_clk_hw_composite("uart1", imx8mp_uart1_se= ls, ccm_base + 0xaf00); - hws[IMX8MP_CLK_UART2] =3D imx8m_clk_hw_composite("uart2", imx8mp_uart2_se= ls, ccm_base + 0xaf80); - hws[IMX8MP_CLK_UART3] =3D imx8m_clk_hw_composite("uart3", imx8mp_uart3_se= ls, ccm_base + 0xb000); - hws[IMX8MP_CLK_UART4] =3D imx8m_clk_hw_composite("uart4", imx8mp_uart4_se= ls, ccm_base + 0xb080); - hws[IMX8MP_CLK_USB_CORE_REF] =3D imx8m_clk_hw_composite("usb_core_ref", i= mx8mp_usb_core_ref_sels, ccm_base + 0xb100); - hws[IMX8MP_CLK_USB_PHY_REF] =3D imx8m_clk_hw_composite("usb_phy_ref", imx= 8mp_usb_phy_ref_sels, ccm_base + 0xb180); - hws[IMX8MP_CLK_GIC] =3D imx8m_clk_hw_composite_critical("gic", imx8mp_gic= _sels, ccm_base + 0xb200); - hws[IMX8MP_CLK_ECSPI1] =3D imx8m_clk_hw_composite("ecspi1", imx8mp_ecspi1= _sels, ccm_base + 0xb280); - hws[IMX8MP_CLK_ECSPI2] =3D imx8m_clk_hw_composite("ecspi2", imx8mp_ecspi2= _sels, ccm_base + 0xb300); - hws[IMX8MP_CLK_PWM1] =3D imx8m_clk_hw_composite("pwm1", imx8mp_pwm1_sels,= ccm_base + 0xb380); - hws[IMX8MP_CLK_PWM2] =3D imx8m_clk_hw_composite("pwm2", imx8mp_pwm2_sels,= ccm_base + 0xb400); - hws[IMX8MP_CLK_PWM3] =3D imx8m_clk_hw_composite("pwm3", imx8mp_pwm3_sels,= ccm_base + 0xb480); - hws[IMX8MP_CLK_PWM4] =3D imx8m_clk_hw_composite("pwm4", imx8mp_pwm4_sels,= ccm_base + 0xb500); - - hws[IMX8MP_CLK_GPT1] =3D imx8m_clk_hw_composite("gpt1", imx8mp_gpt1_sels,= ccm_base + 0xb580); - hws[IMX8MP_CLK_GPT2] =3D imx8m_clk_hw_composite("gpt2", imx8mp_gpt2_sels,= ccm_base + 0xb600); - hws[IMX8MP_CLK_GPT3] =3D imx8m_clk_hw_composite("gpt3", imx8mp_gpt3_sels,= ccm_base + 0xb680); - hws[IMX8MP_CLK_GPT4] =3D imx8m_clk_hw_composite("gpt4", imx8mp_gpt4_sels,= ccm_base + 0xb700); - hws[IMX8MP_CLK_GPT5] =3D imx8m_clk_hw_composite("gpt5", imx8mp_gpt5_sels,= ccm_base + 0xb780); - hws[IMX8MP_CLK_GPT6] =3D imx8m_clk_hw_composite("gpt6", imx8mp_gpt6_sels,= ccm_base + 0xb800); - hws[IMX8MP_CLK_WDOG] =3D imx8m_clk_hw_composite("wdog", imx8mp_wdog_sels,= ccm_base + 0xb900); - hws[IMX8MP_CLK_WRCLK] =3D imx8m_clk_hw_composite("wrclk", imx8mp_wrclk_se= ls, ccm_base + 0xb980); - hws[IMX8MP_CLK_IPP_DO_CLKO1] =3D imx8m_clk_hw_composite("ipp_do_clko1", i= mx8mp_ipp_do_clko1_sels, ccm_base + 0xba00); - hws[IMX8MP_CLK_IPP_DO_CLKO2] =3D imx8m_clk_hw_composite("ipp_do_clko2", i= mx8mp_ipp_do_clko2_sels, ccm_base + 0xba80); - hws[IMX8MP_CLK_HDMI_FDCC_TST] =3D imx8m_clk_hw_composite("hdmi_fdcc_tst",= imx8mp_hdmi_fdcc_tst_sels, ccm_base + 0xbb00); - hws[IMX8MP_CLK_HDMI_24M] =3D imx8m_clk_hw_composite("hdmi_24m", imx8mp_hd= mi_24m_sels, ccm_base + 0xbb80); - hws[IMX8MP_CLK_HDMI_REF_266M] =3D imx8m_clk_hw_composite("hdmi_ref_266m",= imx8mp_hdmi_ref_266m_sels, ccm_base + 0xbc00); - hws[IMX8MP_CLK_USDHC3] =3D imx8m_clk_hw_composite("usdhc3", imx8mp_usdhc3= _sels, ccm_base + 0xbc80); - hws[IMX8MP_CLK_MEDIA_CAM1_PIX] =3D imx8m_clk_hw_composite("media_cam1_pix= ", imx8mp_media_cam1_pix_sels, ccm_base + 0xbd00); - hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF] =3D imx8m_clk_hw_composite("media_mip= i_phy1_ref", imx8mp_media_mipi_phy1_ref_sels, ccm_base + 0xbd80); - hws[IMX8MP_CLK_MEDIA_DISP1_PIX] =3D imx8m_clk_hw_composite_bus_flags("med= ia_disp1_pix", imx8mp_media_disp_pix_sels, ccm_base + 0xbe00, CLK_SET_RATE_= PARENT); - hws[IMX8MP_CLK_MEDIA_CAM2_PIX] =3D imx8m_clk_hw_composite("media_cam2_pix= ", imx8mp_media_cam2_pix_sels, ccm_base + 0xbe80); - hws[IMX8MP_CLK_MEDIA_LDB] =3D imx8m_clk_hw_composite("media_ldb", imx8mp_= media_ldb_sels, ccm_base + 0xbf00); - hws[IMX8MP_CLK_MEMREPAIR] =3D imx8m_clk_hw_composite_critical("mem_repair= ", imx8mp_memrepair_sels, ccm_base + 0xbf80); - hws[IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE] =3D imx8m_clk_hw_composite("media_mi= pi_test_byte", imx8mp_media_mipi_test_byte_sels, ccm_base + 0xc100); - hws[IMX8MP_CLK_ECSPI3] =3D imx8m_clk_hw_composite("ecspi3", imx8mp_ecspi3= _sels, ccm_base + 0xc180); - hws[IMX8MP_CLK_PDM] =3D imx8m_clk_hw_composite("pdm", imx8mp_pdm_sels, cc= m_base + 0xc200); - hws[IMX8MP_CLK_VPU_VC8000E] =3D imx8m_clk_hw_composite("vpu_vc8000e", imx= 8mp_vpu_vc8000e_sels, ccm_base + 0xc280); - hws[IMX8MP_CLK_SAI7] =3D imx8m_clk_hw_composite("sai7", imx8mp_sai7_sels,= ccm_base + 0xc300); + hws[IMX8MP_CLK_A53_CORE] =3D imx_clk_hw_mux2("arm_a53_core", base + 0x988= 0, 24, 1, imx8mp_a53_core_sels, ARRAY_SIZE(imx8mp_a53_core_sels)); + + hws[IMX8MP_CLK_MAIN_AXI] =3D imx8m_clk_hw_composite_bus_critical("main_ax= i", imx8mp_main_axi_sels, base + 0x8800); + hws[IMX8MP_CLK_ENET_AXI] =3D imx8m_clk_hw_composite_bus("enet_axi", imx8m= p_enet_axi_sels, base + 0x8880); + hws[IMX8MP_CLK_NAND_USDHC_BUS] =3D imx8m_clk_hw_composite("nand_usdhc_bus= ", imx8mp_nand_usdhc_sels, base + 0x8900); + hws[IMX8MP_CLK_VPU_BUS] =3D imx8m_clk_hw_composite_bus("vpu_bus", imx8mp_= vpu_bus_sels, base + 0x8980); + hws[IMX8MP_CLK_MEDIA_AXI] =3D imx8m_clk_hw_composite_bus("media_axi", imx= 8mp_media_axi_sels, base + 0x8a00); + hws[IMX8MP_CLK_MEDIA_APB] =3D imx8m_clk_hw_composite_bus("media_apb", imx= 8mp_media_apb_sels, base + 0x8a80); + hws[IMX8MP_CLK_HDMI_APB] =3D imx8m_clk_hw_composite_bus("hdmi_apb", imx8m= p_media_apb_sels, base + 0x8b00); + hws[IMX8MP_CLK_HDMI_AXI] =3D imx8m_clk_hw_composite_bus("hdmi_axi", imx8m= p_media_axi_sels, base + 0x8b80); + hws[IMX8MP_CLK_GPU_AXI] =3D imx8m_clk_hw_composite_bus("gpu_axi", imx8mp_= gpu_axi_sels, base + 0x8c00); + hws[IMX8MP_CLK_GPU_AHB] =3D imx8m_clk_hw_composite_bus("gpu_ahb", imx8mp_= gpu_ahb_sels, base + 0x8c80); + hws[IMX8MP_CLK_NOC] =3D imx8m_clk_hw_composite_bus_critical("noc", imx8mp= _noc_sels, base + 0x8d00); + hws[IMX8MP_CLK_NOC_IO] =3D imx8m_clk_hw_composite_bus_critical("noc_io", = imx8mp_noc_io_sels, base + 0x8d80); + hws[IMX8MP_CLK_ML_AXI] =3D imx8m_clk_hw_composite_bus("ml_axi", imx8mp_ml= _axi_sels, base + 0x8e00); + hws[IMX8MP_CLK_ML_AHB] =3D imx8m_clk_hw_composite_bus("ml_ahb", imx8mp_ml= _ahb_sels, base + 0x8e80); + + hws[IMX8MP_CLK_AHB] =3D imx8m_clk_hw_composite_bus_critical("ahb_root", i= mx8mp_ahb_sels, base + 0x9000); + hws[IMX8MP_CLK_AUDIO_AHB] =3D imx8m_clk_hw_composite_bus("audio_ahb", imx= 8mp_audio_ahb_sels, base + 0x9100); + hws[IMX8MP_CLK_MIPI_DSI_ESC_RX] =3D imx8m_clk_hw_composite_bus("mipi_dsi_= esc_rx", imx8mp_mipi_dsi_esc_rx_sels, base + 0x9200); + hws[IMX8MP_CLK_MEDIA_DISP2_PIX] =3D imx8m_clk_hw_composite_bus_flags("med= ia_disp2_pix", imx8mp_media_disp_pix_sels, base + 0x9300, CLK_SET_RATE_PARE= NT); + + hws[IMX8MP_CLK_IPG_ROOT] =3D imx_clk_hw_divider2("ipg_root", "ahb_root", = base + 0x9080, 0, 1); + + hws[IMX8MP_CLK_DRAM_ALT] =3D imx8m_clk_hw_fw_managed_composite("dram_alt"= , imx8mp_dram_alt_sels, base + 0xa000); + hws[IMX8MP_CLK_DRAM_APB] =3D imx8m_clk_hw_fw_managed_composite_critical("= dram_apb", imx8mp_dram_apb_sels, base + 0xa080); + hws[IMX8MP_CLK_VPU_G1] =3D imx8m_clk_hw_composite("vpu_g1", imx8mp_vpu_g1= _sels, base + 0xa100); + hws[IMX8MP_CLK_VPU_G2] =3D imx8m_clk_hw_composite("vpu_g2", imx8mp_vpu_g2= _sels, base + 0xa180); + hws[IMX8MP_CLK_CAN1] =3D imx8m_clk_hw_composite("can1", imx8mp_can1_sels,= base + 0xa200); + hws[IMX8MP_CLK_CAN2] =3D imx8m_clk_hw_composite("can2", imx8mp_can2_sels,= base + 0xa280); + hws[IMX8MP_CLK_PCIE_AUX] =3D imx8m_clk_hw_composite("pcie_aux", imx8mp_pc= ie_aux_sels, base + 0xa400); + hws[IMX8MP_CLK_I2C5] =3D imx8m_clk_hw_composite("i2c5", imx8mp_i2c5_sels,= base + 0xa480); + hws[IMX8MP_CLK_I2C6] =3D imx8m_clk_hw_composite("i2c6", imx8mp_i2c6_sels,= base + 0xa500); + hws[IMX8MP_CLK_SAI1] =3D imx8m_clk_hw_composite("sai1", imx8mp_sai1_sels,= base + 0xa580); + hws[IMX8MP_CLK_SAI2] =3D imx8m_clk_hw_composite("sai2", imx8mp_sai2_sels,= base + 0xa600); + hws[IMX8MP_CLK_SAI3] =3D imx8m_clk_hw_composite("sai3", imx8mp_sai3_sels,= base + 0xa680); + hws[IMX8MP_CLK_SAI5] =3D imx8m_clk_hw_composite("sai5", imx8mp_sai5_sels,= base + 0xa780); + hws[IMX8MP_CLK_SAI6] =3D imx8m_clk_hw_composite("sai6", imx8mp_sai6_sels,= base + 0xa800); + hws[IMX8MP_CLK_ENET_QOS] =3D imx8m_clk_hw_composite("enet_qos", imx8mp_en= et_qos_sels, base + 0xa880); + hws[IMX8MP_CLK_ENET_QOS_TIMER] =3D imx8m_clk_hw_composite("enet_qos_timer= ", imx8mp_enet_qos_timer_sels, base + 0xa900); + hws[IMX8MP_CLK_ENET_REF] =3D imx8m_clk_hw_composite("enet_ref", imx8mp_en= et_ref_sels, base + 0xa980); + hws[IMX8MP_CLK_ENET_TIMER] =3D imx8m_clk_hw_composite("enet_timer", imx8m= p_enet_timer_sels, base + 0xaa00); + hws[IMX8MP_CLK_ENET_PHY_REF] =3D imx8m_clk_hw_composite("enet_phy_ref", i= mx8mp_enet_phy_ref_sels, base + 0xaa80); + hws[IMX8MP_CLK_NAND] =3D imx8m_clk_hw_composite("nand", imx8mp_nand_sels,= base + 0xab00); + hws[IMX8MP_CLK_QSPI] =3D imx8m_clk_hw_composite("qspi", imx8mp_qspi_sels,= base + 0xab80); + hws[IMX8MP_CLK_USDHC1] =3D imx8m_clk_hw_composite("usdhc1", imx8mp_usdhc1= _sels, base + 0xac00); + hws[IMX8MP_CLK_USDHC2] =3D imx8m_clk_hw_composite("usdhc2", imx8mp_usdhc2= _sels, base + 0xac80); + hws[IMX8MP_CLK_I2C1] =3D imx8m_clk_hw_composite("i2c1", imx8mp_i2c1_sels,= base + 0xad00); + hws[IMX8MP_CLK_I2C2] =3D imx8m_clk_hw_composite("i2c2", imx8mp_i2c2_sels,= base + 0xad80); + hws[IMX8MP_CLK_I2C3] =3D imx8m_clk_hw_composite("i2c3", imx8mp_i2c3_sels,= base + 0xae00); + hws[IMX8MP_CLK_I2C4] =3D imx8m_clk_hw_composite("i2c4", imx8mp_i2c4_sels,= base + 0xae80); + + hws[IMX8MP_CLK_UART1] =3D imx8m_clk_hw_composite("uart1", imx8mp_uart1_se= ls, base + 0xaf00); + hws[IMX8MP_CLK_UART2] =3D imx8m_clk_hw_composite("uart2", imx8mp_uart2_se= ls, base + 0xaf80); + hws[IMX8MP_CLK_UART3] =3D imx8m_clk_hw_composite("uart3", imx8mp_uart3_se= ls, base + 0xb000); + hws[IMX8MP_CLK_UART4] =3D imx8m_clk_hw_composite("uart4", imx8mp_uart4_se= ls, base + 0xb080); + hws[IMX8MP_CLK_USB_CORE_REF] =3D imx8m_clk_hw_composite("usb_core_ref", i= mx8mp_usb_core_ref_sels, base + 0xb100); + hws[IMX8MP_CLK_USB_PHY_REF] =3D imx8m_clk_hw_composite("usb_phy_ref", imx= 8mp_usb_phy_ref_sels, base + 0xb180); + hws[IMX8MP_CLK_GIC] =3D imx8m_clk_hw_composite_critical("gic", imx8mp_gic= _sels, base + 0xb200); + hws[IMX8MP_CLK_ECSPI1] =3D imx8m_clk_hw_composite("ecspi1", imx8mp_ecspi1= _sels, base + 0xb280); + hws[IMX8MP_CLK_ECSPI2] =3D imx8m_clk_hw_composite("ecspi2", imx8mp_ecspi2= _sels, base + 0xb300); + hws[IMX8MP_CLK_PWM1] =3D imx8m_clk_hw_composite("pwm1", imx8mp_pwm1_sels,= base + 0xb380); + hws[IMX8MP_CLK_PWM2] =3D imx8m_clk_hw_composite("pwm2", imx8mp_pwm2_sels,= base + 0xb400); + hws[IMX8MP_CLK_PWM3] =3D imx8m_clk_hw_composite("pwm3", imx8mp_pwm3_sels,= base + 0xb480); + hws[IMX8MP_CLK_PWM4] =3D imx8m_clk_hw_composite("pwm4", imx8mp_pwm4_sels,= base + 0xb500); + + hws[IMX8MP_CLK_GPT1] =3D imx8m_clk_hw_composite("gpt1", imx8mp_gpt1_sels,= base + 0xb580); + hws[IMX8MP_CLK_GPT2] =3D imx8m_clk_hw_composite("gpt2", imx8mp_gpt2_sels,= base + 0xb600); + hws[IMX8MP_CLK_GPT3] =3D imx8m_clk_hw_composite("gpt3", imx8mp_gpt3_sels,= base + 0xb680); + hws[IMX8MP_CLK_GPT4] =3D imx8m_clk_hw_composite("gpt4", imx8mp_gpt4_sels,= base + 0xb700); + hws[IMX8MP_CLK_GPT5] =3D imx8m_clk_hw_composite("gpt5", imx8mp_gpt5_sels,= base + 0xb780); + hws[IMX8MP_CLK_GPT6] =3D imx8m_clk_hw_composite("gpt6", imx8mp_gpt6_sels,= base + 0xb800); + hws[IMX8MP_CLK_WDOG] =3D imx8m_clk_hw_composite("wdog", imx8mp_wdog_sels,= base + 0xb900); + hws[IMX8MP_CLK_WRCLK] =3D imx8m_clk_hw_composite("wrclk", imx8mp_wrclk_se= ls, base + 0xb980); + hws[IMX8MP_CLK_IPP_DO_CLKO1] =3D imx8m_clk_hw_composite("ipp_do_clko1", i= mx8mp_ipp_do_clko1_sels, base + 0xba00); + hws[IMX8MP_CLK_IPP_DO_CLKO2] =3D imx8m_clk_hw_composite("ipp_do_clko2", i= mx8mp_ipp_do_clko2_sels, base + 0xba80); + hws[IMX8MP_CLK_HDMI_FDCC_TST] =3D imx8m_clk_hw_composite("hdmi_fdcc_tst",= imx8mp_hdmi_fdcc_tst_sels, base + 0xbb00); + hws[IMX8MP_CLK_HDMI_24M] =3D imx8m_clk_hw_composite("hdmi_24m", imx8mp_hd= mi_24m_sels, base + 0xbb80); + hws[IMX8MP_CLK_HDMI_REF_266M] =3D imx8m_clk_hw_composite("hdmi_ref_266m",= imx8mp_hdmi_ref_266m_sels, base + 0xbc00); + hws[IMX8MP_CLK_USDHC3] =3D imx8m_clk_hw_composite("usdhc3", imx8mp_usdhc3= _sels, base + 0xbc80); + hws[IMX8MP_CLK_MEDIA_CAM1_PIX] =3D imx8m_clk_hw_composite("media_cam1_pix= ", imx8mp_media_cam1_pix_sels, base + 0xbd00); + hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF] =3D imx8m_clk_hw_composite("media_mip= i_phy1_ref", imx8mp_media_mipi_phy1_ref_sels, base + 0xbd80); + hws[IMX8MP_CLK_MEDIA_DISP1_PIX] =3D imx8m_clk_hw_composite_bus_flags("med= ia_disp1_pix", imx8mp_media_disp_pix_sels, base + 0xbe00, CLK_SET_RATE_PARE= NT); + hws[IMX8MP_CLK_MEDIA_CAM2_PIX] =3D imx8m_clk_hw_composite("media_cam2_pix= ", imx8mp_media_cam2_pix_sels, base + 0xbe80); + hws[IMX8MP_CLK_MEDIA_LDB] =3D imx8m_clk_hw_composite("media_ldb", imx8mp_= media_ldb_sels, base + 0xbf00); + hws[IMX8MP_CLK_MEMREPAIR] =3D imx8m_clk_hw_composite_critical("mem_repair= ", imx8mp_memrepair_sels, base + 0xbf80); + hws[IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE] =3D imx8m_clk_hw_composite("media_mi= pi_test_byte", imx8mp_media_mipi_test_byte_sels, base + 0xc100); + hws[IMX8MP_CLK_ECSPI3] =3D imx8m_clk_hw_composite("ecspi3", imx8mp_ecspi3= _sels, base + 0xc180); + hws[IMX8MP_CLK_PDM] =3D imx8m_clk_hw_composite("pdm", imx8mp_pdm_sels, ba= se + 0xc200); + hws[IMX8MP_CLK_VPU_VC8000E] =3D imx8m_clk_hw_composite("vpu_vc8000e", imx= 8mp_vpu_vc8000e_sels, base + 0xc280); + hws[IMX8MP_CLK_SAI7] =3D imx8m_clk_hw_composite("sai7", imx8mp_sai7_sels,= base + 0xc300); =20 hws[IMX8MP_CLK_DRAM_ALT_ROOT] =3D imx_clk_hw_fixed_factor("dram_alt_root"= , "dram_alt", 1, 4); - hws[IMX8MP_CLK_DRAM_CORE] =3D imx_clk_hw_mux2_flags("dram_core_clk", ccm_= base + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_se= ls), CLK_IS_CRITICAL); - - hws[IMX8MP_CLK_DRAM1_ROOT] =3D imx_clk_hw_gate4_flags("dram1_root_clk", "= dram_core_clk", ccm_base + 0x4050, 0, CLK_IS_CRITICAL); - hws[IMX8MP_CLK_ECSPI1_ROOT] =3D imx_clk_hw_gate4("ecspi1_root_clk", "ecsp= i1", ccm_base + 0x4070, 0); - hws[IMX8MP_CLK_ECSPI2_ROOT] =3D imx_clk_hw_gate4("ecspi2_root_clk", "ecsp= i2", ccm_base + 0x4080, 0); - hws[IMX8MP_CLK_ECSPI3_ROOT] =3D imx_clk_hw_gate4("ecspi3_root_clk", "ecsp= i3", ccm_base + 0x4090, 0); - hws[IMX8MP_CLK_ENET1_ROOT] =3D imx_clk_hw_gate4("enet1_root_clk", "enet_a= xi", ccm_base + 0x40a0, 0); - hws[IMX8MP_CLK_GPIO1_ROOT] =3D imx_clk_hw_gate4("gpio1_root_clk", "ipg_ro= ot", ccm_base + 0x40b0, 0); - hws[IMX8MP_CLK_GPIO2_ROOT] =3D imx_clk_hw_gate4("gpio2_root_clk", "ipg_ro= ot", ccm_base + 0x40c0, 0); - hws[IMX8MP_CLK_GPIO3_ROOT] =3D imx_clk_hw_gate4("gpio3_root_clk", "ipg_ro= ot", ccm_base + 0x40d0, 0); - hws[IMX8MP_CLK_GPIO4_ROOT] =3D imx_clk_hw_gate4("gpio4_root_clk", "ipg_ro= ot", ccm_base + 0x40e0, 0); - hws[IMX8MP_CLK_GPIO5_ROOT] =3D imx_clk_hw_gate4("gpio5_root_clk", "ipg_ro= ot", ccm_base + 0x40f0, 0); - hws[IMX8MP_CLK_GPT1_ROOT] =3D imx_clk_hw_gate4("gpt1_root_clk", "gpt1", c= cm_base + 0x4100, 0); - hws[IMX8MP_CLK_GPT2_ROOT] =3D imx_clk_hw_gate4("gpt2_root_clk", "gpt2", c= cm_base + 0x4110, 0); - hws[IMX8MP_CLK_GPT3_ROOT] =3D imx_clk_hw_gate4("gpt3_root_clk", "gpt3", c= cm_base + 0x4120, 0); - hws[IMX8MP_CLK_GPT4_ROOT] =3D imx_clk_hw_gate4("gpt4_root_clk", "gpt4", c= cm_base + 0x4130, 0); - hws[IMX8MP_CLK_GPT5_ROOT] =3D imx_clk_hw_gate4("gpt5_root_clk", "gpt5", c= cm_base + 0x4140, 0); - hws[IMX8MP_CLK_GPT6_ROOT] =3D imx_clk_hw_gate4("gpt6_root_clk", "gpt6", c= cm_base + 0x4150, 0); - hws[IMX8MP_CLK_I2C1_ROOT] =3D imx_clk_hw_gate4("i2c1_root_clk", "i2c1", c= cm_base + 0x4170, 0); - hws[IMX8MP_CLK_I2C2_ROOT] =3D imx_clk_hw_gate4("i2c2_root_clk", "i2c2", c= cm_base + 0x4180, 0); - hws[IMX8MP_CLK_I2C3_ROOT] =3D imx_clk_hw_gate4("i2c3_root_clk", "i2c3", c= cm_base + 0x4190, 0); - hws[IMX8MP_CLK_I2C4_ROOT] =3D imx_clk_hw_gate4("i2c4_root_clk", "i2c4", c= cm_base + 0x41a0, 0); - hws[IMX8MP_CLK_MU_ROOT] =3D imx_clk_hw_gate4("mu_root_clk", "ipg_root", c= cm_base + 0x4210, 0); - hws[IMX8MP_CLK_OCOTP_ROOT] =3D imx_clk_hw_gate4("ocotp_root_clk", "ipg_ro= ot", ccm_base + 0x4220, 0); - hws[IMX8MP_CLK_PCIE_ROOT] =3D imx_clk_hw_gate4("pcie_root_clk", "pcie_aux= ", ccm_base + 0x4250, 0); - hws[IMX8MP_CLK_PWM1_ROOT] =3D imx_clk_hw_gate4("pwm1_root_clk", "pwm1", c= cm_base + 0x4280, 0); - hws[IMX8MP_CLK_PWM2_ROOT] =3D imx_clk_hw_gate4("pwm2_root_clk", "pwm2", c= cm_base + 0x4290, 0); - hws[IMX8MP_CLK_PWM3_ROOT] =3D imx_clk_hw_gate4("pwm3_root_clk", "pwm3", c= cm_base + 0x42a0, 0); - hws[IMX8MP_CLK_PWM4_ROOT] =3D imx_clk_hw_gate4("pwm4_root_clk", "pwm4", c= cm_base + 0x42b0, 0); - hws[IMX8MP_CLK_QOS_ROOT] =3D imx_clk_hw_gate4("qos_root_clk", "ipg_root",= ccm_base + 0x42c0, 0); - hws[IMX8MP_CLK_QOS_ENET_ROOT] =3D imx_clk_hw_gate4("qos_enet_root_clk", "= ipg_root", ccm_base + 0x42e0, 0); - hws[IMX8MP_CLK_QSPI_ROOT] =3D imx_clk_hw_gate4("qspi_root_clk", "qspi", c= cm_base + 0x42f0, 0); - hws[IMX8MP_CLK_NAND_ROOT] =3D imx_clk_hw_gate2_shared2("nand_root_clk", "= nand", ccm_base + 0x4300, 0, &share_count_nand); - hws[IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK] =3D imx_clk_hw_gate2_shared2("= nand_usdhc_rawnand_clk", "nand_usdhc_bus", ccm_base + 0x4300, 0, &share_cou= nt_nand); - hws[IMX8MP_CLK_I2C5_ROOT] =3D imx_clk_hw_gate2("i2c5_root_clk", "i2c5", c= cm_base + 0x4330, 0); - hws[IMX8MP_CLK_I2C6_ROOT] =3D imx_clk_hw_gate2("i2c6_root_clk", "i2c6", c= cm_base + 0x4340, 0); - hws[IMX8MP_CLK_CAN1_ROOT] =3D imx_clk_hw_gate2("can1_root_clk", "can1", c= cm_base + 0x4350, 0); - hws[IMX8MP_CLK_CAN2_ROOT] =3D imx_clk_hw_gate2("can2_root_clk", "can2", c= cm_base + 0x4360, 0); - hws[IMX8MP_CLK_SDMA1_ROOT] =3D imx_clk_hw_gate4("sdma1_root_clk", "ipg_ro= ot", ccm_base + 0x43a0, 0); - hws[IMX8MP_CLK_SIM_ENET_ROOT] =3D imx_clk_hw_gate4("sim_enet_root_clk", "= enet_axi", ccm_base + 0x4400, 0); - hws[IMX8MP_CLK_ENET_QOS_ROOT] =3D imx_clk_hw_gate4("enet_qos_root_clk", "= sim_enet_root_clk", ccm_base + 0x43b0, 0); - hws[IMX8MP_CLK_GPU2D_ROOT] =3D imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_= core", ccm_base + 0x4450, 0); - hws[IMX8MP_CLK_GPU3D_ROOT] =3D imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_= core", ccm_base + 0x4460, 0); - hws[IMX8MP_CLK_UART1_ROOT] =3D imx_clk_hw_gate4("uart1_root_clk", "uart1"= , ccm_base + 0x4490, 0); - hws[IMX8MP_CLK_UART2_ROOT] =3D imx_clk_hw_gate4("uart2_root_clk", "uart2"= , ccm_base + 0x44a0, 0); - hws[IMX8MP_CLK_UART3_ROOT] =3D imx_clk_hw_gate4("uart3_root_clk", "uart3"= , ccm_base + 0x44b0, 0); - hws[IMX8MP_CLK_UART4_ROOT] =3D imx_clk_hw_gate4("uart4_root_clk", "uart4"= , ccm_base + 0x44c0, 0); - hws[IMX8MP_CLK_USB_ROOT] =3D imx_clk_hw_gate2_shared2("usb_root_clk", "hs= io_axi", ccm_base + 0x44d0, 0, &share_count_usb); - hws[IMX8MP_CLK_USB_SUSP] =3D imx_clk_hw_gate2_shared2("usb_suspend_clk", = "osc_32k", ccm_base + 0x44d0, 0, &share_count_usb); - hws[IMX8MP_CLK_USB_PHY_ROOT] =3D imx_clk_hw_gate4("usb_phy_root_clk", "us= b_phy_ref", ccm_base + 0x44f0, 0); - hws[IMX8MP_CLK_USDHC1_ROOT] =3D imx_clk_hw_gate4("usdhc1_root_clk", "usdh= c1", ccm_base + 0x4510, 0); - hws[IMX8MP_CLK_USDHC2_ROOT] =3D imx_clk_hw_gate4("usdhc2_root_clk", "usdh= c2", ccm_base + 0x4520, 0); - hws[IMX8MP_CLK_WDOG1_ROOT] =3D imx_clk_hw_gate4("wdog1_root_clk", "wdog",= ccm_base + 0x4530, 0); - hws[IMX8MP_CLK_WDOG2_ROOT] =3D imx_clk_hw_gate4("wdog2_root_clk", "wdog",= ccm_base + 0x4540, 0); - hws[IMX8MP_CLK_WDOG3_ROOT] =3D imx_clk_hw_gate4("wdog3_root_clk", "wdog",= ccm_base + 0x4550, 0); - hws[IMX8MP_CLK_VPU_G1_ROOT] =3D imx_clk_hw_gate4("vpu_g1_root_clk", "vpu_= g1", ccm_base + 0x4560, 0); - hws[IMX8MP_CLK_GPU_ROOT] =3D imx_clk_hw_gate4("gpu_root_clk", "gpu_axi", = ccm_base + 0x4570, 0); - hws[IMX8MP_CLK_VPU_VC8KE_ROOT] =3D imx_clk_hw_gate4("vpu_vc8ke_root_clk",= "vpu_vc8000e", ccm_base + 0x4590, 0); - hws[IMX8MP_CLK_VPU_G2_ROOT] =3D imx_clk_hw_gate4("vpu_g2_root_clk", "vpu_= g2", ccm_base + 0x45a0, 0); - hws[IMX8MP_CLK_NPU_ROOT] =3D imx_clk_hw_gate4("npu_root_clk", "ml_core", = ccm_base + 0x45b0, 0); - hws[IMX8MP_CLK_HSIO_ROOT] =3D imx_clk_hw_gate4("hsio_root_clk", "ipg_root= ", ccm_base + 0x45c0, 0); - hws[IMX8MP_CLK_MEDIA_APB_ROOT] =3D imx_clk_hw_gate2_shared2("media_apb_ro= ot_clk", "media_apb", ccm_base + 0x45d0, 0, &share_count_media); - hws[IMX8MP_CLK_MEDIA_AXI_ROOT] =3D imx_clk_hw_gate2_shared2("media_axi_ro= ot_clk", "media_axi", ccm_base + 0x45d0, 0, &share_count_media); - hws[IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT] =3D imx_clk_hw_gate2_shared2("media_c= am1_pix_root_clk", "media_cam1_pix", ccm_base + 0x45d0, 0, &share_count_med= ia); - hws[IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT] =3D imx_clk_hw_gate2_shared2("media_c= am2_pix_root_clk", "media_cam2_pix", ccm_base + 0x45d0, 0, &share_count_med= ia); - hws[IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT] =3D imx_clk_hw_gate2_shared2("media_= disp1_pix_root_clk", "media_disp1_pix", ccm_base + 0x45d0, 0, &share_count_= media); - hws[IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT] =3D imx_clk_hw_gate2_shared2("media_= disp2_pix_root_clk", "media_disp2_pix", ccm_base + 0x45d0, 0, &share_count_= media); - hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT] =3D imx_clk_hw_gate2_shared2("me= dia_mipi_phy1_ref_root", "media_mipi_phy1_ref", ccm_base + 0x45d0, 0, &shar= e_count_media); - hws[IMX8MP_CLK_MEDIA_LDB_ROOT] =3D imx_clk_hw_gate2_shared2("media_ldb_ro= ot_clk", "media_ldb", ccm_base + 0x45d0, 0, &share_count_media); - hws[IMX8MP_CLK_MEDIA_ISP_ROOT] =3D imx_clk_hw_gate2_shared2("media_isp_ro= ot_clk", "media_isp", ccm_base + 0x45d0, 0, &share_count_media); - - hws[IMX8MP_CLK_USDHC3_ROOT] =3D imx_clk_hw_gate4("usdhc3_root_clk", "usdh= c3", ccm_base + 0x45e0, 0); - hws[IMX8MP_CLK_HDMI_ROOT] =3D imx_clk_hw_gate4("hdmi_root_clk", "hdmi_axi= ", ccm_base + 0x45f0, 0); - hws[IMX8MP_CLK_TSENSOR_ROOT] =3D imx_clk_hw_gate4("tsensor_root_clk", "ip= g_root", ccm_base + 0x4620, 0); - hws[IMX8MP_CLK_VPU_ROOT] =3D imx_clk_hw_gate4("vpu_root_clk", "vpu_bus", = ccm_base + 0x4630, 0); - - hws[IMX8MP_CLK_AUDIO_AHB_ROOT] =3D imx_clk_hw_gate2_shared2("audio_ahb_ro= ot", "audio_ahb", ccm_base + 0x4650, 0, &share_count_audio); - hws[IMX8MP_CLK_AUDIO_AXI_ROOT] =3D imx_clk_hw_gate2_shared2("audio_axi_ro= ot", "audio_axi", ccm_base + 0x4650, 0, &share_count_audio); - hws[IMX8MP_CLK_SAI1_ROOT] =3D imx_clk_hw_gate2_shared2("sai1_root", "sai1= ", ccm_base + 0x4650, 0, &share_count_audio); - hws[IMX8MP_CLK_SAI2_ROOT] =3D imx_clk_hw_gate2_shared2("sai2_root", "sai2= ", ccm_base + 0x4650, 0, &share_count_audio); - hws[IMX8MP_CLK_SAI3_ROOT] =3D imx_clk_hw_gate2_shared2("sai3_root", "sai3= ", ccm_base + 0x4650, 0, &share_count_audio); - hws[IMX8MP_CLK_SAI5_ROOT] =3D imx_clk_hw_gate2_shared2("sai5_root", "sai5= ", ccm_base + 0x4650, 0, &share_count_audio); - hws[IMX8MP_CLK_SAI6_ROOT] =3D imx_clk_hw_gate2_shared2("sai6_root", "sai6= ", ccm_base + 0x4650, 0, &share_count_audio); - hws[IMX8MP_CLK_SAI7_ROOT] =3D imx_clk_hw_gate2_shared2("sai7_root", "sai7= ", ccm_base + 0x4650, 0, &share_count_audio); - hws[IMX8MP_CLK_PDM_ROOT] =3D imx_clk_hw_gate2_shared2("pdm_root", "pdm", = ccm_base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_DRAM_CORE] =3D imx_clk_hw_mux2_flags("dram_core_clk", base= + 0x9800, 24, 1, imx8mp_dram_core_sels, ARRAY_SIZE(imx8mp_dram_core_sels),= CLK_IS_CRITICAL); + + hws[IMX8MP_CLK_DRAM1_ROOT] =3D imx_clk_hw_gate4_flags("dram1_root_clk", "= dram_core_clk", base + 0x4050, 0, CLK_IS_CRITICAL); + hws[IMX8MP_CLK_ECSPI1_ROOT] =3D imx_clk_hw_gate4("ecspi1_root_clk", "ecsp= i1", base + 0x4070, 0); + hws[IMX8MP_CLK_ECSPI2_ROOT] =3D imx_clk_hw_gate4("ecspi2_root_clk", "ecsp= i2", base + 0x4080, 0); + hws[IMX8MP_CLK_ECSPI3_ROOT] =3D imx_clk_hw_gate4("ecspi3_root_clk", "ecsp= i3", base + 0x4090, 0); + hws[IMX8MP_CLK_ENET1_ROOT] =3D imx_clk_hw_gate4("enet1_root_clk", "enet_a= xi", base + 0x40a0, 0); + hws[IMX8MP_CLK_GPIO1_ROOT] =3D imx_clk_hw_gate4("gpio1_root_clk", "ipg_ro= ot", base + 0x40b0, 0); + hws[IMX8MP_CLK_GPIO2_ROOT] =3D imx_clk_hw_gate4("gpio2_root_clk", "ipg_ro= ot", base + 0x40c0, 0); + hws[IMX8MP_CLK_GPIO3_ROOT] =3D imx_clk_hw_gate4("gpio3_root_clk", "ipg_ro= ot", base + 0x40d0, 0); + hws[IMX8MP_CLK_GPIO4_ROOT] =3D imx_clk_hw_gate4("gpio4_root_clk", "ipg_ro= ot", base + 0x40e0, 0); + hws[IMX8MP_CLK_GPIO5_ROOT] =3D imx_clk_hw_gate4("gpio5_root_clk", "ipg_ro= ot", base + 0x40f0, 0); + hws[IMX8MP_CLK_GPT1_ROOT] =3D imx_clk_hw_gate4("gpt1_root_clk", "gpt1", b= ase + 0x4100, 0); + hws[IMX8MP_CLK_GPT2_ROOT] =3D imx_clk_hw_gate4("gpt2_root_clk", "gpt2", b= ase + 0x4110, 0); + hws[IMX8MP_CLK_GPT3_ROOT] =3D imx_clk_hw_gate4("gpt3_root_clk", "gpt3", b= ase + 0x4120, 0); + hws[IMX8MP_CLK_GPT4_ROOT] =3D imx_clk_hw_gate4("gpt4_root_clk", "gpt4", b= ase + 0x4130, 0); + hws[IMX8MP_CLK_GPT5_ROOT] =3D imx_clk_hw_gate4("gpt5_root_clk", "gpt5", b= ase + 0x4140, 0); + hws[IMX8MP_CLK_GPT6_ROOT] =3D imx_clk_hw_gate4("gpt6_root_clk", "gpt6", b= ase + 0x4150, 0); + hws[IMX8MP_CLK_I2C1_ROOT] =3D imx_clk_hw_gate4("i2c1_root_clk", "i2c1", b= ase + 0x4170, 0); + hws[IMX8MP_CLK_I2C2_ROOT] =3D imx_clk_hw_gate4("i2c2_root_clk", "i2c2", b= ase + 0x4180, 0); + hws[IMX8MP_CLK_I2C3_ROOT] =3D imx_clk_hw_gate4("i2c3_root_clk", "i2c3", b= ase + 0x4190, 0); + hws[IMX8MP_CLK_I2C4_ROOT] =3D imx_clk_hw_gate4("i2c4_root_clk", "i2c4", b= ase + 0x41a0, 0); + hws[IMX8MP_CLK_MU_ROOT] =3D imx_clk_hw_gate4("mu_root_clk", "ipg_root", b= ase + 0x4210, 0); + hws[IMX8MP_CLK_OCOTP_ROOT] =3D imx_clk_hw_gate4("ocotp_root_clk", "ipg_ro= ot", base + 0x4220, 0); + hws[IMX8MP_CLK_PCIE_ROOT] =3D imx_clk_hw_gate4("pcie_root_clk", "pcie_aux= ", base + 0x4250, 0); + hws[IMX8MP_CLK_PWM1_ROOT] =3D imx_clk_hw_gate4("pwm1_root_clk", "pwm1", b= ase + 0x4280, 0); + hws[IMX8MP_CLK_PWM2_ROOT] =3D imx_clk_hw_gate4("pwm2_root_clk", "pwm2", b= ase + 0x4290, 0); + hws[IMX8MP_CLK_PWM3_ROOT] =3D imx_clk_hw_gate4("pwm3_root_clk", "pwm3", b= ase + 0x42a0, 0); + hws[IMX8MP_CLK_PWM4_ROOT] =3D imx_clk_hw_gate4("pwm4_root_clk", "pwm4", b= ase + 0x42b0, 0); + hws[IMX8MP_CLK_QOS_ROOT] =3D imx_clk_hw_gate4("qos_root_clk", "ipg_root",= base + 0x42c0, 0); + hws[IMX8MP_CLK_QOS_ENET_ROOT] =3D imx_clk_hw_gate4("qos_enet_root_clk", "= ipg_root", base + 0x42e0, 0); + hws[IMX8MP_CLK_QSPI_ROOT] =3D imx_clk_hw_gate4("qspi_root_clk", "qspi", b= ase + 0x42f0, 0); + hws[IMX8MP_CLK_NAND_ROOT] =3D imx_clk_hw_gate2_shared2("nand_root_clk", "= nand", base + 0x4300, 0, &share_count_nand); + hws[IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK] =3D imx_clk_hw_gate2_shared2("= nand_usdhc_rawnand_clk", "nand_usdhc_bus", base + 0x4300, 0, &share_count_n= and); + hws[IMX8MP_CLK_I2C5_ROOT] =3D imx_clk_hw_gate2("i2c5_root_clk", "i2c5", b= ase + 0x4330, 0); + hws[IMX8MP_CLK_I2C6_ROOT] =3D imx_clk_hw_gate2("i2c6_root_clk", "i2c6", b= ase + 0x4340, 0); + hws[IMX8MP_CLK_CAN1_ROOT] =3D imx_clk_hw_gate2("can1_root_clk", "can1", b= ase + 0x4350, 0); + hws[IMX8MP_CLK_CAN2_ROOT] =3D imx_clk_hw_gate2("can2_root_clk", "can2", b= ase + 0x4360, 0); + hws[IMX8MP_CLK_SDMA1_ROOT] =3D imx_clk_hw_gate4("sdma1_root_clk", "ipg_ro= ot", base + 0x43a0, 0); + hws[IMX8MP_CLK_SIM_ENET_ROOT] =3D imx_clk_hw_gate4("sim_enet_root_clk", "= enet_axi", base + 0x4400, 0); + hws[IMX8MP_CLK_ENET_QOS_ROOT] =3D imx_clk_hw_gate4("enet_qos_root_clk", "= sim_enet_root_clk", base + 0x43b0, 0); + hws[IMX8MP_CLK_GPU2D_ROOT] =3D imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_= core", base + 0x4450, 0); + hws[IMX8MP_CLK_GPU3D_ROOT] =3D imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_= core", base + 0x4460, 0); + hws[IMX8MP_CLK_UART1_ROOT] =3D imx_clk_hw_gate4("uart1_root_clk", "uart1"= , base + 0x4490, 0); + hws[IMX8MP_CLK_UART2_ROOT] =3D imx_clk_hw_gate4("uart2_root_clk", "uart2"= , base + 0x44a0, 0); + hws[IMX8MP_CLK_UART3_ROOT] =3D imx_clk_hw_gate4("uart3_root_clk", "uart3"= , base + 0x44b0, 0); + hws[IMX8MP_CLK_UART4_ROOT] =3D imx_clk_hw_gate4("uart4_root_clk", "uart4"= , base + 0x44c0, 0); + hws[IMX8MP_CLK_USB_ROOT] =3D imx_clk_hw_gate2_shared2("usb_root_clk", "hs= io_axi", base + 0x44d0, 0, &share_count_usb); + hws[IMX8MP_CLK_USB_SUSP] =3D imx_clk_hw_gate2_shared2("usb_suspend_clk", = "osc_32k", base + 0x44d0, 0, &share_count_usb); + hws[IMX8MP_CLK_USB_PHY_ROOT] =3D imx_clk_hw_gate4("usb_phy_root_clk", "us= b_phy_ref", base + 0x44f0, 0); + hws[IMX8MP_CLK_USDHC1_ROOT] =3D imx_clk_hw_gate4("usdhc1_root_clk", "usdh= c1", base + 0x4510, 0); + hws[IMX8MP_CLK_USDHC2_ROOT] =3D imx_clk_hw_gate4("usdhc2_root_clk", "usdh= c2", base + 0x4520, 0); + hws[IMX8MP_CLK_WDOG1_ROOT] =3D imx_clk_hw_gate4("wdog1_root_clk", "wdog",= base + 0x4530, 0); + hws[IMX8MP_CLK_WDOG2_ROOT] =3D imx_clk_hw_gate4("wdog2_root_clk", "wdog",= base + 0x4540, 0); + hws[IMX8MP_CLK_WDOG3_ROOT] =3D imx_clk_hw_gate4("wdog3_root_clk", "wdog",= base + 0x4550, 0); + hws[IMX8MP_CLK_VPU_G1_ROOT] =3D imx_clk_hw_gate4("vpu_g1_root_clk", "vpu_= g1", base + 0x4560, 0); + hws[IMX8MP_CLK_GPU_ROOT] =3D imx_clk_hw_gate4("gpu_root_clk", "gpu_axi", = base + 0x4570, 0); + hws[IMX8MP_CLK_VPU_VC8KE_ROOT] =3D imx_clk_hw_gate4("vpu_vc8ke_root_clk",= "vpu_vc8000e", base + 0x4590, 0); + hws[IMX8MP_CLK_VPU_G2_ROOT] =3D imx_clk_hw_gate4("vpu_g2_root_clk", "vpu_= g2", base + 0x45a0, 0); + hws[IMX8MP_CLK_NPU_ROOT] =3D imx_clk_hw_gate4("npu_root_clk", "ml_core", = base + 0x45b0, 0); + hws[IMX8MP_CLK_HSIO_ROOT] =3D imx_clk_hw_gate4("hsio_root_clk", "ipg_root= ", base + 0x45c0, 0); + hws[IMX8MP_CLK_MEDIA_APB_ROOT] =3D imx_clk_hw_gate2_shared2("media_apb_ro= ot_clk", "media_apb", base + 0x45d0, 0, &share_count_media); + hws[IMX8MP_CLK_MEDIA_AXI_ROOT] =3D imx_clk_hw_gate2_shared2("media_axi_ro= ot_clk", "media_axi", base + 0x45d0, 0, &share_count_media); + hws[IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT] =3D imx_clk_hw_gate2_shared2("media_c= am1_pix_root_clk", "media_cam1_pix", base + 0x45d0, 0, &share_count_media); + hws[IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT] =3D imx_clk_hw_gate2_shared2("media_c= am2_pix_root_clk", "media_cam2_pix", base + 0x45d0, 0, &share_count_media); + hws[IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT] =3D imx_clk_hw_gate2_shared2("media_= disp1_pix_root_clk", "media_disp1_pix", base + 0x45d0, 0, &share_count_medi= a); + hws[IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT] =3D imx_clk_hw_gate2_shared2("media_= disp2_pix_root_clk", "media_disp2_pix", base + 0x45d0, 0, &share_count_medi= a); + hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT] =3D imx_clk_hw_gate2_shared2("me= dia_mipi_phy1_ref_root", "media_mipi_phy1_ref", base + 0x45d0, 0, &share_co= unt_media); + hws[IMX8MP_CLK_MEDIA_LDB_ROOT] =3D imx_clk_hw_gate2_shared2("media_ldb_ro= ot_clk", "media_ldb", base + 0x45d0, 0, &share_count_media); + hws[IMX8MP_CLK_MEDIA_ISP_ROOT] =3D imx_clk_hw_gate2_shared2("media_isp_ro= ot_clk", "media_isp", base + 0x45d0, 0, &share_count_media); + + hws[IMX8MP_CLK_USDHC3_ROOT] =3D imx_clk_hw_gate4("usdhc3_root_clk", "usdh= c3", base + 0x45e0, 0); + hws[IMX8MP_CLK_HDMI_ROOT] =3D imx_clk_hw_gate4("hdmi_root_clk", "hdmi_axi= ", base + 0x45f0, 0); + hws[IMX8MP_CLK_TSENSOR_ROOT] =3D imx_clk_hw_gate4("tsensor_root_clk", "ip= g_root", base + 0x4620, 0); + hws[IMX8MP_CLK_VPU_ROOT] =3D imx_clk_hw_gate4("vpu_root_clk", "vpu_bus", = base + 0x4630, 0); + + hws[IMX8MP_CLK_AUDIO_AHB_ROOT] =3D imx_clk_hw_gate2_shared2("audio_ahb_ro= ot", "audio_ahb", base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_AUDIO_AXI_ROOT] =3D imx_clk_hw_gate2_shared2("audio_axi_ro= ot", "audio_axi", base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI1_ROOT] =3D imx_clk_hw_gate2_shared2("sai1_root", "sai1= ", base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI2_ROOT] =3D imx_clk_hw_gate2_shared2("sai2_root", "sai2= ", base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI3_ROOT] =3D imx_clk_hw_gate2_shared2("sai3_root", "sai3= ", base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI5_ROOT] =3D imx_clk_hw_gate2_shared2("sai5_root", "sai5= ", base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI6_ROOT] =3D imx_clk_hw_gate2_shared2("sai6_root", "sai6= ", base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_SAI7_ROOT] =3D imx_clk_hw_gate2_shared2("sai7_root", "sai7= ", base + 0x4650, 0, &share_count_audio); + hws[IMX8MP_CLK_PDM_ROOT] =3D imx_clk_hw_gate2_shared2("pdm_root", "pdm", = base + 0x4650, 0, &share_count_audio); =20 hws[IMX8MP_CLK_ARM] =3D imx_clk_hw_cpu("arm", "arm_a53_core", hws[IMX8MP_CLK_A53_CORE]->clk, --=20 2.43.0