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([2.196.40.29]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-acb6ef9e7e6sm745234366b.162.2025.04.22.23.03.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 23:03:12 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Abel Vesa , Peng Fan , Stephen Boyd , Shawn Guo , Dario Binacchi , Fabio Estevam , Michael Turquette , Pengutronix Kernel Team , Sascha Hauer , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH v11 11/18] clk: imx: add support for i.MX8MM anatop clock driver Date: Wed, 23 Apr 2025 08:02:28 +0200 Message-ID: <20250423060241.95521-12-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250423060241.95521-1-dario.binacchi@amarulasolutions.com> References: <20250423060241.95521-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support NXP i.MX8M anatop PLL module which generates PLLs to CCM root. By doing so, we also simplify the CCM driver code. The changes are backward compatible. Signed-off-by: Dario Binacchi Reviewed-by: Peng Fan --- Changes in v11: - Add 'Reviewed-by' tag of Peng Fan drivers/clk/imx/Makefile | 2 +- drivers/clk/imx/clk-imx8mm-anatop.c | 287 ++++++++++++++++++++++++++++ drivers/clk/imx/clk-imx8mm.c | 172 ++++++++--------- 3 files changed, 367 insertions(+), 94 deletions(-) create mode 100644 drivers/clk/imx/clk-imx8mm-anatop.c diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 03f2b2a1ab63..bf35b1236591 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -25,7 +25,7 @@ mxc-clk-objs +=3D clk-sscg-pll.o mxc-clk-objs +=3D clk-gpr-mux.o obj-$(CONFIG_MXC_CLK) +=3D mxc-clk.o =20 -obj-$(CONFIG_CLK_IMX8MM) +=3D clk-imx8mm.o +obj-$(CONFIG_CLK_IMX8MM) +=3D clk-imx8mm-anatop.o clk-imx8mm.o obj-$(CONFIG_CLK_IMX8MN) +=3D clk-imx8mn.o obj-$(CONFIG_CLK_IMX8MP) +=3D clk-imx8mp.o clk-imx8mp-audiomix.o obj-$(CONFIG_CLK_IMX8MQ) +=3D clk-imx8mq.o diff --git a/drivers/clk/imx/clk-imx8mm-anatop.c b/drivers/clk/imx/clk-imx8= mm-anatop.c new file mode 100644 index 000000000000..4ac870df6370 --- /dev/null +++ b/drivers/clk/imx/clk-imx8mm-anatop.c @@ -0,0 +1,287 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * clk-imx8mm-anatop.c - NXP i.MX8MM anatop clock driver + * + * Copyright (c) 2025 Dario Binacchi + */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +#define IMX8MM_ANATOP_CLK_END (IMX8MM_ANATOP_CLK_CLKOUT2 + 1) + +static const char * const pll_ref_sels[] =3D { "osc_24m", "dummy", "dummy"= , "dummy", }; +static const char * const audio_pll1_bypass_sels[] =3D {"audio_pll1", "aud= io_pll1_ref_sel", }; +static const char * const audio_pll2_bypass_sels[] =3D {"audio_pll2", "aud= io_pll2_ref_sel", }; +static const char * const video_pll_bypass_sels[] =3D {"video_pll", "video= _pll_ref_sel", }; +static const char * const dram_pll_bypass_sels[] =3D {"dram_pll", "dram_pl= l_ref_sel", }; +static const char * const gpu_pll_bypass_sels[] =3D {"gpu_pll", "gpu_pll_r= ef_sel", }; +static const char * const vpu_pll_bypass_sels[] =3D {"vpu_pll", "vpu_pll_r= ef_sel", }; +static const char * const arm_pll_bypass_sels[] =3D {"arm_pll", "arm_pll_r= ef_sel", }; +static const char * const sys_pll3_bypass_sels[] =3D {"sys_pll3", "sys_pll= 3_ref_sel", }; +static const char * const clkout_sels[] =3D {"audio_pll1_out", "audio_pll2= _out", "video_pll_out", + "dummy", "dummy", "gpu_pll_out", "vpu_pll_out", + "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", + "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; + +static struct clk_hw_onecell_data *clk_hw_data; +static struct clk_hw **hws; + +static int imx8mm_anatop_clocks_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + void __iomem *base; + int ret; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) { + dev_err(dev, "failed to get base address\n"); + return PTR_ERR(base); + } + + clk_hw_data =3D devm_kzalloc(dev, struct_size(clk_hw_data, hws, + IMX8MM_ANATOP_CLK_END), + GFP_KERNEL); + if (WARN_ON(!clk_hw_data)) + return -ENOMEM; + + clk_hw_data->num =3D IMX8MM_ANATOP_CLK_END; + hws =3D clk_hw_data->hws; + + hws[IMX8MM_ANATOP_CLK_DUMMY] =3D imx_clk_hw_fixed("dummy", 0); + hws[IMX8MM_ANATOP_CLK_32K] =3D imx_get_clk_hw_by_name(np, "osc_32k"); + hws[IMX8MM_ANATOP_CLK_24M] =3D imx_get_clk_hw_by_name(np, "osc_24m"); + + hws[IMX8MM_ANATOP_AUDIO_PLL1_REF_SEL] =3D + imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_ANATOP_AUDIO_PLL2_REF_SEL] =3D + imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_ANATOP_VIDEO_PLL_REF_SEL] =3D + imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_ANATOP_DRAM_PLL_REF_SEL] =3D + imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_ANATOP_GPU_PLL_REF_SEL] =3D + imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_ANATOP_VPU_PLL_REF_SEL] =3D + imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_ANATOP_ARM_PLL_REF_SEL] =3D + imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + hws[IMX8MM_ANATOP_SYS_PLL3_REF_SEL] =3D + imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, + pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); + + hws[IMX8MM_ANATOP_AUDIO_PLL1] =3D + imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", + base, &imx_1443x_pll); + hws[IMX8MM_ANATOP_AUDIO_PLL2] =3D + imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", + base + 0x14, &imx_1443x_pll); + hws[IMX8MM_ANATOP_VIDEO_PLL] =3D + imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", + base + 0x28, &imx_1443x_pll); + hws[IMX8MM_ANATOP_DRAM_PLL] =3D + imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", + base + 0x50, &imx_1443x_dram_pll); + hws[IMX8MM_ANATOP_GPU_PLL] =3D + imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", + base + 0x64, &imx_1416x_pll); + hws[IMX8MM_ANATOP_VPU_PLL] =3D + imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", + base + 0x74, &imx_1416x_pll); + hws[IMX8MM_ANATOP_ARM_PLL] =3D + imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", + base + 0x84, &imx_1416x_pll); + hws[IMX8MM_ANATOP_SYS_PLL1] =3D imx_clk_hw_fixed("sys_pll1", 800000000); + hws[IMX8MM_ANATOP_SYS_PLL2] =3D imx_clk_hw_fixed("sys_pll2", 1000000000); + hws[IMX8MM_ANATOP_SYS_PLL3] =3D + imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", + base + 0x114, &imx_1416x_pll); + + /* PLL bypass out */ + hws[IMX8MM_ANATOP_AUDIO_PLL1_BYPASS] =3D + imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, + audio_pll1_bypass_sels, + ARRAY_SIZE(audio_pll1_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MM_ANATOP_AUDIO_PLL2_BYPASS] =3D + imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, + audio_pll2_bypass_sels, + ARRAY_SIZE(audio_pll2_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MM_ANATOP_VIDEO_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1, + video_pll_bypass_sels, + ARRAY_SIZE(video_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MM_ANATOP_DRAM_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, + dram_pll_bypass_sels, + ARRAY_SIZE(dram_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MM_ANATOP_GPU_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, + gpu_pll_bypass_sels, + ARRAY_SIZE(gpu_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MM_ANATOP_VPU_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1, + vpu_pll_bypass_sels, + ARRAY_SIZE(vpu_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MM_ANATOP_ARM_PLL_BYPASS] =3D + imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, + arm_pll_bypass_sels, + ARRAY_SIZE(arm_pll_bypass_sels), + CLK_SET_RATE_PARENT); + hws[IMX8MM_ANATOP_SYS_PLL3_BYPASS] =3D + imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, + sys_pll3_bypass_sels, + ARRAY_SIZE(sys_pll3_bypass_sels), + CLK_SET_RATE_PARENT); + + /* PLL out gate */ + hws[IMX8MM_ANATOP_AUDIO_PLL1_OUT] =3D + imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", + base, 13); + hws[IMX8MM_ANATOP_AUDIO_PLL2_OUT] =3D + imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", + base + 0x14, 13); + hws[IMX8MM_ANATOP_VIDEO_PLL_OUT] =3D + imx_clk_hw_gate("video_pll_out", "video_pll_bypass", + base + 0x28, 13); + hws[IMX8MM_ANATOP_DRAM_PLL_OUT] =3D + imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", + base + 0x50, 13); + hws[IMX8MM_ANATOP_GPU_PLL_OUT] =3D + imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", + base + 0x64, 11); + hws[IMX8MM_ANATOP_VPU_PLL_OUT] =3D + imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", + base + 0x74, 11); + hws[IMX8MM_ANATOP_ARM_PLL_OUT] =3D + imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", + base + 0x84, 11); + hws[IMX8MM_ANATOP_SYS_PLL3_OUT] =3D + imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", + base + 0x114, 11); + + /* SYS PLL1 fixed output */ + hws[IMX8MM_ANATOP_SYS_PLL1_OUT] =3D + imx_clk_hw_gate("sys_pll1_out", "sys_pll1", + base + 0x94, 11); + + hws[IMX8MM_ANATOP_SYS_PLL1_40M] =3D + imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); + hws[IMX8MM_ANATOP_SYS_PLL1_80M] =3D + imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10); + hws[IMX8MM_ANATOP_SYS_PLL1_100M] =3D + imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8); + hws[IMX8MM_ANATOP_SYS_PLL1_133M] =3D + imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6); + hws[IMX8MM_ANATOP_SYS_PLL1_160M] =3D + imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5); + hws[IMX8MM_ANATOP_SYS_PLL1_200M] =3D + imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4); + hws[IMX8MM_ANATOP_SYS_PLL1_266M] =3D + imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3); + hws[IMX8MM_ANATOP_SYS_PLL1_400M] =3D + imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2); + hws[IMX8MM_ANATOP_SYS_PLL1_800M] =3D + imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1); + + /* SYS PLL2 fixed output */ + hws[IMX8MM_ANATOP_SYS_PLL2_OUT] =3D + imx_clk_hw_gate("sys_pll2_out", "sys_pll2", + base + 0x104, 11); + + hws[IMX8MM_ANATOP_SYS_PLL2_50M] =3D + imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20); + hws[IMX8MM_ANATOP_SYS_PLL2_100M] =3D + imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10); + hws[IMX8MM_ANATOP_SYS_PLL2_125M] =3D + imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8); + hws[IMX8MM_ANATOP_SYS_PLL2_166M] =3D + imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6); + hws[IMX8MM_ANATOP_SYS_PLL2_200M] =3D + imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5); + hws[IMX8MM_ANATOP_SYS_PLL2_250M] =3D + imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4); + hws[IMX8MM_ANATOP_SYS_PLL2_333M] =3D + imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3); + hws[IMX8MM_ANATOP_SYS_PLL2_500M] =3D + imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); + hws[IMX8MM_ANATOP_SYS_PLL2_1000M] =3D + imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); + + hws[IMX8MM_ANATOP_CLK_CLKOUT1_SEL] =3D + imx_clk_hw_mux2("clkout1_sel", base + 0x128, 4, 4, + clkout_sels, ARRAY_SIZE(clkout_sels)); + hws[IMX8MM_ANATOP_CLK_CLKOUT1_DIV] =3D + imx_clk_hw_divider("clkout1_div", "clkout1_sel", + base + 0x128, 0, 4); + hws[IMX8MM_ANATOP_CLK_CLKOUT1] =3D + imx_clk_hw_gate("clkout1", "clkout1_div", base + 0x128, 8); + hws[IMX8MM_ANATOP_CLK_CLKOUT2_SEL] =3D + imx_clk_hw_mux2("clkout2_sel", base + 0x128, 20, 4, + clkout_sels, ARRAY_SIZE(clkout_sels)); + hws[IMX8MM_ANATOP_CLK_CLKOUT2_DIV] =3D + imx_clk_hw_divider("clkout2_div", "clkout2_sel", base + 0x128, + 16, 4); + hws[IMX8MM_ANATOP_CLK_CLKOUT2] =3D + imx_clk_hw_gate("clkout2", "clkout2_div", base + 0x128, 24); + + imx_check_clk_hws(hws, IMX8MM_ANATOP_CLK_END); + + ret =3D of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); + if (ret < 0) { + imx_unregister_hw_clocks(hws, IMX8MM_ANATOP_CLK_END); + return dev_err_probe(dev, ret, + "failed to register anatop clock provider\n"); + } + + dev_info(dev, "NXP i.MX8MM anatop clock driver probed\n"); + return 0; +} + +static const struct of_device_id imx8mm_anatop_clk_of_match[] =3D { + { .compatible =3D "fsl,imx8mm-anatop" }, + { /* Sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, imx8mm_anatop_clk_of_match); + +static struct platform_driver imx8mm_anatop_clk_driver =3D { + .probe =3D imx8mm_anatop_clocks_probe, + .driver =3D { + .name =3D "imx8mm-anatop", + /* + * Disable bind attributes: clocks are not removed and + * reloading the driver will crash or break devices. + */ + .suppress_bind_attrs =3D true, + .of_match_table =3D imx8mm_anatop_clk_of_match, + }, +}; + +module_platform_driver(imx8mm_anatop_clk_driver); + +MODULE_AUTHOR("Dario Binacchi "); +MODULE_DESCRIPTION("NXP i.MX8MM anatop clock driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index 8a1fc7e17ba2..d39de0a81a6f 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -25,16 +25,6 @@ static u32 share_count_disp; static u32 share_count_pdm; static u32 share_count_nand; =20 -static const char *pll_ref_sels[] =3D { "osc_24m", "dummy", "dummy", "dumm= y", }; -static const char *audio_pll1_bypass_sels[] =3D {"audio_pll1", "audio_pll1= _ref_sel", }; -static const char *audio_pll2_bypass_sels[] =3D {"audio_pll2", "audio_pll2= _ref_sel", }; -static const char *video_pll_bypass_sels[] =3D {"video_pll", "video_pll_re= f_sel", }; -static const char *dram_pll_bypass_sels[] =3D {"dram_pll", "dram_pll_ref_s= el", }; -static const char *gpu_pll_bypass_sels[] =3D {"gpu_pll", "gpu_pll_ref_sel"= , }; -static const char *vpu_pll_bypass_sels[] =3D {"vpu_pll", "vpu_pll_ref_sel"= , }; -static const char *arm_pll_bypass_sels[] =3D {"arm_pll", "arm_pll_ref_sel"= , }; -static const char *sys_pll3_bypass_sels[] =3D {"sys_pll3", "sys_pll3_ref_s= el", }; - /* CCM ROOT */ static const char *imx8mm_a53_sels[] =3D {"osc_24m", "arm_pll_out", "sys_p= ll2_500m", "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", }; @@ -288,21 +278,20 @@ static const char *imx8mm_clko1_sels[] =3D {"osc_24m"= , "sys_pll1_800m", "dummy", " static const char *imx8mm_clko2_sels[] =3D {"osc_24m", "sys_pll2_200m", "s= ys_pll1_400m", "sys_pll2_166m", "sys_pll3_out", "audio_pll1_out", "video_pll_out", "osc_32k", }; =20 -static const char * const clkout_sels[] =3D {"audio_pll1_out", "audio_pll2= _out", "video_pll_out", - "dummy", "dummy", "gpu_pll_out", "vpu_pll_out", - "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", - "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; - static struct clk_hw_onecell_data *clk_hw_data; static struct clk_hw **hws; =20 static int imx8mm_clocks_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; - struct device_node *np =3D dev->of_node; + struct device_node *np =3D dev->of_node, *anp; void __iomem *base; int ret; =20 + base =3D devm_platform_ioremap_resource(pdev, 0); + if (WARN_ON(IS_ERR(base))) + return PTR_ERR(base); + clk_hw_data =3D kzalloc(struct_size(clk_hw_data, hws, IMX8MM_CLK_END), GFP_KERNEL); if (WARN_ON(!clk_hw_data)) @@ -311,96 +300,92 @@ static int imx8mm_clocks_probe(struct platform_device= *pdev) clk_hw_data->num =3D IMX8MM_CLK_END; hws =3D clk_hw_data->hws; =20 - hws[IMX8MM_CLK_DUMMY] =3D imx_clk_hw_fixed("dummy", 0); - hws[IMX8MM_CLK_24M] =3D imx_get_clk_hw_by_name(np, "osc_24m"); - hws[IMX8MM_CLK_32K] =3D imx_get_clk_hw_by_name(np, "osc_32k"); + anp =3D of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop"); + if (!anp) + return dev_err_probe(dev, -ENODEV, "missing anatop\n"); + + of_node_put(anp); + + hws[IMX8MM_CLK_DUMMY] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_DU= MMY); + hws[IMX8MM_CLK_24M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_24M); + hws[IMX8MM_CLK_32K] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_32K); hws[IMX8MM_CLK_EXT1] =3D imx_get_clk_hw_by_name(np, "clk_ext1"); hws[IMX8MM_CLK_EXT2] =3D imx_get_clk_hw_by_name(np, "clk_ext2"); hws[IMX8MM_CLK_EXT3] =3D imx_get_clk_hw_by_name(np, "clk_ext3"); hws[IMX8MM_CLK_EXT4] =3D imx_get_clk_hw_by_name(np, "clk_ext4"); =20 - np =3D of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop"); - base =3D of_iomap(np, 0); - of_node_put(np); - if (WARN_ON(!base)) - return -ENOMEM; - - hws[IMX8MM_AUDIO_PLL1_REF_SEL] =3D imx_clk_hw_mux("audio_pll1_ref_sel", b= ase + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_AUDIO_PLL2_REF_SEL] =3D imx_clk_hw_mux("audio_pll2_ref_sel", b= ase + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_VIDEO_PLL_REF_SEL] =3D imx_clk_hw_mux("video_pll_ref_sel", bas= e + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_DRAM_PLL_REF_SEL] =3D imx_clk_hw_mux("dram_pll_ref_sel", base = + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_GPU_PLL_REF_SEL] =3D imx_clk_hw_mux("gpu_pll_ref_sel", base + = 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_VPU_PLL_REF_SEL] =3D imx_clk_hw_mux("vpu_pll_ref_sel", base + = 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_ARM_PLL_REF_SEL] =3D imx_clk_hw_mux("arm_pll_ref_sel", base + = 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMX8MM_SYS_PLL3_REF_SEL] =3D imx_clk_hw_mux("sys_pll3_ref_sel", base = + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - - hws[IMX8MM_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_r= ef_sel", base, &imx_1443x_pll); - hws[IMX8MM_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_r= ef_sel", base + 0x14, &imx_1443x_pll); - hws[IMX8MM_VIDEO_PLL] =3D imx_clk_hw_pll14xx("video_pll", "video_pll_ref_= sel", base + 0x28, &imx_1443x_pll); - hws[IMX8MM_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel= ", base + 0x50, &imx_1443x_dram_pll); - hws[IMX8MM_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", = base + 0x64, &imx_1416x_pll); - hws[IMX8MM_VPU_PLL] =3D imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", = base + 0x74, &imx_1416x_pll); - hws[IMX8MM_ARM_PLL] =3D imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", = base + 0x84, &imx_1416x_pll); - hws[IMX8MM_SYS_PLL1] =3D imx_clk_hw_fixed("sys_pll1", 800000000); - hws[IMX8MM_SYS_PLL2] =3D imx_clk_hw_fixed("sys_pll2", 1000000000); - hws[IMX8MM_SYS_PLL3] =3D imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel= ", base + 0x114, &imx_1416x_pll); + hws[IMX8MM_AUDIO_PLL1_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANAT= OP_AUDIO_PLL1_REF_SEL); + hws[IMX8MM_AUDIO_PLL2_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANAT= OP_AUDIO_PLL2_REF_SEL); + hws[IMX8MM_VIDEO_PLL_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATO= P_VIDEO_PLL_REF_SEL); + hws[IMX8MM_DRAM_PLL_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP= _DRAM_PLL_REF_SEL); + hws[IMX8MM_GPU_PLL_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_= GPU_PLL_REF_SEL); + hws[IMX8MM_VPU_PLL_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_= VPU_PLL_REF_SEL); + hws[IMX8MM_ARM_PLL_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_= ARM_PLL_REF_SEL); + hws[IMX8MM_SYS_PLL3_REF_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP= _SYS_PLL3_REF_SEL); + + hws[IMX8MM_AUDIO_PLL1] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_AUDIO= _PLL1); + hws[IMX8MM_AUDIO_PLL2] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_AUDIO= _PLL2); + hws[IMX8MM_VIDEO_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VIDEO_= PLL); + hws[IMX8MM_DRAM_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_DRAM_PL= L); + hws[IMX8MM_GPU_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_GPU_PLL); + hws[IMX8MM_VPU_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VPU_PLL); + hws[IMX8MM_ARM_PLL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_ARM_PLL); + hws[IMX8MM_SYS_PLL1] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL= 1); + hws[IMX8MM_SYS_PLL2] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL= 2); + hws[IMX8MM_SYS_PLL3] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS_PLL= 3); =20 /* PLL bypass out */ - hws[IMX8MM_AUDIO_PLL1_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll1_bypass= ", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels),= CLK_SET_RATE_PARENT); - hws[IMX8MM_AUDIO_PLL2_BYPASS] =3D imx_clk_hw_mux_flags("audio_pll2_bypass= ", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass= _sels), CLK_SET_RATE_PARENT); - hws[IMX8MM_VIDEO_PLL_BYPASS] =3D imx_clk_hw_mux_flags("video_pll_bypass",= base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sel= s), CLK_SET_RATE_PARENT); - hws[IMX8MM_DRAM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("dram_pll_bypass", b= ase + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), = CLK_SET_RATE_PARENT); - hws[IMX8MM_GPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("gpu_pll_bypass", bas= e + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_= SET_RATE_PARENT); - hws[IMX8MM_VPU_PLL_BYPASS] =3D imx_clk_hw_mux_flags("vpu_pll_bypass", bas= e + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_= SET_RATE_PARENT); - hws[IMX8MM_ARM_PLL_BYPASS] =3D imx_clk_hw_mux_flags("arm_pll_bypass", bas= e + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_= SET_RATE_PARENT); - hws[IMX8MM_SYS_PLL3_BYPASS] =3D imx_clk_hw_mux_flags("sys_pll3_bypass", b= ase + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels),= CLK_SET_RATE_PARENT); + hws[IMX8MM_AUDIO_PLL1_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATO= P_AUDIO_PLL1_BYPASS); + hws[IMX8MM_AUDIO_PLL2_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATO= P_AUDIO_PLL2_BYPASS); + hws[IMX8MM_VIDEO_PLL_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP= _VIDEO_PLL_BYPASS); + hws[IMX8MM_DRAM_PLL_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_= DRAM_PLL_BYPASS); + hws[IMX8MM_GPU_PLL_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_G= PU_PLL_BYPASS); + hws[IMX8MM_VPU_PLL_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_V= PU_PLL_BYPASS); + hws[IMX8MM_ARM_PLL_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_A= RM_PLL_BYPASS); + hws[IMX8MM_SYS_PLL3_BYPASS] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_= SYS_PLL3_BYPASS); =20 /* PLL out gate */ - hws[IMX8MM_AUDIO_PLL1_OUT] =3D imx_clk_hw_gate("audio_pll1_out", "audio_p= ll1_bypass", base, 13); - hws[IMX8MM_AUDIO_PLL2_OUT] =3D imx_clk_hw_gate("audio_pll2_out", "audio_p= ll2_bypass", base + 0x14, 13); - hws[IMX8MM_VIDEO_PLL_OUT] =3D imx_clk_hw_gate("video_pll_out", "video_pll= _bypass", base + 0x28, 13); - hws[IMX8MM_DRAM_PLL_OUT] =3D imx_clk_hw_gate("dram_pll_out", "dram_pll_by= pass", base + 0x50, 13); - hws[IMX8MM_GPU_PLL_OUT] =3D imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypas= s", base + 0x64, 11); - hws[IMX8MM_VPU_PLL_OUT] =3D imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypas= s", base + 0x74, 11); - hws[IMX8MM_ARM_PLL_OUT] =3D imx_clk_hw_gate("arm_pll_out", "arm_pll_bypas= s", base + 0x84, 11); - hws[IMX8MM_SYS_PLL3_OUT] =3D imx_clk_hw_gate("sys_pll3_out", "sys_pll3_by= pass", base + 0x114, 11); + hws[IMX8MM_AUDIO_PLL1_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_A= UDIO_PLL1_OUT); + hws[IMX8MM_AUDIO_PLL2_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_A= UDIO_PLL2_OUT); + hws[IMX8MM_VIDEO_PLL_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VI= DEO_PLL_OUT); + hws[IMX8MM_DRAM_PLL_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_DRA= M_PLL_OUT); + hws[IMX8MM_GPU_PLL_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_GPU_= PLL_OUT); + hws[IMX8MM_VPU_PLL_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_VPU_= PLL_OUT); + hws[IMX8MM_ARM_PLL_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_ARM_= PLL_OUT); + hws[IMX8MM_SYS_PLL3_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS= _PLL3_OUT); =20 /* SYS PLL1 fixed output */ - hws[IMX8MM_SYS_PLL1_OUT] =3D imx_clk_hw_gate("sys_pll1_out", "sys_pll1", = base + 0x94, 11); - - hws[IMX8MM_SYS_PLL1_40M] =3D imx_clk_hw_fixed_factor("sys_pll1_40m", "sys= _pll1_out", 1, 20); - hws[IMX8MM_SYS_PLL1_80M] =3D imx_clk_hw_fixed_factor("sys_pll1_80m", "sys= _pll1_out", 1, 10); - hws[IMX8MM_SYS_PLL1_100M] =3D imx_clk_hw_fixed_factor("sys_pll1_100m", "s= ys_pll1_out", 1, 8); - hws[IMX8MM_SYS_PLL1_133M] =3D imx_clk_hw_fixed_factor("sys_pll1_133m", "s= ys_pll1_out", 1, 6); - hws[IMX8MM_SYS_PLL1_160M] =3D imx_clk_hw_fixed_factor("sys_pll1_160m", "s= ys_pll1_out", 1, 5); - hws[IMX8MM_SYS_PLL1_200M] =3D imx_clk_hw_fixed_factor("sys_pll1_200m", "s= ys_pll1_out", 1, 4); - hws[IMX8MM_SYS_PLL1_266M] =3D imx_clk_hw_fixed_factor("sys_pll1_266m", "s= ys_pll1_out", 1, 3); - hws[IMX8MM_SYS_PLL1_400M] =3D imx_clk_hw_fixed_factor("sys_pll1_400m", "s= ys_pll1_out", 1, 2); - hws[IMX8MM_SYS_PLL1_800M] =3D imx_clk_hw_fixed_factor("sys_pll1_800m", "s= ys_pll1_out", 1, 1); + hws[IMX8MM_SYS_PLL1_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS= _PLL1_OUT); + + hws[IMX8MM_SYS_PLL1_40M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS= _PLL1_40M); + hws[IMX8MM_SYS_PLL1_80M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS= _PLL1_80M); + hws[IMX8MM_SYS_PLL1_100M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL1_100M); + hws[IMX8MM_SYS_PLL1_133M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL1_133M); + hws[IMX8MM_SYS_PLL1_160M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL1_160M); + hws[IMX8MM_SYS_PLL1_200M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL1_200M); + hws[IMX8MM_SYS_PLL1_266M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL1_266M); + hws[IMX8MM_SYS_PLL1_400M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL1_400M); + hws[IMX8MM_SYS_PLL1_800M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL1_800M); =20 /* SYS PLL2 fixed output */ - hws[IMX8MM_SYS_PLL2_OUT] =3D imx_clk_hw_gate("sys_pll2_out", "sys_pll2", = base + 0x104, 11); - hws[IMX8MM_SYS_PLL2_50M] =3D imx_clk_hw_fixed_factor("sys_pll2_50m", "sys= _pll2_out", 1, 20); - hws[IMX8MM_SYS_PLL2_100M] =3D imx_clk_hw_fixed_factor("sys_pll2_100m", "s= ys_pll2_out", 1, 10); - hws[IMX8MM_SYS_PLL2_125M] =3D imx_clk_hw_fixed_factor("sys_pll2_125m", "s= ys_pll2_out", 1, 8); - hws[IMX8MM_SYS_PLL2_166M] =3D imx_clk_hw_fixed_factor("sys_pll2_166m", "s= ys_pll2_out", 1, 6); - hws[IMX8MM_SYS_PLL2_200M] =3D imx_clk_hw_fixed_factor("sys_pll2_200m", "s= ys_pll2_out", 1, 5); - hws[IMX8MM_SYS_PLL2_250M] =3D imx_clk_hw_fixed_factor("sys_pll2_250m", "s= ys_pll2_out", 1, 4); - hws[IMX8MM_SYS_PLL2_333M] =3D imx_clk_hw_fixed_factor("sys_pll2_333m", "s= ys_pll2_out", 1, 3); - hws[IMX8MM_SYS_PLL2_500M] =3D imx_clk_hw_fixed_factor("sys_pll2_500m", "s= ys_pll2_out", 1, 2); - hws[IMX8MM_SYS_PLL2_1000M] =3D imx_clk_hw_fixed_factor("sys_pll2_1000m", = "sys_pll2_out", 1, 1); - - hws[IMX8MM_CLK_CLKOUT1_SEL] =3D imx_clk_hw_mux2("clkout1_sel", base + 0x1= 28, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels)); - hws[IMX8MM_CLK_CLKOUT1_DIV] =3D imx_clk_hw_divider("clkout1_div", "clkout= 1_sel", base + 0x128, 0, 4); - hws[IMX8MM_CLK_CLKOUT1] =3D imx_clk_hw_gate("clkout1", "clkout1_div", bas= e + 0x128, 8); - hws[IMX8MM_CLK_CLKOUT2_SEL] =3D imx_clk_hw_mux2("clkout2_sel", base + 0x1= 28, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels)); - hws[IMX8MM_CLK_CLKOUT2_DIV] =3D imx_clk_hw_divider("clkout2_div", "clkout= 2_sel", base + 0x128, 16, 4); - hws[IMX8MM_CLK_CLKOUT2] =3D imx_clk_hw_gate("clkout2", "clkout2_div", bas= e + 0x128, 24); - - np =3D dev->of_node; - base =3D devm_platform_ioremap_resource(pdev, 0); - if (WARN_ON(IS_ERR(base))) - return PTR_ERR(base); + hws[IMX8MM_SYS_PLL2_OUT] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS= _PLL2_OUT); + + hws[IMX8MM_SYS_PLL2_50M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SYS= _PLL2_50M); + hws[IMX8MM_SYS_PLL2_100M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL2_100M); + hws[IMX8MM_SYS_PLL2_125M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL2_125M); + hws[IMX8MM_SYS_PLL2_166M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL2_166M); + hws[IMX8MM_SYS_PLL2_200M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL2_200M); + hws[IMX8MM_SYS_PLL2_250M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL2_250M); + hws[IMX8MM_SYS_PLL2_333M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL2_333M); + hws[IMX8MM_SYS_PLL2_500M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_SY= S_PLL2_500M); + hws[IMX8MM_SYS_PLL2_1000M] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_S= YS_PLL2_1000M); + + hws[IMX8MM_CLK_CLKOUT1_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_= CLK_CLKOUT1_SEL); + hws[IMX8MM_CLK_CLKOUT1_DIV] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_= CLK_CLKOUT1_DIV); + hws[IMX8MM_CLK_CLKOUT1] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_= CLKOUT1); + hws[IMX8MM_CLK_CLKOUT2_SEL] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_= CLK_CLKOUT2_SEL); + hws[IMX8MM_CLK_CLKOUT2_DIV] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_= CLK_CLKOUT2_DIV); + hws[IMX8MM_CLK_CLKOUT2] =3D imx_anatop_get_clk_hw(anp, IMX8MM_ANATOP_CLK_= CLKOUT2); =20 /* Core Slice */ hws[IMX8MM_CLK_A53_DIV] =3D imx8m_clk_hw_composite_core("arm_a53_div", im= x8mm_a53_sels, base + 0x8000); @@ -611,6 +596,7 @@ static int imx8mm_clocks_probe(struct platform_device *= pdev) =20 imx_register_uart_clocks(); =20 + dev_info(dev, "NXP i.MX8MM ccm clock driver probed\n"); return 0; =20 unregister_hws: --=20 2.43.0