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Wed, 23 Apr 2025 05:59:01 -0700 (PDT) Received: from [127.0.1.1] ([62.231.96.41]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-acb6ef426c4sm794377966b.131.2025.04.23.05.59.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Apr 2025 05:59:00 -0700 (PDT) From: Abel Vesa Date: Wed, 23 Apr 2025 15:58:52 +0300 Subject: [PATCH] arm64: dts: qcom: x1e80100: Add GFX power domain to GPU clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250423-x1e80100-add-gpucc-gfx-pd-v1-1-677d97f61963@linaro.org> X-B4-Tracking: v=1; b=H4sIAAvkCGgC/x3MPQrDMAxA4asEzRVIzg+hVykdjCU7WhJj02IIu XtMxm9474SqxbTCezih6N+qHXsHvwYIm9+Tokk3OHIzTW7ExroSE6EXwZR/IWCKDbOgn1nHGJ0 sytD7XDRae96f73XdscwmEGsAAAA= X-Change-ID: 20250423-x1e80100-add-gpucc-gfx-pd-a51e3ff2d6e1 To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold , stable@vger.kernel.org, Abel Vesa X-Mailer: b4 0.15-dev-dedf8 X-Developer-Signature: v=1; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE According to documentation, the VDD_GFX is powering up the whole GPU subsystem. The VDD_GFX is routed through the RPMh GFX power domain. So tie the RPMh GFX power domain to the GPU clock controller. Cc: stable@vger.kernel.org # 6.11 Fixes: 721e38301b79 ("arm64: dts: qcom: x1e80100: Add gpu support") Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index 46b79fce92c90d969e3de48bc88e27915d1592bb..96d5ab3c426639b0c0af2458d12= 7e3bbbe41c556 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3873,6 +3873,7 @@ gpucc: clock-controller@3d90000 { clocks =3D <&bi_tcxo_div2>, <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>; + power-domains =3D <&rpmhpd RPMHPD_GFX>; #clock-cells =3D <1>; #reset-cells =3D <1>; #power-domain-cells =3D <1>; --- base-commit: 2c9c612abeb38aab0e87d48496de6fd6daafb00b change-id: 20250423-x1e80100-add-gpucc-gfx-pd-a51e3ff2d6e1 Best regards, --=20 Abel Vesa