From nobody Tue Feb 10 00:24:07 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4474A1FFC4B; Tue, 22 Apr 2025 23:13:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745363590; cv=none; b=mo+mMBeTQ3eRLjT0zdWQ0+L4yxk4ksotdcT5Mz7dumV8OSVcm+R2YPqm3/U77kMyQXBtnmSxGS2Rj92ddxGlttgXC8ecazeANRHnesKV47G9kOK+sZ+CktPA8sP72/m2DJtZZSVu0SS72djNjWnwKXxTChsAC2fDotHATs1kzpc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745363590; c=relaxed/simple; bh=X2dc1RoW35+p5vXAXItk3NA5tz5VGr0iGZ5O3gbucG4=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=jwlRk0X2gxJNxiqpkLVJZB/F+/1KWTQtW7PyMrd9hEkOh13E207HQpFixssWwxh3MnPrPXLtDAvy19TOhNGej8NqOtX4UzQq/lLEwxjbISBQ2GMaq9JWSA+lbQHQYAbR+/uOJ53kVoceLuocyiykelhlZTCzcppy+AKv/qhYvug= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=CvqZJSmI; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="CvqZJSmI" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 53MKpqYH014555; Tue, 22 Apr 2025 23:12:57 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=qcppdkim1; bh=c7zhYrQc3lYtB09eAqSejS TtSPghl3ph37nLptiyKwY=; b=CvqZJSmIF9KSvE/PjNqvY326FBkVNknDAxR+Xj 1eXVf8DAJsUkft7m9D/LO07N1nKoEy3LlZ3lz9VMBH/xbxsLqaiXqSZgVl3yzMY8 fFICoXsZdhAvV5l/xiE+2X4D+OIDL0Db8NpNLWFAZkwzhQ+4yGrxUtgD+h45Hojo HkEld1/B/G8txtJ78hykRb3dF5GY0o4BRhxn0Lc5DAdw33LeCoszZ1rrSv1EENFr Y7pTkU89R9wkkdIyuE7o4z39egPnc37A0BOBZZoBCgyU/+1N3PgGvOVwsQy0uaes 4QHBGFqnC/5h3x/Tx4KXPdkQLtTtYd/T6abY75mZO3y1E7bg== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 466jgy08bb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 22 Apr 2025 23:12:56 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 53MNCt9L003783 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 22 Apr 2025 23:12:55 GMT Received: from hu-djaggi-lv.qualcomm.com (10.49.16.6) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 22 Apr 2025 16:12:54 -0700 From: Deepti Jaggi To: , , , , , CC: , , , , , Shazad Hussain Subject: [PATCH v3] arm64: dts: qcom: add initial support for qcom sa8255p-ride Date: Tue, 22 Apr 2025 16:12:49 -0700 Message-ID: <20250422231249.871995-1-quic_djaggi@quicinc.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDIyMDE3NCBTYWx0ZWRfX1uh9hfW8ONYG vSAfosAaLHFpVv5MwWvMFBuKyykN+C8ebbEYq/e9erLkixbHLObwmMzBe74IlNVzXVpG15b0FVw pgCcbEoRZD/8J5Cc0q2799d/9gqp7fUDLnUjm1YpBZZXaTBpmkxVWW60qRtJNkkPyNu6aUtrhPm mekxW7ISE4x/V07CPMdarCzaYPFElNyd2a7Qs5xwucM8O/oi4P4PeKFTRfLgs70REjyt5anwPBV GSuktdcbPJqDzppcAdqUYT4ow9Mz+m/Q2eKxy1HYxK3BqOC+k8qayFZUmJhFjIdPCkIAjom32Du PoRUyNYmliBou+Wp5JWOlies8/OSRikQ/z4iqwwZ/Nd4aUDHnfHl2CgABXyjbqDKetu3+lN+I2q mZiTqc9HmFOlaNu2C0qegI4my+5YS6mm19+cFlGlwJCVxGPu6Ldti9mzyQTSQzeRnQvPFSKz X-Proofpoint-GUID: djSy0RG1lbSnljVmDD03BaAyrAawCTEE X-Proofpoint-ORIG-GUID: djSy0RG1lbSnljVmDD03BaAyrAawCTEE X-Authority-Analysis: v=2.4 cv=M5VNKzws c=1 sm=1 tr=0 ts=68082278 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=3H110R4YSZwA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=N4VItbOPVz7apOv8ffUA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-22_11,2025-04-22_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 priorityscore=1501 mlxscore=0 mlxlogscore=999 malwarescore=0 impostorscore=0 clxscore=1011 suspectscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504220174 Content-Type: text/plain; charset="utf-8" From: Nikunj Kela This adds basic support for the Qualcomm sa8255p platform and the reference board: sa8255p-ride. The dt files describe the basics of the SoC and enable booting to shell with ramdisk. The Qualcomm automotive sa8255p SoC utilizes firmware to configure platform resources such as clocks, interconnects, and TLMM. Device drivers request these resources through the SCMI power and performance protocols. The SCMI platform supports resource aggregation and handles parallel requests from agents, with each driver having a dedicated SCMI channel for communication. Co-developed-by: Shazad Hussain Signed-off-by: Shazad Hussain Signed-off-by: Nikunj Kela Signed-off-by: Deepti Jaggi --- This patch is dependent on [2] for booting to shell and DT bindings. Changes in v3: Removed the patches from original series [1]. Added arm,max-msg and arm,max-msg-size DT property in scmi nodes. Changed max-rx-timeout-ms to arm,max-rx-timeout-ms in scmi nodes. Updated commit text. Reordered range property for qupv3_id_0, qupv3_id_1 and qupv3_id_3 = nodes. Reordered vendor property(#qcom,sensors) for tsens* nodes. Changed cache labels to lower case. Removed unused i2c,spi and tlmm nodes. Updated reserved memory nodes. Changes in v2: Removed scmichannels label and alias Modified scmi node name to conform to schema Moved status property to be the last one in scmi instances Changed to lower case for cpu labels Added fallback compatible for tlmm node [1]: https://lore.kernel.org/all/20240903220240.2594102-1-quic_nkela@quicin= c.com/ [2]: https://lore.kernel.org/all/20250418151235.27787-1-quic_ptalari@quicin= c.com/ --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi | 80 + arch/arm64/boot/dts/qcom/sa8255p-ride.dts | 94 + arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi | 2440 +++++++++++++++++++ arch/arm64/boot/dts/qcom/sa8255p.dtsi | 2075 ++++++++++++++++ 5 files changed, 4690 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-ride.dts create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi create mode 100644 arch/arm64/boot/dts/qcom/sa8255p.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index adb4d026bcc4..7437e51e5849 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -134,6 +134,7 @@ qrb5165-rb5-vision-mezzanine-dtbs :=3D qrb5165-rb5.dtb = qrb5165-rb5-vision-mezzanin dtb-$(CONFIG_ARCH_QCOM) +=3D qrb5165-rb5-vision-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qru1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sa8155p-adp.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D sa8255p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sa8540p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sa8775p-ride.dtb diff --git a/arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi b/arch/arm64/boot/= dts/qcom/sa8255p-pmics.dtsi new file mode 100644 index 000000000000..b00c2b05cef7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights re= served. + */ + +/ { + thermal-zones { + pmm8654au_0_thermal: pm8255-0-thermal { + polling-delay-passive =3D <100>; + + trips { + trip0 { + temperature =3D <105000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + pmm8654au_1_thermal: pm8255-1-thermal { + polling-delay-passive =3D <100>; + + trips { + trip0 { + temperature =3D <105000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + pmm8654au_2_thermal: pm8255-2-thermal { + polling-delay-passive =3D <100>; + + trips { + trip0 { + temperature =3D <105000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + pmm8654au_3_thermal: pm8255-3-thermal { + polling-delay-passive =3D <100>; + + trips { + trip0 { + temperature =3D <105000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <125000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sa8255p-ride.dts b/arch/arm64/boot/dt= s/qcom/sa8255p-ride.dts new file mode 100644 index 000000000000..cb866f897d0a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8255p-ride.dts @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights res= erved. + */ + +/dts-v1/; + +#include + +#include "sa8255p.dtsi" +#include "sa8255p-pmics.dtsi" +#include "sa8255p-scmi.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. SA8255P Ride"; + compatible =3D "qcom,sa8255p-ride", "qcom,sa8255p"; + + aliases { + serial0 =3D &uart10; + serial1 =3D &uart4; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&adreno_smmu { + power-domains =3D <&scmi15_pd 0>; + + status =3D "okay"; +}; + +&gpll0_board_clk { + clock-frequency =3D <300000000>; +}; + +&pmm8654au_0_thermal { + thermal-sensors =3D <&scmi23_sensor 0>; +}; + +&pmm8654au_1_thermal { + thermal-sensors =3D <&scmi23_sensor 1>; +}; + +&pmm8654au_2_thermal { + thermal-sensors =3D <&scmi23_sensor 2>; +}; + +&pmm8654au_3_thermal { + thermal-sensors =3D <&scmi23_sensor 3>; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&scmi11 { + status =3D "okay"; +}; + +&scmi15 { + status =3D "okay"; +}; + +&scmi23 { + status =3D "okay"; +}; + +&sleep_clk { + clock-frequency =3D <32000>; +}; + +&uart4 { + power-domains =3D <&scmi11_pd 4>, <&scmi11_dvfs 4>; + power-domain-names =3D "power", "perf"; + + status =3D "okay"; +}; + +&uart10 { + power-domains =3D <&scmi11_pd 10>, <&scmi11_dvfs 10>; + power-domain-names =3D "power", "perf"; + + status =3D "okay"; +}; + +&xo_board_clk { + clock-frequency =3D <38400000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi b/arch/arm64/boot/d= ts/qcom/sa8255p-scmi.dtsi new file mode 100644 index 000000000000..589bb09f027b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi @@ -0,0 +1,2440 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights res= erved. + */ + +#include + +&firmware { + scmi0: scmi-0 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem0>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi0_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi0_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi0_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi1: scmi-1 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem1>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi1_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi1_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi1_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi2: scmi-2 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem2>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi2_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi2_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi2_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi3: scmi-3 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem3>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi3_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi3_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi3_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi4: scmi-4 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem4>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi4_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi4_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi4_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi5: scmi-5 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem5>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi5_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi5_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi5_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi6: scmi-6 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem6>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi6_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi6_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi6_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi7: scmi-7 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem7>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi7_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi7_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi7_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi8: scmi-8 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem8>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi8_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi8_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi8_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi9: scmi-9 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem9>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi9_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi9_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi9_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi10: scmi-10 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem10>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi10_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi10_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi10_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi11: scmi-11 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem11>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi11_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi11_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi11_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi12: scmi-12 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem12>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi12_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi12_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi12_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi13: scmi-13 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem13>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi13_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi13_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi13_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi14: scmi-14 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem14>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi14_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi14_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi14_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi15: scmi-15 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem15>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi15_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi15_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi15_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi16: scmi-16 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem16>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi16_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi16_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi16_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi17: scmi-17 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem17>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi17_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi17_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi17_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi18: scmi-18 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem18>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi18_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi18_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi18_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi19: scmi-19 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem19>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi19_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi19_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi19_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi20: scmi-20 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem20>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi20_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi20_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi20_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi21: scmi-21 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem21>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi21_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi21_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi21_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi22: scmi-22 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem22>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi22_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi22_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi22_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi23: scmi-23 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem23>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi23_sensor: protocol@15 { + reg =3D <0x15>; + #thermal-sensor-cells =3D <1>; + }; + }; + + scmi24: scmi-24 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem24>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi24_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi24_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi24_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi25: scmi-25 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem25>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi25_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi25_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi25_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi26: scmi-26 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem26>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi26_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi26_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi26_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi27: scmi-27 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem27>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi27_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi27_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi27_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi28: scmi-28 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem28>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi28_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi28_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi28_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi29: scmi-29 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem29>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi29_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi29_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi29_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi30: scmi-30 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem30>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi30_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi30_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi30_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi31: scmi-31 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem31>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi31_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi31_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi31_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi32: scmi-32 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem32>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi32_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi32_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi32_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi33: scmi-33 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem33>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi33_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi33_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi33_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi34: scmi-34 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem34>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi34_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi34_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi34_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi35: scmi-35 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem35>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi35_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi35_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi35_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi36: scmi-36 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem36>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi36_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi36_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi36_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi37: scmi-37 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem37>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi37_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi37_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi37_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi38: scmi-38 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem38>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi38_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi38_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi38_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi39: scmi-39 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem39>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi39_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi39_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi39_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi40: scmi-40 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem40>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi40_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi40_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi40_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi41: scmi-41 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem41>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi41_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi41_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi41_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi42: scmi-42 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem42>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi42_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi42_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi42_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi43: scmi-43 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem43>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi43_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi43_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi43_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi44: scmi-44 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem44>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi44_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi44_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi44_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi45: scmi-45 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem45>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi45_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi45_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi45_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi46: scmi-46 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem46>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi46_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi46_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi46_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi47: scmi-47 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem47>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi47_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi47_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi47_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi48: scmi-48 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem48>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi48_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi48_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi48_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi49: scmi-49 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem49>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi49_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi49_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi49_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi50: scmi-50 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem50>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi50_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi50_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi50_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi51: scmi-51 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem51>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi51_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi51_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi51_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi52: scmi-52 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem52>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi52_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi52_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi52_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi53: scmi-53 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem53>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi53_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi53_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi53_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi54: scmi-54 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem54>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi54_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi54_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi54_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi55: scmi-55 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem55>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi55_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi55_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi55_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi56: scmi-56 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem56>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi56_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi56_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi56_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi57: scmi-57 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem57>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi57_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi57_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi57_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi58: scmi-58 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem58>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi58_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi58_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi58_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi59: scmi-59 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem59>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi59_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi59_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi59_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi60: scmi-60 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem60>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi60_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi60_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi60_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi61: scmi-61 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem61>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi61_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi61_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi61_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi62: scmi-62 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem62>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi62_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi62_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi62_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; + + scmi63: scmi-63 { + compatible =3D "qcom,scmi-smc"; + arm,smc-id =3D <0xc6008012>; + shmem =3D <&shmem63>; + + interrupts =3D ; + interrupt-names =3D "a2p"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + arm,max-msg =3D <10>; + arm,max-msg-size =3D <256>; + arm,max-rx-timeout-ms =3D <3000>; + + status =3D "disabled"; + + scmi63_pd: protocol@11 { + reg =3D <0x11>; + #power-domain-cells =3D <1>; + }; + + scmi63_dvfs: protocol@13 { + reg =3D <0x13>; + #power-domain-cells =3D <1>; + }; + + scmi63_rst: protocol@16 { + reg =3D <0x16>; + #reset-cells =3D <1>; + }; + }; +}; + +&soc { + sram@d0000000 { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "mmio-sram"; + reg =3D <0x0 0xd0000000 0x0 0x40000>; + ranges =3D <0x0 0x0 0x0 0xffffffff>; + + shmem0: scmi-sram@d0000000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0000000 0x1000>; + }; + + shmem1: scmi-sram@d0001000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0001000 0x1000>; + }; + + shmem2: scmi-sram@d0002000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0002000 0x1000>; + }; + + shmem3: scmi-sram@d0003000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0003000 0x1000>; + }; + + shmem4: scmi-sram@d0004000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0004000 0x1000>; + }; + + shmem5: scmi-sram@d0005000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0005000 0x1000>; + }; + + shmem6: scmi-sram@d0006000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0006000 0x1000>; + }; + + shmem7: scmi-sram@d0007000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0007000 0x1000>; + }; + + shmem8: scmi-sram@d0008000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0008000 0x1000>; + }; + + shmem9: scmi-sram@d0009000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0009000 0x1000>; + }; + + shmem10: scmi-sram@d000a000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd000a000 0x1000>; + }; + + shmem11: scmi-sram@d000b000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd000b000 0x1000>; + }; + + shmem12: scmi-sram@d000c000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd000c000 0x1000>; + }; + + shmem13: scmi-sram@d000d000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd000d000 0x1000>; + }; + + shmem14: scmi-sram@d000e000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd000e000 0x1000>; + }; + + shmem15: scmi-sram@d000f000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd000f000 0x1000>; + }; + + shmem16: scmi-sram@d0010000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0010000 0x1000>; + }; + + shmem17: scmi-sram@d0011000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0011000 0x1000>; + }; + + shmem18: scmi-sram@d0012000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0012000 0x1000>; + }; + + shmem19: scmi-sram@d0013000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0013000 0x1000>; + }; + + shmem20: scmi-sram@d0014000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0014000 0x1000>; + }; + + shmem21: scmi-sram@d0015000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0015000 0x1000>; + }; + + shmem22: scmi-sram@d0016000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0016000 0x1000>; + }; + + shmem23: scmi-sram@d0017000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0017000 0x1000>; + }; + + shmem24: scmi-sram@d0018000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0018000 0x1000>; + }; + + shmem25: scmi-sram@d0019000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0019000 0x1000>; + }; + + shmem26: scmi-sram@d001a000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd001a000 0x1000>; + }; + + shmem27: scmi-sram@d001b000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd001b000 0x1000>; + }; + + shmem28: scmi-sram@d001c000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd001c000 0x1000>; + }; + + shmem29: scmi-sram@d001d000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd001d000 0x1000>; + }; + + shmem30: scmi-sram@d001e000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd001e000 0x1000>; + }; + + shmem31: scmi-sram@d001f000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd001f000 0x1000>; + }; + + shmem32: scmi-sram@d0020000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0020000 0x1000>; + }; + + shmem33: scmi-sram@d0021000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0021000 0x1000>; + }; + + shmem34: scmi-sram@d0022000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0022000 0x1000>; + }; + + shmem35: scmi-sram@d0023000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0023000 0x1000>; + }; + + shmem36: scmi-sram@d0024000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0024000 0x1000>; + }; + + shmem37: scmi-sram@d0025000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0025000 0x1000>; + }; + + shmem38: scmi-sram@d0026000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0026000 0x1000>; + }; + + shmem39: scmi-sram@d0027000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0027000 0x1000>; + }; + + shmem40: scmi-sram@d0028000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0028000 0x1000>; + }; + + shmem41: scmi-sram@d0029000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0029000 0x1000>; + }; + + shmem42: scmi-sram@d002a000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd002a000 0x1000>; + }; + + shmem43: scmi-sram@d002b000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd002b000 0x1000>; + }; + + shmem44: scmi-sram@d002c000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd002c000 0x1000>; + }; + + shmem45: scmi-sram@d002d000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd002d000 0x1000>; + }; + + shmem46: scmi-sram@d002e000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd002e000 0x1000>; + }; + + shmem47: scmi-sram@d002f000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd002f000 0x1000>; + }; + + shmem48: scmi-sram@d0030000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0030000 0x1000>; + }; + + shmem49: scmi-sram@d0031000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0031000 0x1000>; + }; + + shmem50: scmi-sram@d0032000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0032000 0x1000>; + }; + + shmem51: scmi-sram@d0033000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0033000 0x1000>; + }; + + shmem52: scmi-sram@d0034000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0034000 0x1000>; + }; + + shmem53: scmi-sram@d0035000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0035000 0x1000>; + }; + + shmem54: scmi-sram@d0036000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0036000 0x1000>; + }; + + shmem55: scmi-sram@d0037000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0037000 0x1000>; + }; + + shmem56: scmi-sram@d0038000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0038000 0x1000>; + }; + + shmem57: scmi-sram@d0039000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd0039000 0x1000>; + }; + + shmem58: scmi-sram@d003a000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd003a000 0x1000>; + }; + + shmem59: scmi-sram@d003b000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd003b000 0x1000>; + }; + + shmem60: scmi-sram@d003c000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd003c000 0x1000>; + }; + + shmem61: scmi-sram@d003d000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd003d000 0x1000>; + }; + + shmem62: scmi-sram@d003e000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd003e000 0x1000>; + }; + + shmem63: scmi-sram@d003f000 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0xd003f000 0x1000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sa8255p.dtsi b/arch/arm64/boot/dts/qc= om/sa8255p.dtsi new file mode 100644 index 000000000000..bde94f8af8f7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8255p.dtsi @@ -0,0 +1,2075 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights res= erved. + */ + +#include +#include + +/ { + interrupt-parent =3D <&intc>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + clocks { + xo_board_clk: xo-board-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + gpll0_board_clk: gpll0-board-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + }; + + bi_tcxo_div2: bi-tcxo-div2-clk { + compatible =3D "fixed-factor-clock"; + clocks =3D <&xo_board_clk>; + clock-mult =3D <1>; + clock-div =3D <2>; + #clock-cells =3D <0>; + }; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 0>; + next-level-cache =3D <&l2_0>; + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + l3_0: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x100>; + enable-method =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 0>; + next-level-cache =3D <&l2_1>; + l2_1: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x200>; + enable-method =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 0>; + next-level-cache =3D <&l2_2>; + l2_2: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x300>; + enable-method =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 0>; + next-level-cache =3D <&l2_3>; + l2_3: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu4: cpu@10000 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x10000>; + enable-method =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 1>; + next-level-cache =3D <&l2_4>; + l2_4: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_1>; + l3_1: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-unified; + }; + + }; + }; + + cpu5: cpu@10100 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x10100>; + enable-method =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 1>; + next-level-cache =3D <&l2_5>; + l2_5: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_1>; + }; + }; + + cpu6: cpu@10200 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x10200>; + enable-method =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 1>; + next-level-cache =3D <&l2_6>; + l2_6: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_1>; + }; + }; + + cpu7: cpu@10300 { + device_type =3D "cpu"; + compatible =3D "qcom,kryo"; + reg =3D <0x0 0x10300>; + enable-method =3D "psci"; + qcom,freq-domain =3D <&cpufreq_hw 1>; + next-level-cache =3D <&l2_7>; + l2_7: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu4>; + }; + + core1 { + cpu =3D <&cpu5>; + }; + + core2 { + cpu =3D <&cpu6>; + }; + + core3 { + cpu =3D <&cpu7>; + }; + }; + }; + }; + + firmware: firmware { + scm { + compatible =3D "qcom,scm-sa8255p", "qcom,scm"; + memory-region =3D <&tz_ffi_mem>; + qcom,dload-mode =3D <&tcsr 0x13000>; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible =3D "arm,armv8-pmuv3"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + sail_ss_mem: sail-ss@80000000 { + reg =3D <0x0 0x80000000 0x0 0x10000000>; + no-map; + }; + + hyp_mem: hyp@90000000 { + reg =3D <0x0 0x90000000 0x0 0x600000>; + no-map; + }; + + xbl_boot_mem: xbl-boot@90700000 { + reg =3D <0x0 0x90700000 0x0 0x100000>; + no-map; + }; + + aop_image_mem: aop-image@90800000 { + reg =3D <0x0 0x90800000 0x0 0x60000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@90860000 { + compatible =3D "qcom,cmd-db"; + reg =3D <0x0 0x90860000 0x0 0x20000>; + no-map; + }; + + uefi_log: uefi-log@908b0000 { + reg =3D <0x0 0x908b0000 0x0 0x10000>; + no-map; + }; + + ddr_training_checksum: ddr-training-checksum@908c0000 { + reg =3D <0x0 0x908c0000 0x0 0x1000>; + no-map; + }; + + reserved_mem: reserved@908f0000 { + reg =3D <0x0 0x908f0000 0x0 0xe000>; + no-map; + }; + + secdata_apss_mem: secdata-apss@908fe000 { + reg =3D <0x0 0x908fe000 0x0 0x2000>; + no-map; + }; + + smem_mem: smem@90900000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x90900000 0x0 0x200000>; + no-map; + hwlocks =3D <&tcsr_mutex 3>; + }; + + tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 { + reg =3D <0x0 0x90c00000 0x0 0x100000>; + no-map; + }; + + sail_mailbox_mem: sail-ss@90d00000 { + reg =3D <0x0 0x90d00000 0x0 0x100000>; + no-map; + }; + + sail_ota_mem: sail-ss@90e00000 { + reg =3D <0x0 0x90e00000 0x0 0x300000>; + no-map; + }; + + hyp_md_mem: hyp-md@91a80000 { + no-map; + reg =3D <0x0 0x91a80000 0x0 0x80000>; + }; + + aoss_backup_mem: aoss-backup@91b00000 { + reg =3D <0x0 0x91b00000 0x0 0x40000>; + no-map; + }; + + cpucp_backup_mem: cpucp-backup@91b40000 { + reg =3D <0x0 0x91b40000 0x0 0x40000>; + no-map; + }; + + tz_config_backup_mem: tz-config-backup@91b80000 { + reg =3D <0x0 0x91b80000 0x0 0x10000>; + no-map; + }; + + ddr_training_data_mem: ddr-training-data@91b90000 { + reg =3D <0x0 0x91b90000 0x0 0x10000>; + no-map; + }; + + cdt_data_backup_mem: cdt-data-backup@91ba0000 { + reg =3D <0x0 0x91ba0000 0x0 0x1000>; + no-map; + }; + + tz_ffi_mem: tz-ffi@91c00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0x91c00000 0x0 0x1400000>; + no-map; + }; + + lpass_machine_learning_mem: lpass-machine-learning@93b00000 { + reg =3D <0x0 0x93b00000 0x0 0xf00000>; + no-map; + }; + + adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 { + reg =3D <0x0 0x94a00000 0x0 0x800000>; + no-map; + }; + + pil_camera_mem: pil-camera@95200000 { + reg =3D <0x0 0x95200000 0x0 0x500000>; + no-map; + }; + + pil_adsp_mem: pil-adsp@95c00000 { + reg =3D <0x0 0x95c00000 0x0 0x1e00000>; + no-map; + }; + + pil_adsp_dtb_mem: q6-adsp-dtb@97a00000 { + no-map; + reg =3D <0x0 0x97a00000 0x0 0x80000>; + }; + + pil_gdsp0_dtb_mem: pil-gdsp0-dtb@97a80000 { + no-map; + reg =3D <0x0 0x97a80000 0x0 0x80000>; + }; + + pil_gdsp0_mem: pil-gdsp0@97b00000 { + reg =3D <0x0 0x97b00000 0x0 0x1e00000>; + no-map; + }; + + pil_gdsp1_mem: pil-gdsp1@99900000 { + reg =3D <0x0 0x99900000 0x0 0x1e00000>; + no-map; + }; + + pil_gdsp1_dtb_mem: pil-gdsp1-dtb@9b700000 { + no-map; + reg =3D <0x0 0x9b700000 0x0 0x80000>; + }; + + pil_cdsp0_dtb_mem: pil-cdsp0-dtb@9b780000 { + no-map; + reg =3D <0x0 0x9b780000 0x0 0x80000>; + }; + + pil_cdsp0_mem: pil-cdsp0@9b800000 { + reg =3D <0x0 0x9b800000 0x0 0x1e00000>; + no-map; + }; + + pil_gpu_mem: pil-gpu@9d600000 { + reg =3D <0x0 0x9d600000 0x0 0x2000>; + no-map; + }; + + pil_cdsp1_dtb_mem: pil-cdsp1-dtb@9d680000 { + no-map; + reg =3D <0x0 0x9d680000 0x0 0x80000>; + }; + + pil_cdsp1_mem: pil-cdsp1@9d700000 { + reg =3D <0x0 0x9d700000 0x0 0x1e00000>; + no-map; + }; + + pil_cvp_mem: pil-cvp@9f500000 { + reg =3D <0x0 0x9f500000 0x0 0x700000>; + no-map; + }; + + pil_video_mem: pil-video@9fc00000 { + reg =3D <0x0 0x9fc00000 0x0 0x700000>; + no-map; + }; + + audio_config_mem: audio-config-region@ac600000 { + no-map; + reg =3D <0x0 0xac600000 0x0 0xa00000>; + }; + + audio_mdf_mem: audio-mdf-region@ad000000 { + reg =3D <0x0 0xad000000 0x0 0x2000000>; + no-map; + }; + + firmware_mem: firmware-region@b0000000 { + reg =3D <0x0 0xb0000000 0x0 0x800000>; + no-map; + }; + + hyptz_reserved_mem: hyptz-reserved@beb00000 { + reg =3D <0x0 0xbeb00000 0x0 0x11500000>; + no-map; + }; + + scmi_mem: scmi-region@d0000000 { + reg =3D <0x0 0xd0000000 0x0 0x40000>; + no-map; + }; + + firmware_logs_mem: firmware-logs@d0040000 { + reg =3D <0x0 0xd0040000 0x0 0x10000>; + no-map; + }; + + firmware_audio_mem: firmware-audio@d0050000 { + reg =3D <0x0 0xd0050000 0x0 0x4000>; + no-map; + }; + + firmware_camera_mem: firmware-camera@d0054000 { + no-map; + reg =3D <0x0 0xd0054000 0x0 0x2000>; + }; + + firmware_reserved_mem: firmware-reserved@d0056000 { + reg =3D <0x0 0xd0056000 0x0 0x9a000>; + no-map; + }; + + firmware_quantum_test_mem: firmware-quantum-test@d00f0000 { + reg =3D <0x0 0xd00f0000 0x0 0x10000>; + no-map; + }; + + tags_mem: tags@d0100000 { + reg =3D <0x0 0xd0100000 0x0 0x1200000>; + no-map; + }; + + qtee_mem: qtee@d1300000 { + reg =3D <0x0 0xd1300000 0x0 0x500000>; + no-map; + }; + + deepsleep_backup_mem: deepsleep-backup@d1800000 { + reg =3D <0x0 0xd1800000 0x0 0x100000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@d1900000 { + reg =3D <0x0 0xd1900000 0x0 0x3800000>; + no-map; + }; + + tz_stat_mem: tz-stat@db100000 { + reg =3D <0x0 0xdb100000 0x0 0x100000>; + no-map; + }; + + cpucp_fw_mem: cpucp-fw@db200000 { + reg =3D <0x0 0xdb200000 0x0 0x100000>; + no-map; + }; + + cma: linux,cma { + compatible =3D "shared-dma-pool"; + alloc-ranges =3D <0x0 0x00000000 0x0 0xdfffffff>; + reusable; + alignment =3D <0x0 0x400000>; + size =3D <0x0 0x2000000>; + linux,cma-default; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0 0 0 0 0x10 0>; + + ipcc0: mailbox@408000 { + compatible =3D "qcom,sa8255p-ipcc", "qcom,ipcc"; + reg =3D <0x0 0x00408000 0x0 0x1000>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <3>; + #mbox-cells =3D <2>; + }; + + ipcc1: mailbox@488000 { + compatible =3D "qcom,sa8255p-ipcc", "qcom,ipcc"; + reg =3D <0x0 0x00488000 0x0 0x1000>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <3>; + #mbox-cells =3D <2>; + status =3D "disabled"; + }; + + qupv3_id_2: geniqup@8c0000 { + compatible =3D "qcom,sa8255p-geni-se-qup"; + reg =3D <0x0 0x008c0000 0x0 0x6000>; + ranges; + iommus =3D <&apps_smmu 0x5a3 0x0>; + #address-cells =3D <2>; + #size-cells =3D <2>; + status =3D "disabled"; + + uart14: serial@880000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x00880000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + + uart15: serial@884000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x00884000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + + uart16: serial@888000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x00888000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + + uart17: serial@88c000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x0088c000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + + uart18: serial@890000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x00890000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + + uart19: serial@894000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x00894000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + + uart20: serial@898000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x00898000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + }; + + qupv3_id_0: geniqup@9c0000 { + compatible =3D "qcom,sa8255p-geni-se-qup"; + reg =3D <0x0 0x9c0000 0x0 0x6000>; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + iommus =3D <&apps_smmu 0x403 0x0>; + status =3D "disabled"; + + uart0: serial@980000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x980000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + + uart1: serial@984000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x984000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + + uart2: serial@988000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x988000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + + uart3: serial@98c000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x98c000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + + uart4: serial@990000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x990000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + + uart5: serial@994000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x994000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible =3D "qcom,sa8255p-geni-se-qup"; + reg =3D <0x0 0x00ac0000 0x0 0x6000>; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + iommus =3D <&apps_smmu 0x443 0x0>; + status =3D "disabled"; + + uart7: serial@a80000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x00a80000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + + uart8: serial@a84000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x00a84000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + + uart9: serial@a88000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0xa88000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + + uart10: serial@a8c000 { + compatible =3D "qcom,sa8255p-geni-debug-uart"; + reg =3D <0x0 0x00a8c000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + + uart11: serial@a90000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x00a90000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + + uart12: serial@a94000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x00a94000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + + }; + + qupv3_id_3: geniqup@bc0000 { + compatible =3D "qcom,sa8255p-geni-se-qup"; + reg =3D <0x0 0xbc0000 0x0 0x6000>; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + iommus =3D <&apps_smmu 0x43 0x0>; + status =3D "disabled"; + + uart21: serial@b80000 { + compatible =3D "qcom,sa8255p-geni-uart"; + reg =3D <0x0 0x00b80000 0x0 0x4000>; + interrupts =3D ; + status =3D "disabled"; + }; + }; + + rng: rng@10d2000 { + compatible =3D "qcom,sa8255p-trng", "qcom,trng"; + reg =3D <0x0 0x010d2000 0x0 0x1000>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x01f40000 0x0 0x20000>; + #hwlock-cells =3D <1>; + }; + + tcsr: syscon@1fc0000 { + compatible =3D "qcom,sa8255p-tcsr", "syscon"; + reg =3D <0x0 0x1fc0000 0x0 0x30000>; + }; + + adreno_smmu: iommu@3da0000 { + compatible =3D "qcom,sa8255p-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x03da0000 0x0 0x20000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <2>; + dma-coherent; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pdc: interrupt-controller@b220000 { + compatible =3D "qcom,sa8255p-pdc", "qcom,pdc"; + reg =3D <0x0 0x0b220000 0x0 0x30000>, + <0x0 0x17c000f0 0x0 0x64>; + qcom,pdc-ranges =3D <0 480 40>, + <40 140 14>, + <54 263 1>, + <55 306 4>, + <59 312 3>, + <62 374 2>, + <64 434 2>, + <66 438 2>, + <70 520 1>, + <73 523 1>, + <118 568 6>, + <124 609 3>, + <159 638 1>, + <160 720 3>, + <169 728 30>, + <199 416 2>, + <201 449 1>, + <202 89 1>, + <203 451 1>, + <204 462 1>, + <205 264 1>, + <206 579 1>, + <207 653 1>, + <208 656 1>, + <209 659 1>, + <210 122 1>, + <211 699 1>, + <212 705 1>, + <213 450 1>, + <214 643 2>, + <216 646 5>, + <221 390 5>, + <226 700 2>, + <228 440 1>, + <229 663 1>, + <230 524 2>, + <232 612 3>, + <235 723 5>; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&intc>; + interrupt-controller; + }; + + tsens2: thermal-sensor@c251000 { + compatible =3D "qcom,sa8255p-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c251000 0x0 0x1ff>, + <0x0 0x0c224000 0x0 0x8>; + interrupts =3D , + ; + interrupt-names =3D "uplow", "critical"; + #thermal-sensor-cells =3D <1>; + #qcom,sensors =3D <13>; + }; + + tsens3: thermal-sensor@c252000 { + compatible =3D "qcom,sa8255p-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c252000 0x0 0x1ff>, + <0x0 0x0c225000 0x0 0x8>; + interrupts =3D , + ; + interrupt-names =3D "uplow", "critical"; + #thermal-sensor-cells =3D <1>; + #qcom,sensors =3D <13>; + }; + + tsens0: thermal-sensor@c263000 { + compatible =3D "qcom,sa8255p-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c263000 0x0 0x1ff>, + <0x0 0x0c222000 0x0 0x8>; + interrupts =3D , + ; + interrupt-names =3D "uplow", "critical"; + #thermal-sensor-cells =3D <1>; + #qcom,sensors =3D <12>; + }; + + tsens1: thermal-sensor@c265000 { + compatible =3D "qcom,sa8255p-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c265000 0x0 0x1ff>, + <0x0 0x0c223000 0x0 0x8>; + interrupts =3D , + ; + interrupt-names =3D "uplow", "critical"; + #thermal-sensor-cells =3D <1>; + #qcom,sensors =3D <12>; + }; + + aoss_qmp: power-management@c300000 { + compatible =3D "qcom,sa8255p-aoss-qmp", "qcom,aoss-qmp"; + reg =3D <0x0 0x0c300000 0x0 0x400>; + interrupts-extended =3D <&ipcc0 IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc0 IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + #clock-cells =3D <0>; + }; + + tlmm: pinctrl@f000000 { + compatible =3D "qcom,sa8255p-tlmm", "qcom,sa8775p-tlmm"; + reg =3D <0x0 0x0f000000 0x0 0x1000000>; + interrupts =3D ; + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + gpio-ranges =3D <&tlmm 0 0 149>; + wakeup-parent =3D <&pdc>; + }; + + apps_smmu: iommu@15000000 { + compatible =3D "qcom,sa8255p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x15000000 0x0 0x100000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <2>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + intc: interrupt-controller@17a00000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupt-controller; + #interrupt-cells =3D <3>; + interrupts =3D ; + #redistributor-regions =3D <1>; + redistributor-stride =3D <0x0 0x20000>; + }; + + watchdog@17c10000 { + compatible =3D "qcom,apss-wdt-sa8255p", "qcom,kpss-wdt"; + reg =3D <0x0 0x17c10000 0x0 0x1000>; + clocks =3D <&sleep_clk>; + interrupts =3D ; + }; + + memtimer: timer@17c20000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0x17c20000 0x0 0x1000>; + ranges =3D <0x0 0x0 0x0 0x20000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + frame@17c21000 { + reg =3D <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + interrupts =3D , + ; + frame-number =3D <0>; + }; + + frame@17c23000 { + reg =3D <0x17c23000 0x1000>; + interrupts =3D ; + frame-number =3D <1>; + status =3D "disabled"; + }; + + frame@17c25000 { + reg =3D <0x17c25000 0x1000>; + interrupts =3D ; + frame-number =3D <2>; + status =3D "disabled"; + }; + + frame@17c27000 { + reg =3D <0x17c27000 0x1000>; + interrupts =3D ; + frame-number =3D <3>; + status =3D "disabled"; + }; + + frame@17c29000 { + reg =3D <0x17c29000 0x1000>; + interrupts =3D ; + frame-number =3D <4>; + status =3D "disabled"; + }; + + frame@17c2b000 { + reg =3D <0x17c2b000 0x1000>; + interrupts =3D ; + frame-number =3D <5>; + status =3D "disabled"; + }; + + frame@17c2d000 { + reg =3D <0x17c2d000 0x1000>; + interrupts =3D ; + frame-number =3D <6>; + status =3D "disabled"; + }; + }; + + cpufreq_hw: cpufreq@18591000 { + compatible =3D "qcom,sa8255p-cpufreq-epss", + "qcom,cpufreq-epss"; + reg =3D <0x0 0x18591000 0x0 0x1000>, + <0x0 0x18593000 0x0 0x1000>; + reg-names =3D "freq-domain0", "freq-domain1"; + clocks =3D <&bi_tcxo_div2>, <&gpll0_board_clk>; + clock-names =3D "xo", "alternate"; + #freq-domain-cells =3D <1>; + }; + }; + + thermal-zones { + aoss-0-thermal { + thermal-sensors =3D <&tsens0 0>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-0-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 1>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-1-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 2>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-2-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 3>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-3-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 4>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + gpuss-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 5>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + gpuss-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 6>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + gpuss-2-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 7>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + audio-thermal { + thermal-sensors =3D <&tsens0 8>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + camss-0-thermal { + thermal-sensors =3D <&tsens0 9>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pcie-0-thermal { + thermal-sensors =3D <&tsens0 10>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cpuss-0-0-thermal { + thermal-sensors =3D <&tsens0 11>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + aoss-1-thermal { + thermal-sensors =3D <&tsens1 0>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-0-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 1>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-1-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 2>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-2-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 3>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cpu-0-3-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 4>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + gpuss-3-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 5>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + gpuss-4-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 6>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + gpuss-5-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 7>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + video-thermal { + thermal-sensors =3D <&tsens1 8>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + camss-1-thermal { + thermal-sensors =3D <&tsens1 9>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + pcie-1-thermal { + thermal-sensors =3D <&tsens1 10>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cpuss-0-1-thermal { + thermal-sensors =3D <&tsens1 11>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + aoss-2-thermal { + thermal-sensors =3D <&tsens2 0>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-0-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens2 1>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-1-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens2 2>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-2-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens2 3>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-3-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens2 4>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + nsp-0-0-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens2 5>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + nsp-0-1-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens2 6>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + nsp-0-2-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens2 7>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + nsp-1-0-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens2 8>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + nsp-1-1-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens2 9>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + nsp-1-2-0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens2 10>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + ddrss-0-thermal { + thermal-sensors =3D <&tsens2 11>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cpuss-1-0-thermal { + thermal-sensors =3D <&tsens2 12>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + aoss-3-thermal { + thermal-sensors =3D <&tsens3 0>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-0-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens3 1>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-1-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens3 2>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-2-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens3 3>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cpu-1-3-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens3 4>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + nsp-0-0-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens3 5>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + nsp-0-1-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens3 6>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + nsp-0-2-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens3 7>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + nsp-1-0-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens3 8>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + nsp-1-1-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens3 9>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + nsp-1-2-1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens3 10>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + ddrss-1-thermal { + thermal-sensors =3D <&tsens3 11>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + + cpuss-1-1-thermal { + thermal-sensors =3D <&tsens3 12>; + + trips { + trip-point0 { + temperature =3D <105000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <115000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + }; + }; + }; + + arch_timer: timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; +}; base-commit: f6b66b288edf32f91d2330eaf8b84714819ac50a --=20 2.25.1