From nobody Mon Feb 9 03:30:44 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 46A651D5ADE; Tue, 22 Apr 2025 17:39:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745343598; cv=none; b=C0fcHxBT6aRNiFU1wTvZNR/A5cl/4qDNcZKJhwY+Xdg5bOp3hFkhrbLJfcnEYb/e1XkInKTibdPZKrTtMgpbgIvNPiQ44C/BnzKLc4s+QWaIkiFZtXrlL2vz3TaVJMJn9F3oD5lMfMpiSzn4bxVVEgXqSY2jtzilXbckIsKHBz4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745343598; c=relaxed/simple; bh=PBLpPLSLfe9Mt+GQNQVbm4ymFf8m7p+zdoI3fFJOxCE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LVyoFfKcXNezfRlxJLxSrgDSlgpeHCzxo5majZfa+Zq7kG1Zj+gu5a86HIAqGTMZRTGJbhzLoC4ozYLj42ytGNuNg3ioFMoqVYrpOCQqiW+z5WDyVnOcjCTVpSyScMp1xBTeRXFmmtJyruQV3dV1bkzMlvWGaPZ1tjUznvBLbMo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: 7uzH/BrCQ4yR9cDigrAgCA== X-CSE-MsgGUID: zY6CyfWZTeasNnAX9/p5WA== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 23 Apr 2025 02:39:50 +0900 Received: from mulinux.home (unknown [10.226.92.16]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 45CA64043788; Wed, 23 Apr 2025 02:39:46 +0900 (JST) From: Fabrizio Castro To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Fabrizio Castro , Biju Das , Wolfram Sang , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Lad Prabhakar , Conor Dooley Subject: [PATCH v6 1/6] dt-bindings: dma: rz-dmac: Restrict properties for RZ/A1H Date: Tue, 22 Apr 2025 18:39:32 +0100 Message-Id: <20250422173937.3722875-2-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250422173937.3722875-1-fabrizio.castro.jz@renesas.com> References: <20250422173937.3722875-1-fabrizio.castro.jz@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Make sure we don't allow for the clocks, clock-names, resets, reset-names. and power-domains properties for the Renesas RZ/A1H SoC because its DMAC doesn't have clocks, resets, and power domains. Fixes: 209efec19c4c ("dt-bindings: dma: rz-dmac: Document RZ/A1H SoC") Signed-off-by: Fabrizio Castro Acked-by: Conor Dooley Reviewed-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v5->v6: * No change. v4->v5: * Collected tags. v3->v4: * No change. v2->v3: * No change. v1->v2: * No change. --- .../devicetree/bindings/dma/renesas,rz-dmac.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/D= ocumentation/devicetree/bindings/dma/renesas,rz-dmac.yaml index b356251de5a8..82de3b927479 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml @@ -112,6 +112,14 @@ allOf: - resets - reset-names =20 + else: + properties: + clocks: false + clock-names: false + power-domains: false + resets: false + reset-names: false + additionalProperties: false =20 examples: --=20 2.34.1 From nobody Mon Feb 9 03:30:44 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D5E381E0DDC; Tue, 22 Apr 2025 17:39:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745343599; cv=none; b=FuSolycJllFZUk6uxrCIXnn7g80OUOA2zAKrOON22dPnoeq0A++uy2gu1edF56wbStvX9YER96DUp0xQbE+JDXolTlXHn73hMTwGKURrXZD3X3G3tLqRbcw9dubmw+s9dkyT675Ufc82s1VJunoRJ0AoijXl+oenPKgVaXk/ngk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745343599; c=relaxed/simple; bh=hM5uRm2ZzSyafoF0r32/Knq4faTcoF4fBnWkJJ6N15M=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FLeiwYmQG5atY42EwecPbzzwaXWUgosKQG2g4ln4pgISWlrfVSZTf1nxulncKZUv0i52424xhZl9IAFY01TZ3L/zhBrydQeRaN0DVxCl3WKvE5OLfHqqeK1jr6KJSg5yc6djeZDUOCICRLYLK1h1g/yK7aoDE+uD153aNPC3iPQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: LR4Od9yIRm6E4O261/rJbw== X-CSE-MsgGUID: DOQZYdAHSmS7WYuPTn3GlQ== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 23 Apr 2025 02:39:55 +0900 Received: from mulinux.home (unknown [10.226.92.16]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 0BC1A4043788; Wed, 23 Apr 2025 02:39:50 +0900 (JST) From: Fabrizio Castro To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Fabrizio Castro , Biju Das , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Lad Prabhakar , Conor Dooley Subject: [PATCH v6 2/6] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs Date: Tue, 22 Apr 2025 18:39:33 +0100 Message-Id: <20250422173937.3722875-3-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250422173937.3722875-1-fabrizio.castro.jz@renesas.com> References: <20250422173937.3722875-1-fabrizio.castro.jz@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the Renesas RZ/V2H(P) family of SoCs DMAC block. The Renesas RZ/V2H(P) DMAC is very similar to the one found on the Renesas RZ/G2L family of SoCs, but there are some differences: * It only uses one register area * It only uses one clock * It only uses one reset * Instead of using MID/IRD it uses REQ No * It is connected to the Interrupt Control Unit (ICU) Signed-off-by: Fabrizio Castro Acked-by: Conor Dooley Reviewed-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Reviewed-by: Rob Herring (Arm) --- v5->v6: * Reworked the description of `#dma-cells`. * Reworked `renesas,icu` related descriptions. * Added `reg:`->`minItems: 2` for `renesas,r7s72100-dmac`. * Since the structure of the document remains the same, I have kept the tags I have received. Please let me know if that's not okay. v4->v5: * Removed ACK No from the specification of the dma cell. * I have kept the tags received as this is a minor change and the structure remains the same as v4. Please let me know if this is not okay. v3->v4: * No change. v2->v3: * No change. v1->v2: * Removed RZ/V2H DMAC example. * Improved the readability of the `if` statement. --- .../bindings/dma/renesas,rz-dmac.yaml | 101 ++++++++++++++---- 1 file changed, 82 insertions(+), 19 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/D= ocumentation/devicetree/bindings/dma/renesas,rz-dmac.yaml index 82de3b927479..6cdf6658b672 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml @@ -11,19 +11,23 @@ maintainers: =20 properties: compatible: - items: - - enum: - - renesas,r7s72100-dmac # RZ/A1H - - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five - - renesas,r9a07g044-dmac # RZ/G2{L,LC} - - renesas,r9a07g054-dmac # RZ/V2L - - renesas,r9a08g045-dmac # RZ/G3S - - const: renesas,rz-dmac + oneOf: + - items: + - enum: + - renesas,r7s72100-dmac # RZ/A1H + - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five + - renesas,r9a07g044-dmac # RZ/G2{L,LC} + - renesas,r9a07g054-dmac # RZ/V2L + - renesas,r9a08g045-dmac # RZ/G3S + - const: renesas,rz-dmac + + - const: renesas,r9a09g057-dmac # RZ/V2H(P) =20 reg: items: - description: Control and channel register block - description: DMA extended resource selector block + minItems: 1 =20 interrupts: maxItems: 17 @@ -52,6 +56,7 @@ properties: items: - description: DMA main clock - description: DMA register access clock + minItems: 1 =20 clock-names: items: @@ -61,10 +66,10 @@ properties: '#dma-cells': const: 1 description: - The cell specifies the encoded MID/RID values of the DMAC port - connected to the DMA client and the slave channel configuration - parameters. - bits[0:9] - Specifies MID/RID value + The cell specifies the encoded MID/RID or the REQ No values of + the DMAC port connected to the DMA client and the slave channel + configuration parameters. + bits[0:9] - Specifies the MID/RID or the REQ No value bit[10] - Specifies DMA request high enable (HIEN) bit[11] - Specifies DMA request detection type (LVL) bits[12:14] - Specifies DMAACK output mode (AM) @@ -80,12 +85,26 @@ properties: items: - description: Reset for DMA ARESETN reset terminal - description: Reset for DMA RST_ASYNC reset terminal + minItems: 1 =20 reset-names: items: - const: arst - const: rst_async =20 + renesas,icu: + description: + It must contain the phandle to the ICU, and the index of the DMAC as= seen + from the ICU (e.g. parameter k from register ICU_DMkSELy). + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the ICU node. + - description: + The number of the DMAC as seen from the ICU, i.e. parameter = k from + register ICU_DMkSELy. This may differ from the actual DMAC i= nstance + number. + required: - compatible - reg @@ -98,13 +117,25 @@ allOf: - $ref: dma-controller.yaml# =20 - if: - not: - properties: - compatible: - contains: - enum: - - renesas,r7s72100-dmac + properties: + compatible: + contains: + enum: + - renesas,r9a07g043-dmac + - renesas,r9a07g044-dmac + - renesas,r9a07g054-dmac + - renesas,r9a08g045-dmac then: + properties: + reg: + minItems: 2 + clocks: + minItems: 2 + resets: + minItems: 2 + + renesas,icu: false + required: - clocks - clock-names @@ -112,13 +143,45 @@ allOf: - resets - reset-names =20 - else: + - if: + properties: + compatible: + contains: + const: renesas,r7s72100-dmac + then: properties: + reg: + minItems: 2 + clocks: false clock-names: false power-domains: false resets: false reset-names: false + renesas,icu: false + + - if: + properties: + compatible: + contains: + const: renesas,r9a09g057-dmac + then: + properties: + reg: + maxItems: 1 + clocks: + maxItems: 1 + resets: + maxItems: 1 + + clock-names: false + reset-names: false + + required: + - clocks + - power-domains + - renesas,icu + - resets =20 additionalProperties: false =20 --=20 2.34.1 From nobody Mon Feb 9 03:30:44 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A842A280A3A; Tue, 22 Apr 2025 17:39:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745343600; cv=none; b=JyrDqlsYsJuS5wnUwo9ejIEktZGWb5oo9NtHT7OSJ9vCtkAl+0OQ/7puzyYElso5WdnvrRb7gJT1nFZg3ir2WTJbp1Ft4lI06+chf5dWpNRd4nMOzLSmADuz5e0F6lPN9h5/2JoBOSXt8touKEgQlBcld+nrZX70ScWHOOGfUEs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745343600; c=relaxed/simple; bh=Udm3qOb6uwZ+fwJOlgX4PzedELLqGOI1lTpe5FwzcHA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fHDmIShmLIsi4t/goGdcujPhC1/Ykae0cz0B2YbLXWJFINUNDZzKy6Sb0UVq+A10RB3MPcoCRfpTstTFfMnAN1w6QxKQI1Yk5oEBACWfBJuUPJc2/rsEtQYWn1BX/IX9/db8SbnaY/CHGdX2stP01aAzg4y7AHa793zge5hdX18= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: f+in2TO1RYabZmxXpMuRGQ== X-CSE-MsgGUID: Zmx9e3uPSculBAjTHu7c0w== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 23 Apr 2025 02:39:57 +0900 Received: from mulinux.home (unknown [10.226.92.16]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 8DD564043788; Wed, 23 Apr 2025 02:39:55 +0900 (JST) From: Fabrizio Castro To: Thomas Gleixner , Geert Uytterhoeven Cc: Fabrizio Castro , Lad Prabhakar , linux-kernel@vger.kernel.org, Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v6 3/6] irqchip/renesas-rzv2h: Add rzv2h_icu_register_dma_req() Date: Tue, 22 Apr 2025 18:39:34 +0100 Message-Id: <20250422173937.3722875-4-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250422173937.3722875-1-fabrizio.castro.jz@renesas.com> References: <20250422173937.3722875-1-fabrizio.castro.jz@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On the Renesas RZ/V2H(P) family of SoCs, DMAC IPs are connected to the Interrupt Control Unit (ICU). For DMA transfers, a request number must be registered with the ICU, which means that the DMAC driver has to be able to instruct the ICU driver with the registration of such id. Export rzv2h_icu_register_dma_req() so that the DMAC driver can register the DMAC request number. Signed-off-by: Fabrizio Castro Reviewed-by: Thomas Gleixner Reviewed-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v5->v6: * Collected tags. v4->v5: * Dropped the registration of ACK No. * Removed some #define in the driver and in the header file. * Renamed the exported function to rzv2h_icu_register_dma_req. * Rebased on top of the latest ICU related changes from Biju. * Reworked changelog and title. * Dropped Thomas' Reviewed-by tag as too much has changed since v4. v3->v4: * No change. v2->v3: * Replaced rzv2h_icu_register_dma_req_ack with rzv2h_icu_register_dma_req_ack() in changelog. * Added dummy for rzv2h_icu_register_dma_req_ack(). * Added Rb Thomas. v1->v2: * Improved macros. * Shared new macros for minimum values. --- drivers/irqchip/irq-renesas-rzv2h.c | 35 +++++++++++++++++++++++ include/linux/irqchip/irq-renesas-rzv2h.h | 23 +++++++++++++++ 2 files changed, 58 insertions(+) create mode 100644 include/linux/irqchip/irq-renesas-rzv2h.h diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index 0f0fd7d4dfdf..4bdd4148c56f 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -41,6 +42,8 @@ #define ICU_TSCLR 0x24 #define ICU_TITSR(k) (0x28 + (k) * 4) #define ICU_TSSR(k) (0x30 + (k) * 4) +#define ICU_DMkSELy(k, y) (0x420 + (k) * 0x20 + (y) * 4) +#define ICU_DMACKSELk(k) (0x500 + (k) * 4) =20 /* NMI */ #define ICU_NMI_EDGE_FALLING 0 @@ -103,6 +106,15 @@ struct rzv2h_hw_info { u8 field_width; }; =20 +/* DMAC */ +#define ICU_DMAC_DkRQ_SEL_MASK GENMASK(9, 0) + +#define ICU_DMAC_DMAREQ_SHIFT(up) ((up) * 16) +#define ICU_DMAC_DMAREQ_MASK(up) (ICU_DMAC_DkRQ_SEL_MASK \ + << ICU_DMAC_DMAREQ_SHIFT(up)) +#define ICU_DMAC_PREP_DMAREQ(sel, up) (FIELD_PREP(ICU_DMAC_DkRQ_SEL_MASK,= (sel)) \ + << ICU_DMAC_DMAREQ_SHIFT(up)) + /** * struct rzv2h_icu_priv - Interrupt Control Unit controller private data = structure. * @base: Controller's base address @@ -117,6 +129,27 @@ struct rzv2h_icu_priv { const struct rzv2h_hw_info *info; }; =20 +void rzv2h_icu_register_dma_req(struct platform_device *icu_dev, u8 dmac_i= ndex, u8 dmac_channel, + u16 req_no) +{ + struct rzv2h_icu_priv *priv =3D platform_get_drvdata(icu_dev); + u32 icu_dmksely, dmareq, dmareq_mask; + u8 y, upper; + + y =3D dmac_channel / 2; + upper =3D dmac_channel % 2; + + dmareq =3D ICU_DMAC_PREP_DMAREQ(req_no, upper); + dmareq_mask =3D ICU_DMAC_DMAREQ_MASK(upper); + + guard(raw_spinlock_irqsave)(&priv->lock); + + icu_dmksely =3D readl(priv->base + ICU_DMkSELy(dmac_index, y)); + icu_dmksely =3D (icu_dmksely & ~dmareq_mask) | dmareq; + writel(icu_dmksely, priv->base + ICU_DMkSELy(dmac_index, y)); +} +EXPORT_SYMBOL_GPL(rzv2h_icu_register_dma_req); + static inline struct rzv2h_icu_priv *irq_data_to_priv(struct irq_data *dat= a) { return data->domain->host_data; @@ -491,6 +524,8 @@ static int rzv2h_icu_init_common(struct device_node *no= de, struct device_node *p if (!rzv2h_icu_data) return -ENOMEM; =20 + platform_set_drvdata(pdev, rzv2h_icu_data); + rzv2h_icu_data->base =3D devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, = NULL); if (IS_ERR(rzv2h_icu_data->base)) return PTR_ERR(rzv2h_icu_data->base); diff --git a/include/linux/irqchip/irq-renesas-rzv2h.h b/include/linux/irqc= hip/irq-renesas-rzv2h.h new file mode 100644 index 000000000000..618a60d2eac0 --- /dev/null +++ b/include/linux/irqchip/irq-renesas-rzv2h.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Renesas RZ/V2H(P) Interrupt Control Unit (ICU) + * + * Copyright (C) 2025 Renesas Electronics Corporation. + */ + +#ifndef __LINUX_IRQ_RENESAS_RZV2H +#define __LINUX_IRQ_RENESAS_RZV2H + +#include + +#define RZV2H_ICU_DMAC_REQ_NO_DEFAULT 0x3ff + +#ifdef CONFIG_RENESAS_RZV2H_ICU +void rzv2h_icu_register_dma_req(struct platform_device *icu_dev, u8 dmac_i= ndex, u8 dmac_channel, + u16 req_no); +#else +static inline void rzv2h_icu_register_dma_req(struct platform_device *icu_= dev, u8 dmac_index, + u8 dmac_channel, u16 req_no) { } +#endif + +#endif /* __LINUX_IRQ_RENESAS_RZV2H */ --=20 2.34.1 From nobody Mon Feb 9 03:30:44 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7DE872980C2; Tue, 22 Apr 2025 17:40:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745343603; cv=none; b=cQt/dmINPNTtWLRJY21XhqQcDN/rvFZS6jdnZ8nEEECaizaPMUZ786DY8XsTLLbAVqeZfhCrKfvhPlQNn2fNzdkBmMCyKTGvfIYK2j/jV08J0AkrqMOXZn1G/WkZM9yo1Rc0Kc4SyQROFn63ch3rXFbdN/NWZ36gVWdzJ306s34= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745343603; c=relaxed/simple; bh=T1nezSAU2/i7clh4+utfsA6OXaqiGq6mmwz7s1fsqpA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=N9UjZVUW2EovlEQPpVIGNQUqkPaGV9YzvXhXPkHKwnYkUL9L9vFJPRyml0fRX+nMXcEngeuq9hnQ6gPZWiVLYWgm2fmsOWeP5uCrxqL9wMflKT1NfyQwiNLDQkXu8ir+pjxODtmRypDmTYm/J3USyHMsdZR/exxuDbaboaMVYw8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: D+ZhbfOhTMS0BfJxF91gaw== X-CSE-MsgGUID: /R0BtqE8QyGNEoBhH4Xr/w== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 23 Apr 2025 02:40:01 +0900 Received: from mulinux.home (unknown [10.226.92.16]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 399C140437A5; Wed, 23 Apr 2025 02:39:57 +0900 (JST) From: Fabrizio Castro To: Vinod Koul , Geert Uytterhoeven Cc: Fabrizio Castro , Lad Prabhakar , Wolfram Sang , Biju Das , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v6 4/6] dmaengine: sh: rz-dmac: Allow for multiple DMACs Date: Tue, 22 Apr 2025 18:39:35 +0100 Message-Id: <20250422173937.3722875-5-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250422173937.3722875-1-fabrizio.castro.jz@renesas.com> References: <20250422173937.3722875-1-fabrizio.castro.jz@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" dma_request_channel() calls into __dma_request_channel() with NULL as value for np, which won't allow for the selection of the correct DMAC when multiple DMACs are available. Switch to using __dma_request_channel() directly so that we can choose the desired DMA for the channel. This is in preparation of adding DMAC support for the Renesas RZ/V2H(P) and similar SoCs. Signed-off-by: Fabrizio Castro Reviewed-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v5->v6: * No change. v4->v5: * Collected tags. v3->v4: * No change. v2->v3: * Added () for calls in changelog. v1->v2: * No change. --- drivers/dma/sh/rz-dmac.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index 9235db551026..d7a4ce28040b 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -748,7 +748,8 @@ static struct dma_chan *rz_dmac_of_xlate(struct of_phan= dle_args *dma_spec, dma_cap_zero(mask); dma_cap_set(DMA_SLAVE, mask); =20 - return dma_request_channel(mask, rz_dmac_chan_filter, dma_spec); + return __dma_request_channel(&mask, rz_dmac_chan_filter, dma_spec, + ofdma->of_node); } =20 /* --=20 2.34.1 From nobody Mon Feb 9 03:30:44 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3A7062980C2; Tue, 22 Apr 2025 17:40:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745343607; cv=none; b=J78MICaVLSAoidhdthHGkkXjDtka/zAfkAVx5FQzMHfT5bN0fW88ZyaGoDI/XaiGxFQO0+XoBch2uxAJoUanZ439NkVjlyHi4/tfEZF2IBwedbtd4VLwgqGFuYKz785CAskTHk1Idx/3Z4DpnsvhSSD06XC+1W+O1UEBhN4YT3I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745343607; c=relaxed/simple; bh=mhBcYuNZ2Ra7zROHPJeH98X8A2FqiAiddgszOSe3O+s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=GDezULOcpYJcUiZs/FcssL61vafC5Q+KZ2kS8x8f6bsLjIy1IGLE0SwcAmJStLFVDZS3sPf8zEF7eRlqWhMV7HSW9nhvd9WMbOSvHI4H6wWEVdOuMa/NZAgv8W8sNnYVAt6KIEukJLd9gjOfpvD3RnUl6dvHhzJlguVlHpdNtf0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: NVGXt/0bSC2RO8GoDYPWMg== X-CSE-MsgGUID: FU6Y9PO4SfmkKCxFZP1YYQ== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 23 Apr 2025 02:40:04 +0900 Received: from mulinux.home (unknown [10.226.92.16]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id C4A164043788; Wed, 23 Apr 2025 02:40:01 +0900 (JST) From: Fabrizio Castro To: Vinod Koul , Geert Uytterhoeven , Magnus Damm Cc: Fabrizio Castro , Wolfram Sang , Lad Prabhakar , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Biju Das , dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v6 5/6] dmaengine: sh: rz-dmac: Add RZ/V2H(P) support Date: Tue, 22 Apr 2025 18:39:36 +0100 Message-Id: <20250422173937.3722875-6-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250422173937.3722875-1-fabrizio.castro.jz@renesas.com> References: <20250422173937.3722875-1-fabrizio.castro.jz@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The DMAC IP found on the Renesas RZ/V2H(P) family of SoCs is similar to the version found on the Renesas RZ/G2L family of SoCs, but there are some differences: * It only uses one register area * It only uses one clock * It only uses one reset * Instead of using MID/IRD it uses REQ No * It is connected to the Interrupt Control Unit (ICU) * On the RZ/G2L there is only 1 DMAC, on the RZ/V2H(P) there are 5 Add specific support for the Renesas RZ/V2H(P) family of SoC by tackling the aforementioned differences. Signed-off-by: Fabrizio Castro Reviewed-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v5->v6: * Collected tags. v4->v5: * Reused RZ/G2L cell specification (with REQ No in place of MID/RID). * Dropped ACK No. * Removed mid_rid/req_no/ack_no union and reused mid_rid for REQ No. * Other small improvements. v3->v4: * Fixed an issue with mid_rid/req_no/ack_no initialization v2->v3: * Dropped change to Kconfig. * Replaced rz_dmac_type with has_icu flag. * Put req_no and ack_no in an anonymous struct, nested under an anonymous union with mid_rid. * Dropped data field of_rz_dmac_match[], and added logic to determine value of has_icu flag from DT parsing. v1->v2: * Switched to new macros for minimum values. --- drivers/dma/sh/rz-dmac.c | 81 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 74 insertions(+), 7 deletions(-) diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c index d7a4ce28040b..1f687b08d6b8 100644 --- a/drivers/dma/sh/rz-dmac.c +++ b/drivers/dma/sh/rz-dmac.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -89,8 +90,14 @@ struct rz_dmac_chan { =20 #define to_rz_dmac_chan(c) container_of(c, struct rz_dmac_chan, vc.chan) =20 +struct rz_dmac_icu { + struct platform_device *pdev; + u8 dmac_index; +}; + struct rz_dmac { struct dma_device engine; + struct rz_dmac_icu icu; struct device *dev; struct reset_control *rstc; void __iomem *base; @@ -99,6 +106,8 @@ struct rz_dmac { unsigned int n_channels; struct rz_dmac_chan *channels; =20 + bool has_icu; + DECLARE_BITMAP(modules, 1024); }; =20 @@ -167,6 +176,9 @@ struct rz_dmac { #define RZ_DMAC_MAX_CHANNELS 16 #define DMAC_NR_LMDESC 64 =20 +/* RZ/V2H ICU related */ +#define RZV2H_MAX_DMAC_INDEX 4 + /* * -----------------------------------------------------------------------= ------ * Device access @@ -324,7 +336,13 @@ static void rz_dmac_prepare_desc_for_memcpy(struct rz_= dmac_chan *channel) lmdesc->chext =3D 0; lmdesc->header =3D HEADER_LV; =20 - rz_dmac_set_dmars_register(dmac, channel->index, 0); + if (dmac->has_icu) { + rzv2h_icu_register_dma_req(dmac->icu.pdev, dmac->icu.dmac_index, + channel->index, + RZV2H_ICU_DMAC_REQ_NO_DEFAULT); + } else { + rz_dmac_set_dmars_register(dmac, channel->index, 0); + } =20 channel->chcfg =3D chcfg; channel->chctrl =3D CHCTRL_STG | CHCTRL_SETEN; @@ -375,7 +393,13 @@ static void rz_dmac_prepare_descs_for_slave_sg(struct = rz_dmac_chan *channel) =20 channel->lmdesc.tail =3D lmdesc; =20 - rz_dmac_set_dmars_register(dmac, channel->index, channel->mid_rid); + if (dmac->has_icu) { + rzv2h_icu_register_dma_req(dmac->icu.pdev, dmac->icu.dmac_index, + channel->index, channel->mid_rid); + } else { + rz_dmac_set_dmars_register(dmac, channel->index, channel->mid_rid); + } + channel->chctrl =3D CHCTRL_SETEN; } =20 @@ -647,7 +671,13 @@ static void rz_dmac_device_synchronize(struct dma_chan= *chan) if (ret < 0) dev_warn(dmac->dev, "DMA Timeout"); =20 - rz_dmac_set_dmars_register(dmac, channel->index, 0); + if (dmac->has_icu) { + rzv2h_icu_register_dma_req(dmac->icu.pdev, dmac->icu.dmac_index, + channel->index, + RZV2H_ICU_DMAC_REQ_NO_DEFAULT); + } else { + rz_dmac_set_dmars_register(dmac, channel->index, 0); + } } =20 /* @@ -824,6 +854,38 @@ static int rz_dmac_chan_probe(struct rz_dmac *dmac, return 0; } =20 +static int rz_dmac_parse_of_icu(struct device *dev, struct rz_dmac *dmac) +{ + struct device_node *np =3D dev->of_node; + struct of_phandle_args args; + uint32_t dmac_index; + int ret; + + ret =3D of_parse_phandle_with_fixed_args(np, "renesas,icu", 1, 0, &args); + if (ret =3D=3D -ENOENT) + return 0; + if (ret) + return ret; + + dmac->has_icu =3D true; + + dmac->icu.pdev =3D of_find_device_by_node(args.np); + of_node_put(args.np); + if (!dmac->icu.pdev) { + dev_err(dev, "ICU device not found.\n"); + return -ENODEV; + } + + dmac_index =3D args.args[0]; + if (dmac_index > RZV2H_MAX_DMAC_INDEX) { + dev_err(dev, "DMAC index %u invalid.\n", dmac_index); + return -EINVAL; + } + dmac->icu.dmac_index =3D dmac_index; + + return 0; +} + static int rz_dmac_parse_of(struct device *dev, struct rz_dmac *dmac) { struct device_node *np =3D dev->of_node; @@ -840,7 +902,7 @@ static int rz_dmac_parse_of(struct device *dev, struct = rz_dmac *dmac) return -EINVAL; } =20 - return 0; + return rz_dmac_parse_of_icu(dev, dmac); } =20 static int rz_dmac_probe(struct platform_device *pdev) @@ -874,9 +936,11 @@ static int rz_dmac_probe(struct platform_device *pdev) if (IS_ERR(dmac->base)) return PTR_ERR(dmac->base); =20 - dmac->ext_base =3D devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(dmac->ext_base)) - return PTR_ERR(dmac->ext_base); + if (!dmac->has_icu) { + dmac->ext_base =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(dmac->ext_base)) + return PTR_ERR(dmac->ext_base); + } =20 /* Register interrupt handler for error */ irq =3D platform_get_irq_byname(pdev, irqname); @@ -991,9 +1055,12 @@ static void rz_dmac_remove(struct platform_device *pd= ev) reset_control_assert(dmac->rstc); pm_runtime_put(&pdev->dev); pm_runtime_disable(&pdev->dev); + + platform_device_put(dmac->icu.pdev); } =20 static const struct of_device_id of_rz_dmac_match[] =3D { + { .compatible =3D "renesas,r9a09g057-dmac", }, { .compatible =3D "renesas,rz-dmac", }, { /* Sentinel */ } }; --=20 2.34.1 From nobody Mon Feb 9 03:30:44 2026 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id F298E1E0E0B; Tue, 22 Apr 2025 17:45:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745343924; cv=none; b=K7FHkR3VlsFJ7cuEnV9XTE25VKoM5yPrqGu/Msa2Ap8Cd2U0eKN0s7VUMnteLK13gj5i/VkJhgaROHfzHMNWOuPcngF0qGmFnPiw0epxTwyZhbdLWOOGIZEBcjKxT91iJecUu2LHofMF0NEL9NdTeIA2qtpng089AJ3a8K6yb58= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745343924; c=relaxed/simple; bh=TP92gUWGVkFzH3MKoN1aN8S/2F6S96syX8J46GyVAg0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Ri7mibtGjC8a7uJsYk0IuNEnrNXo1usXUNSHMKuQJZy4yJxZyHSneUbzN2JfCXpfGiASHCQmJovNjbfNkaGQyZPTfP44csOoEMlLrfte0LbC/mdpt7k1FSf62vHag/a4WkwAwtcMPqZ8Cvy48hsx4etdVBTctoJfAMoZeCrHYRc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: wfq5pVq0Qai6PcUL5g4+XQ== X-CSE-MsgGUID: sJkLmvwBSdCwTRIyHgaEQw== Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 23 Apr 2025 02:40:08 +0900 Received: from mulinux.home (unknown [10.226.92.16]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 800B34045852; Wed, 23 Apr 2025 02:40:05 +0900 (JST) From: Fabrizio Castro To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Fabrizio Castro , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Lad Prabhakar Subject: [PATCH v6 6/6] arm64: dts: renesas: r9a09g057: Add DMAC nodes Date: Tue, 22 Apr 2025 18:39:37 +0100 Message-Id: <20250422173937.3722875-7-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250422173937.3722875-1-fabrizio.castro.jz@renesas.com> References: <20250422173937.3722875-1-fabrizio.castro.jz@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add nodes for the DMAC IPs found on the Renesas RZ/V2H(P) SoC. Signed-off-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven Reviewed-by: Lad Prabhakar --- v5->v6: * Rebased on top of the latest changes. * Added Prabhakar's Reviewed-by tag. v4->v5: * Collected tags. v3->v4: * No change. v2->v3: * No change. v1->v2: * No change. --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 165 +++++++++++++++++++++ 1 file changed, 165 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g057.dtsi index 18ab5639b301..0f3501951409 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -280,6 +280,171 @@ sys: system-controller@10430000 { resets =3D <&cpg 0x30>; }; =20 + dmac0: dma-controller@11400000 { + compatible =3D "renesas,r9a09g057-dmac"; + reg =3D <0 0x11400000 0 0x10000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks =3D <&cpg CPG_MOD 0x0>; + power-domains =3D <&cpg>; + resets =3D <&cpg 0x31>; + #dma-cells =3D <1>; + dma-channels =3D <16>; + renesas,icu =3D <&icu 4>; + }; + + dmac1: dma-controller@14830000 { + compatible =3D "renesas,r9a09g057-dmac"; + reg =3D <0 0x14830000 0 0x10000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks =3D <&cpg CPG_MOD 0x1>; + power-domains =3D <&cpg>; + resets =3D <&cpg 0x32>; + #dma-cells =3D <1>; + dma-channels =3D <16>; + renesas,icu =3D <&icu 0>; + }; + + dmac2: dma-controller@14840000 { + compatible =3D "renesas,r9a09g057-dmac"; + reg =3D <0 0x14840000 0 0x10000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks =3D <&cpg CPG_MOD 0x2>; + power-domains =3D <&cpg>; + resets =3D <&cpg 0x33>; + #dma-cells =3D <1>; + dma-channels =3D <16>; + renesas,icu =3D <&icu 1>; + }; + + dmac3: dma-controller@12000000 { + compatible =3D "renesas,r9a09g057-dmac"; + reg =3D <0 0x12000000 0 0x10000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks =3D <&cpg CPG_MOD 0x3>; + power-domains =3D <&cpg>; + resets =3D <&cpg 0x34>; + #dma-cells =3D <1>; + dma-channels =3D <16>; + renesas,icu =3D <&icu 2>; + }; + + dmac4: dma-controller@12010000 { + compatible =3D "renesas,r9a09g057-dmac"; + reg =3D <0 0x12010000 0 0x10000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks =3D <&cpg CPG_MOD 0x4>; + power-domains =3D <&cpg>; + resets =3D <&cpg 0x35>; + #dma-cells =3D <1>; + dma-channels =3D <16>; + renesas,icu =3D <&icu 3>; + }; + ostm0: timer@11800000 { compatible =3D "renesas,r9a09g057-ostm", "renesas,ostm"; reg =3D <0x0 0x11800000 0x0 0x1000>; --=20 2.34.1