From nobody Tue Feb 10 05:48:33 2026 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE18027CB00; Tue, 22 Apr 2025 12:01:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745323280; cv=none; b=kCwkeCnewpFweWOOnupWXzk8pSn+vwNXo9EjorEEPDWXRLrqUw+L15SvjmIbUrPLNl7REDI3vghC0wJZ71xZ3uF51+p6j64fC3ThIkLHD+7jHxOrzDpdzYdeDDM4oow2HIRqc7Rh/WYT53JcmELyDpExEQf9ntAbLQlwsgxhgmE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745323280; c=relaxed/simple; bh=OJqlIGXDMUHd6a8BultHwtYcsW69GfJT3MGT6Ip1mac=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Kp6cNJ+dc+dg4Gd88DsHk50/3czrGiWhJya4NNVE82d+XJMukphqpOAsAcvsklqHKHo8sJVIpn2NXRe/4yt/4T6Vm2VoNjGGiU2rwIaEq3b7pweIr6H8zmi6enk5qRuOwn+PMFzQzawEJ8p/BNfG8kzqwl07p36wiuTvWK/y3LU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=wpChS8Wf; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="wpChS8Wf" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 53MC1DNn1206468 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 22 Apr 2025 07:01:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1745323273; bh=tZ/tDli0UVdGhUBUbsWxOnKadhDMEs3cC/lGhTcqtyQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=wpChS8WfJBroFySmZ7bUughF+8cVTfyhOkfw/C5NGSC6irLfLy7ro/mPXTiZEBPnq 4aE3FNCQWeXi2r1x1pRWgcZWrV41qhYMguCkV4Z8u5yjDawAGEjGIQkSwaqJBOlxPE ClkebCwGYqM3bTRTXo5JXXA/iElA9WJPVdmaTeuw= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 53MC1D17000443 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Apr 2025 07:01:13 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 22 Apr 2025 07:01:13 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 22 Apr 2025 07:01:13 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.113]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53MC0hW4094623; Tue, 22 Apr 2025 07:01:09 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [PATCH v2 7/7] arm64: dts: ti: k3-j784s4-j742s2-main-common: switch to 64-bit address space for PCIe0 and PCIe1 Date: Tue, 22 Apr 2025 17:30:42 +0530 Message-ID: <20250422120042.3746004-8-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250422120042.3746004-1-s-vadapalli@ti.com> References: <20250422120042.3746004-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The PCIe0 and PCIe1 instances of PCIe in J742S2 and J784S4 SoCs support: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar --- Link to v1 patch: https://lore.kernel.org/r/20250417120407.2646929-8-s-vadapalli@ti.com/ Changes since v1: - Based on Udit's feedback and offline discussion as described at: https://lore.kernel.org/r/7f6ea98c-df6d-4c94-8f42-76cc8306b6c4@ti.com/ the address region of 4 GB is split as: 0. 4 KB ECAM 1. 1 MB IO 2. (4 GB - 1 MB - 4 KB) 32-bit Non-Prefetchable MEM instead of the previous split of: 0. 4 KB ECAM 1. 1 MB IO 2. 128 MB 32-bit Non-Prefetchable MEM 3. (4 GB - 129 MB - 4 KB) 64-bit Prefetchable MEM Regards, Siddharth. .../boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arc= h/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index 1944616ab357..e6c9080d80b0 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -1055,7 +1055,7 @@ pcie0_rc: pcie@2900000 { reg =3D <0x00 0x02900000 0x00 0x1000>, <0x00 0x02907000 0x00 0x400>, <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x10000000 0x00 0x00001000>; + <0x40 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ reg-names =3D "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names =3D "link_state"; interrupts =3D ; @@ -1073,8 +1073,8 @@ pcie0_rc: pcie@2900000 { device-id =3D <0xb012>; msi-map =3D <0x0 &gic_its 0x0 0x10000>; dma-coherent; - ranges =3D <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, - <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; + ranges =3D <0x01000000 0x00 0x00001000 0x40 0x00001000 0x00 0x00100000>,= /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x40 0x00101000 0x00 0xffeff000>; /* 32-bi= t Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ dma-ranges =3D <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; status =3D "disabled"; }; @@ -1084,7 +1084,7 @@ pcie1_rc: pcie@2910000 { reg =3D <0x00 0x02910000 0x00 0x1000>, <0x00 0x02917000 0x00 0x400>, <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x00001000>; + <0x41 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ reg-names =3D "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names =3D "link_state"; interrupts =3D ; @@ -1102,8 +1102,8 @@ pcie1_rc: pcie@2910000 { device-id =3D <0xb012>; msi-map =3D <0x0 &gic_its 0x10000 0x10000>; dma-coherent; - ranges =3D <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + ranges =3D <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>,= /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bi= t Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ dma-ranges =3D <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; status =3D "disabled"; }; --=20 2.34.1