From nobody Tue Dec 16 00:31:06 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABFE1175D47; Tue, 22 Apr 2025 12:01:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745323262; cv=none; b=moqGgK0OpPMi6kISW0r3Ep08M+HZYFzh70LEeepQz2WZgVyJN2oOjAqX0syeuSpNN8XTPeoY7D6oUSV6y+NBmVdLLACEXSJ8A+E2sx6GyI3CjF4EesWaL6rIzGSi64n9keTpguTlpjg1ejZ+iTy2S9DoPdtd2+pFbExDhEhpC50= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745323262; c=relaxed/simple; bh=ZTgWFtWz2Suav/XQmWVnooOD0s2/jhBF1FyGkNT4UNk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=CyaOhJ06Lu/jpdtbLzZq0HQ+bkETK1gDiJuWPzb7QXQVxCFcMobr6zcmPrfH04SY0YzZIRqiV/p7z1j1WOc0vzLH0+SDalc4ltruevmOcBFNzWhMd4/l+FxY62ifdAAJdTysBuIp+l7LI53hskHAKI5Ok1UHI7JuZRirpHe+2NY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=bDKfRohH; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="bDKfRohH" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 53MC0td41206376 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 22 Apr 2025 07:00:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1745323255; bh=nSYnp43NmutNUwP4lbG1E4YOAzqQ1MUBKR7/QGJucII=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=bDKfRohHVPF+28Krv3kzeqb6Co9zlOrJELU/6VM2/rmiHGB3hkClxcBDvYkccPBRT DZAz/ig9qSKlO7zi0R3xPyfO+gruqx6PdpJ6KuWvCEIQ/TprNe+y6kY91a2FkaG/UR 1bwyesYxmiRSzH3Lb5jmVSbVi59r3xr8uXPF2jts= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 53MC0tMJ024976 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Apr 2025 07:00:55 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 22 Apr 2025 07:00:54 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 22 Apr 2025 07:00:54 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.113]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53MC0hVx094623; Tue, 22 Apr 2025 07:00:51 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [PATCH v2 2/7] arm64: dts: ti: k3-j7200-main: switch to 64-bit address space for PCIe1 Date: Tue, 22 Apr 2025 17:30:37 +0530 Message-ID: <20250422120042.3746004-3-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250422120042.3746004-1-s-vadapalli@ti.com> References: <20250422120042.3746004-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The PCIe0 instance of PCIe in J7200 SoC supports: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli --- Link to v1 patch: https://lore.kernel.org/r/20250417120407.2646929-3-s-vadapalli@ti.com/ Changes since v1: - Based on Udit's feedback and offline discussion as described at: https://lore.kernel.org/r/7f6ea98c-df6d-4c94-8f42-76cc8306b6c4@ti.com/ the address region of 4 GB is split as: 0. 4 KB ECAM 1. 1 MB IO 2. (4 GB - 1 MB - 4 KB) 32-bit Non-Prefetchable MEM instead of the previous split of: 0. 4 KB ECAM 1. 1 MB IO 2. 128 MB 32-bit Non-Prefetchable MEM 3. (4 GB - 129 MB - 4 KB) 64-bit Prefetchable MEM Regards, Siddharth. arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j7200-main.dtsi index 5ab510a0605f..21c3e574277c 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -759,7 +759,7 @@ pcie1_rc: pcie@2910000 { reg =3D <0x00 0x02910000 0x00 0x1000>, <0x00 0x02917000 0x00 0x400>, <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x00001000>; + <0x41 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ reg-names =3D "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names =3D "link_state"; interrupts =3D ; @@ -778,8 +778,8 @@ pcie1_rc: pcie@2910000 { device-id =3D <0xb00f>; msi-map =3D <0x0 &gic_its 0x0 0x10000>; dma-coherent; - ranges =3D <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + ranges =3D <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>,= /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bi= t Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ dma-ranges =3D <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; status =3D "disabled"; }; --=20 2.34.1