From nobody Sun Dec 14 19:13:16 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB30927CCED; Tue, 22 Apr 2025 12:01:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745323270; cv=none; b=fCWO6SkHMomzcXLVbgdFav7Eq+bayZ2VJBmwiI5DT3o4Ym/c6Kc4/VBcHDJT4KsYh9Wx3MfJNP5Bkx0MDuMoywVs2xGyG5uclxW7fVVkeAbtYNTo+KQWIMXTo4RD+qIncYMYEIyETJVTb7aqPUwfKMnazs1/27YCacNx0Exd2mA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745323270; c=relaxed/simple; bh=dgcUu/itwJyJNZKWj/PhqbFq3Ag/DF/lqGAW3FOTdjo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=bO5ZT4i7Ucw3xCyC5cO1T77n5XQyWBMalqCc5Ed4N8zEV4t3+X+QVTBx1cHm4NpbuksrBW12mxAQKizP9pWj1AmTtwXcr3bO8VHmmKvxRSUtIGuD08g5Mwt+kQk9u0dn17uu8zzDAjeNmW2FV857gxWg7r/y5Vgcu063tmbUNlw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=RWErh6Ld; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="RWErh6Ld" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 53MC0pEx1886355 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 22 Apr 2025 07:00:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1745323251; bh=ioPQ6GrujZDzKGHjQrit9JMcZgfR+0VvUBfS1eBdb7I=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=RWErh6LdTWxwSw89+l1mUSf9qUMGCYq7hEbEOZyY4RLNjtn2Hbhk+D7lYYVmG5JSa 1S7jgAoT8XKeB4ZdsP5MioehEu0/Y8LR/V0koZJJeWcpqjehLainllOnphOV47V87L lW4AcKTe48QWghvKHcPidWAVtvuIxMXpwK/FfFWM= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 53MC0peB024936 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Apr 2025 07:00:51 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 22 Apr 2025 07:00:50 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 22 Apr 2025 07:00:50 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.113]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53MC0hVw094623; Tue, 22 Apr 2025 07:00:47 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [PATCH v2 1/7] arm64: dts: ti: k3-am64-main: switch to 64-bit address space for PCIe0 Date: Tue, 22 Apr 2025 17:30:36 +0530 Message-ID: <20250422120042.3746004-2-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250422120042.3746004-1-s-vadapalli@ti.com> References: <20250422120042.3746004-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The PCIe0 instance of PCIe in AM64 SoC supports: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar --- Link to v1 patch: https://lore.kernel.org/r/20250417120407.2646929-2-s-vadapalli@ti.com/ Changes since v1: - Based on Udit's feedback and offline discussion as described at: https://lore.kernel.org/r/7f6ea98c-df6d-4c94-8f42-76cc8306b6c4@ti.com/ the address region of 4 GB is split as: 0. 4 KB ECAM 1. 1 MB IO 2. (4 GB - 1 MB - 4 KB) 32-bit Non-Prefetchable MEM instead of the previous split of: 0. 4 KB ECAM 1. 1 MB IO 2. 128 MB 32-bit Non-Prefetchable MEM 3. (4 GB - 129 MB - 4 KB) 64-bit Prefetchable MEM Regards, Siddharth. arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am64-main.dtsi index 324eb44c258d..a22295ab4f9e 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -1031,7 +1031,7 @@ pcie0_rc: pcie@f102000 { reg =3D <0x00 0x0f102000 0x00 0x1000>, <0x00 0x0f100000 0x00 0x400>, <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x68000000 0x00 0x00001000>; + <0x06 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ reg-names =3D "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names =3D "link_state"; interrupts =3D ; @@ -1049,8 +1049,8 @@ pcie0_rc: pcie@f102000 { vendor-id =3D <0x104c>; device-id =3D <0xb010>; msi-map =3D <0x0 &gic_its 0x0 0x10000>; - ranges =3D <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, - <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; + ranges =3D <0x01000000 0x00 0x00001000 0x06 0x00001000 0x00 0x00100000>,= /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x06 0x00101000 0x00 0xffeff000>; /* 32-bi= t Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ dma-ranges =3D <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; status =3D "disabled"; }; --=20 2.34.1 From nobody Sun Dec 14 19:13:16 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABFE1175D47; Tue, 22 Apr 2025 12:01:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745323262; cv=none; b=moqGgK0OpPMi6kISW0r3Ep08M+HZYFzh70LEeepQz2WZgVyJN2oOjAqX0syeuSpNN8XTPeoY7D6oUSV6y+NBmVdLLACEXSJ8A+E2sx6GyI3CjF4EesWaL6rIzGSi64n9keTpguTlpjg1ejZ+iTy2S9DoPdtd2+pFbExDhEhpC50= ARC-Message-Signature: i=1; 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Tue, 22 Apr 2025 07:00:54 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.113]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53MC0hVx094623; Tue, 22 Apr 2025 07:00:51 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [PATCH v2 2/7] arm64: dts: ti: k3-j7200-main: switch to 64-bit address space for PCIe1 Date: Tue, 22 Apr 2025 17:30:37 +0530 Message-ID: <20250422120042.3746004-3-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250422120042.3746004-1-s-vadapalli@ti.com> References: <20250422120042.3746004-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The PCIe0 instance of PCIe in J7200 SoC supports: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar --- Link to v1 patch: https://lore.kernel.org/r/20250417120407.2646929-3-s-vadapalli@ti.com/ Changes since v1: - Based on Udit's feedback and offline discussion as described at: https://lore.kernel.org/r/7f6ea98c-df6d-4c94-8f42-76cc8306b6c4@ti.com/ the address region of 4 GB is split as: 0. 4 KB ECAM 1. 1 MB IO 2. (4 GB - 1 MB - 4 KB) 32-bit Non-Prefetchable MEM instead of the previous split of: 0. 4 KB ECAM 1. 1 MB IO 2. 128 MB 32-bit Non-Prefetchable MEM 3. (4 GB - 129 MB - 4 KB) 64-bit Prefetchable MEM Regards, Siddharth. arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j7200-main.dtsi index 5ab510a0605f..21c3e574277c 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -759,7 +759,7 @@ pcie1_rc: pcie@2910000 { reg =3D <0x00 0x02910000 0x00 0x1000>, <0x00 0x02917000 0x00 0x400>, <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x00001000>; + <0x41 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ reg-names =3D "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names =3D "link_state"; interrupts =3D ; @@ -778,8 +778,8 @@ pcie1_rc: pcie@2910000 { device-id =3D <0xb00f>; msi-map =3D <0x0 &gic_its 0x0 0x10000>; dma-coherent; - ranges =3D <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; 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Tue, 22 Apr 2025 07:00:58 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.113]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53MC0hW0094623; Tue, 22 Apr 2025 07:00:54 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [PATCH v2 3/7] arm64: dts: ti: k3-j721e: add ranges for PCIe0 DAT1 and PCIe1 DAT1 Date: Tue, 22 Apr 2025 17:30:38 +0530 Message-ID: <20250422120042.3746004-4-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250422120042.3746004-1-s-vadapalli@ti.com> References: <20250422120042.3746004-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The PCIe0 DAT1 and PCIe1 DAT1 are 4 GB address regions in the 64-bit address space of the respective PCIe Controllers. Hence, update the ranges to include them. Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar --- Link to v1 patch: https://lore.kernel.org/r/20250417120407.2646929-4-s-vadapalli@ti.com/ Changes since v1: - Fixed the 'ranges' to set the size as 4 GB instead of the incorrect value of 128 MB. Regards, Siddharth. arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/= k3-j721e.dtsi index a7f2f52f42f7..b6e22c242951 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -126,6 +126,8 @@ cbass_main: bus@100000 { <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */ <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ + <0x40 0x00000000 0x40 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */ + <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */ <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */ <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ --=20 2.34.1 From nobody Sun Dec 14 19:13:16 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC33827D762; Tue, 22 Apr 2025 12:01:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745323270; cv=none; b=ahpnoxT5R0nM2czrNU8VrLVByG48aziO9M44gm2fSfOPOUTtcOxi9wcMydVks/V9I+eAUMhJONAwcjd6HvIUU/hzY0Hj8jtGSAJzFkkPqyPMKkkqUqbui2j0dJIOY5V/2YTk4pCDp/UJNklMOhokvhp3xO12+d0uB3TNjwuVT6Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745323270; c=relaxed/simple; bh=1LJwDGir4d4FIfgt0EClLQbg+PdB6dGMUIsmo2Zr14I=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pXOFQ1KWoBrsb6SlA5uHDFbeDe3Vi5teOJ2pM6oB501Ki/LDU/lNnweRv0jZL4rODvOUGSWwbRKrnoBmt/vlEibaODv0spSPoHe7aPTYEQlXThldvZmUIBnWZok4naWrNVeqrtSZRAGyLSeI2j2+zE1jfKA/auR+6XucUGEjzmE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=cl89CAyn; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="cl89CAyn" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 53MC12w81886392 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 22 Apr 2025 07:01:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1745323262; bh=jIeV8CRx1+lCd8420TzH+2CKzwgmxlhGYdd/TGwwqTs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=cl89CAyn1Rxs2JMXwh19Qkox/SNipWMYv02e/Kkyma9AOO9yzkSp+EbWmJdilo1Ss 95Nh1cWG8t1oedojkxEysiQ4tzhs82qTx+6yC8RU8Isn08H4d5pied5ks0o0g5amm0 hhznLfoUPcbPETuF74ljsW/gRmF0o7sjyG6U9p1I= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 53MC12Mf128164 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Apr 2025 07:01:02 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 22 Apr 2025 07:01:01 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 22 Apr 2025 07:01:01 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.113]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53MC0hW1094623; Tue, 22 Apr 2025 07:00:58 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [PATCH v2 4/7] arm64: dts: ti: k3-j721e-main: switch to 64-bit address space for PCIe0 and PCIe1 Date: Tue, 22 Apr 2025 17:30:39 +0530 Message-ID: <20250422120042.3746004-5-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250422120042.3746004-1-s-vadapalli@ti.com> References: <20250422120042.3746004-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The PCIe0 and PCIe1 instances of PCIe in J721E SoC support: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar --- Link to v1 patch: https://lore.kernel.org/r/20250417120407.2646929-5-s-vadapalli@ti.com/ Changes since v1: - Based on Udit's feedback and offline discussion as described at: https://lore.kernel.org/r/7f6ea98c-df6d-4c94-8f42-76cc8306b6c4@ti.com/ the address region of 4 GB is split as: 0. 4 KB ECAM 1. 1 MB IO 2. (4 GB - 1 MB - 4 KB) 32-bit Non-Prefetchable MEM instead of the previous split of: 0. 4 KB ECAM 1. 1 MB IO 2. 128 MB 32-bit Non-Prefetchable MEM 3. (4 GB - 129 MB - 4 KB) 64-bit Prefetchable MEM Regards, Siddharth. arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j721e-main.dtsi index af3d730154ac..6e1bd1dac6e5 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -941,7 +941,7 @@ pcie0_rc: pcie@2900000 { reg =3D <0x00 0x02900000 0x00 0x1000>, <0x00 0x02907000 0x00 0x400>, <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x10000000 0x00 0x00001000>; + <0x40 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ reg-names =3D "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names =3D "link_state"; interrupts =3D ; @@ -959,8 +959,8 @@ pcie0_rc: pcie@2900000 { device-id =3D <0xb00d>; msi-map =3D <0x0 &gic_its 0x0 0x10000>; dma-coherent; - ranges =3D <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, - <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; + ranges =3D <0x01000000 0x00 0x00001000 0x40 0x00001000 0x00 0x00100000>,= /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x40 0x00101000 0x00 0xffeff000>; /* 32-bi= t Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ dma-ranges =3D <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; status =3D "disabled"; }; @@ -970,7 +970,7 @@ pcie1_rc: pcie@2910000 { reg =3D <0x00 0x02910000 0x00 0x1000>, <0x00 0x02917000 0x00 0x400>, <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x00001000>; + <0x41 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ reg-names =3D "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names =3D "link_state"; interrupts =3D ; @@ -988,8 +988,8 @@ pcie1_rc: pcie@2910000 { device-id =3D <0xb00d>; msi-map =3D <0x0 &gic_its 0x10000 0x10000>; dma-coherent; - ranges =3D <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; + ranges =3D <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>,= /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; 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Tue, 22 Apr 2025 07:01:05 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.113]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53MC0hW2094623; Tue, 22 Apr 2025 07:01:02 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [PATCH v2 5/7] arm64: dts: ti: k3-j721s2-main: switch to 64-bit address space for PCIe1 Date: Tue, 22 Apr 2025 17:30:40 +0530 Message-ID: <20250422120042.3746004-6-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250422120042.3746004-1-s-vadapalli@ti.com> References: <20250422120042.3746004-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The PCIe1 instance of PCIe in J721S2 SoC supports: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar --- Link to v1 patch: https://lore.kernel.org/r/20250417120407.2646929-6-s-vadapalli@ti.com/ Changes since v1: - Based on Udit's feedback and offline discussion as described at: https://lore.kernel.org/r/7f6ea98c-df6d-4c94-8f42-76cc8306b6c4@ti.com/ the address region of 4 GB is split as: 0. 4 KB ECAM 1. 1 MB IO 2. (4 GB - 1 MB - 4 KB) 32-bit Non-Prefetchable MEM instead of the previous split of: 0. 4 KB ECAM 1. 1 MB IO 2. 128 MB 32-bit Non-Prefetchable MEM 3. (4 GB - 129 MB - 4 KB) 64-bit Prefetchable MEM Regards, Siddharth. arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 92bf48fdbeba..bfc7edf64764 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1394,7 +1394,7 @@ pcie1_rc: pcie@2910000 { reg =3D <0x00 0x02910000 0x00 0x1000>, <0x00 0x02917000 0x00 0x400>, <0x00 0x0d800000 0x00 0x800000>, - <0x00 0x18000000 0x00 0x1000>; + <0x41 0x00000000 0x00 0x1000>; /* ECAM (4 KB) */ reg-names =3D "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names =3D "link_state"; interrupts =3D ; @@ -1412,8 +1412,8 @@ pcie1_rc: pcie@2910000 { device-id =3D <0xb013>; msi-map =3D <0x0 &gic_its 0x0 0x10000>; dma-coherent; - ranges =3D <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; 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Tue, 22 Apr 2025 07:01:09 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.113]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53MC0hW3094623; Tue, 22 Apr 2025 07:01:06 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [PATCH v2 6/7] arm64: dts: ti: k3-j722s-main: switch to 64-bit address space for PCIe0 Date: Tue, 22 Apr 2025 17:30:41 +0530 Message-ID: <20250422120042.3746004-7-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250422120042.3746004-1-s-vadapalli@ti.com> References: <20250422120042.3746004-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The PCIe0 instance of PCIe in J722S SoC supports: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar --- Link to v1 patch: https://lore.kernel.org/r/20250417120407.2646929-7-s-vadapalli@ti.com/ Changes since v1: - Based on Udit's feedback and offline discussion as described at: https://lore.kernel.org/r/7f6ea98c-df6d-4c94-8f42-76cc8306b6c4@ti.com/ the address region of 4 GB is split as: 0. 4 KB ECAM 1. 1 MB IO 2. (4 GB - 1 MB - 4 KB) 32-bit Non-Prefetchable MEM instead of the previous split of: 0. 4 KB ECAM 1. 1 MB IO 2. 128 MB 32-bit Non-Prefetchable MEM 3. (4 GB - 129 MB - 4 KB) 64-bit Prefetchable MEM Regards, Siddharth. arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j722s-main.dtsi index 6850f50530f1..da22988ff9db 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -98,10 +98,10 @@ pcie0_rc: pcie@f102000 { reg =3D <0x00 0x0f102000 0x00 0x1000>, <0x00 0x0f100000 0x00 0x400>, <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x68000000 0x00 0x00001000>; + <0x06 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ reg-names =3D "intd_cfg", "user_cfg", "reg", "cfg"; - ranges =3D <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, - <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; + ranges =3D <0x01000000 0x00 0x00001000 0x06 0x00001000 0x00 0x00100000>,= /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x06 0x00101000 0x00 0xffeff000>; /* 32-bi= t Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ dma-ranges =3D <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 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Tue, 22 Apr 2025 07:01:13 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 22 Apr 2025 07:01:13 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 22 Apr 2025 07:01:13 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.113]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 53MC0hW4094623; Tue, 22 Apr 2025 07:01:09 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , Subject: [PATCH v2 7/7] arm64: dts: ti: k3-j784s4-j742s2-main-common: switch to 64-bit address space for PCIe0 and PCIe1 Date: Tue, 22 Apr 2025 17:30:42 +0530 Message-ID: <20250422120042.3746004-8-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250422120042.3746004-1-s-vadapalli@ti.com> References: <20250422120042.3746004-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The PCIe0 and PCIe1 instances of PCIe in J742S2 and J784S4 SoCs support: 1. 128 MB address region in the 32-bit address space 2. 4 GB address region in the 64-bit address space The default configuration is that of a 128 MB address region in the 32-bit address space. While this might be sufficient for most use-cases, it is insufficient for supporting use-cases which require larger address spaces. Therefore, switch to using the 64-bit address space with a 4 GB address region. Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar --- Link to v1 patch: https://lore.kernel.org/r/20250417120407.2646929-8-s-vadapalli@ti.com/ Changes since v1: - Based on Udit's feedback and offline discussion as described at: https://lore.kernel.org/r/7f6ea98c-df6d-4c94-8f42-76cc8306b6c4@ti.com/ the address region of 4 GB is split as: 0. 4 KB ECAM 1. 1 MB IO 2. (4 GB - 1 MB - 4 KB) 32-bit Non-Prefetchable MEM instead of the previous split of: 0. 4 KB ECAM 1. 1 MB IO 2. 128 MB 32-bit Non-Prefetchable MEM 3. (4 GB - 129 MB - 4 KB) 64-bit Prefetchable MEM Regards, Siddharth. .../boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arc= h/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi index 1944616ab357..e6c9080d80b0 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi @@ -1055,7 +1055,7 @@ pcie0_rc: pcie@2900000 { reg =3D <0x00 0x02900000 0x00 0x1000>, <0x00 0x02907000 0x00 0x400>, <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x10000000 0x00 0x00001000>; + <0x40 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ reg-names =3D "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names =3D "link_state"; interrupts =3D ; @@ -1073,8 +1073,8 @@ pcie0_rc: pcie@2900000 { device-id =3D <0xb012>; msi-map =3D <0x0 &gic_its 0x0 0x10000>; dma-coherent; - ranges =3D <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, - <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; + ranges =3D <0x01000000 0x00 0x00001000 0x40 0x00001000 0x00 0x00100000>,= /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x40 0x00101000 0x00 0xffeff000>; /* 32-bi= t Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ dma-ranges =3D <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; status =3D "disabled"; }; @@ -1084,7 +1084,7 @@ pcie1_rc: pcie@2910000 { reg =3D <0x00 0x02910000 0x00 0x1000>, <0x00 0x02917000 0x00 0x400>, <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x00001000>; + <0x41 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */ reg-names =3D "intd_cfg", "user_cfg", "reg", "cfg"; interrupt-names =3D "link_state"; interrupts =3D ; @@ -1102,8 +1102,8 @@ pcie1_rc: pcie@2910000 { device-id =3D <0xb012>; msi-map =3D <0x0 &gic_its 0x10000 0x10000>; dma-coherent; - ranges =3D <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, - <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + ranges =3D <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>,= /* IO (1 MB) */ + <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bi= t Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */ dma-ranges =3D <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; status =3D "disabled"; }; --=20 2.34.1