From nobody Tue Feb 10 05:17:07 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CA6FF20E026; Tue, 22 Apr 2025 11:29:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745321360; cv=none; b=K3KwGC4wFxBeRE7vUPxfjSg8wNlybpfbFcIMSlwlHBdm5OUZk84hvELhgji7P712oADTemawiI4iSGRAJS6vl+CcjU+9V+eXxxtItTAr1ah6WQkJViqxy70i0kYHSO+7wcVWeGbN9BiNYA50nqW69P2OsqGhMoUWo971I93tXaI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745321360; c=relaxed/simple; bh=IvGEQNUceeg6xRYk8HLHokwv2utpLMx7wJYj1ZZ4wLg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=b+AYxSyAdaKufQlrWsrncfgtfNHYIxrieWxsbRN8hhWrRQQ0OrQdAsKew8xlhgMWx9W8PmlPR3SWj6XSCn2eZ16q/DnRoLIdtcj9mmbhYRSK/iNrJ57IVri0u1eSSb4ql69zKs5HlMTi5KEfSrhmZQ2HoT/w4Z5ilh88v3dBN2Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=FvaKoOE9; arc=none smtp.client-ip=117.135.210.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="FvaKoOE9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=VWSzt ViPqdKr7S8pdiVILgmqXIuB8IOWVgCpwivvfjs=; b=FvaKoOE9clFUjj1xqwHP9 4EgdZdjMwiJWuZjYRoR1ccZoUitNhW/WDpLdVCKD/ya+vwIF2aOe0U95z3j3SnPl L72jFhmA1PGfR7EuQzvoGbGFh0ousUIgD1db9VDyED8L1hjajDd15u7LKWGIe9mQ nfdu3IM7rSjVJl7gX8x208= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-0 (Coremail) with SMTP id _____wCXbK1gfQdoRW2NBg--.44191S3; Tue, 22 Apr 2025 19:28:36 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, heiko@sntech.de Cc: manivannan.sadhasivam@linaro.org, robh@kernel.org, jingoohan1@gmail.com, shawn.lin@rock-chips.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Hans Zhang <18255117159@163.com> Subject: [PATCH 1/3] PCI: dw-rockchip: Remove unused PCIE_CLIENT_GENERAL_DEBUG Date: Tue, 22 Apr 2025 19:28:28 +0800 Message-Id: <20250422112830.204374-2-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250422112830.204374-1-18255117159@163.com> References: <20250422112830.204374-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wCXbK1gfQdoRW2NBg--.44191S3 X-Coremail-Antispam: 1Uf129KBjvdXoWruw1kCw48Gw15WrykXrW8WFg_yoWDtrbE9r yUuF4xXryDKrWSk392yw4xZFn0yas7ur1xGFZYgF4ava47Kr4rXry8ZrWrXa1DGr43JFWx t34vyF4rua4xJjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7sR_vtCUUUUUU== X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbBDwE3o2gHegppMQAAsd Content-Type: text/plain; charset="utf-8" The PCIE_CLIENT_GENERAL_DEBUG register offset is defined but never used in the driver. Its presence adds noise to the register map and may mislead future developers. Remove this redundant definition to keep the register list minimal and aligned with actual hardware usage. Signed-off-by: Hans Zhang <18255117159@163.com> Reviewed-by: Niklas Cassel --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index 0e0c09bafd63..fd5827bbfae3 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -54,7 +54,6 @@ #define PCIE_CLIENT_GENERAL_CONTROL 0x0 #define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 #define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c -#define PCIE_CLIENT_GENERAL_DEBUG 0x104 #define PCIE_CLIENT_HOT_RESET_CTRL 0x180 #define PCIE_CLIENT_LTSSM_STATUS 0x300 #define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) --=20 2.25.1