From nobody Mon Feb 9 05:19:20 2026 Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CA6FF20E026; Tue, 22 Apr 2025 11:29:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745321360; cv=none; b=K3KwGC4wFxBeRE7vUPxfjSg8wNlybpfbFcIMSlwlHBdm5OUZk84hvELhgji7P712oADTemawiI4iSGRAJS6vl+CcjU+9V+eXxxtItTAr1ah6WQkJViqxy70i0kYHSO+7wcVWeGbN9BiNYA50nqW69P2OsqGhMoUWo971I93tXaI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745321360; c=relaxed/simple; bh=IvGEQNUceeg6xRYk8HLHokwv2utpLMx7wJYj1ZZ4wLg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=b+AYxSyAdaKufQlrWsrncfgtfNHYIxrieWxsbRN8hhWrRQQ0OrQdAsKew8xlhgMWx9W8PmlPR3SWj6XSCn2eZ16q/DnRoLIdtcj9mmbhYRSK/iNrJ57IVri0u1eSSb4ql69zKs5HlMTi5KEfSrhmZQ2HoT/w4Z5ilh88v3dBN2Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=FvaKoOE9; arc=none smtp.client-ip=117.135.210.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="FvaKoOE9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=VWSzt ViPqdKr7S8pdiVILgmqXIuB8IOWVgCpwivvfjs=; b=FvaKoOE9clFUjj1xqwHP9 4EgdZdjMwiJWuZjYRoR1ccZoUitNhW/WDpLdVCKD/ya+vwIF2aOe0U95z3j3SnPl L72jFhmA1PGfR7EuQzvoGbGFh0ousUIgD1db9VDyED8L1hjajDd15u7LKWGIe9mQ nfdu3IM7rSjVJl7gX8x208= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-0 (Coremail) with SMTP id _____wCXbK1gfQdoRW2NBg--.44191S3; Tue, 22 Apr 2025 19:28:36 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, heiko@sntech.de Cc: manivannan.sadhasivam@linaro.org, robh@kernel.org, jingoohan1@gmail.com, shawn.lin@rock-chips.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Hans Zhang <18255117159@163.com> Subject: [PATCH 1/3] PCI: dw-rockchip: Remove unused PCIE_CLIENT_GENERAL_DEBUG Date: Tue, 22 Apr 2025 19:28:28 +0800 Message-Id: <20250422112830.204374-2-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250422112830.204374-1-18255117159@163.com> References: <20250422112830.204374-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wCXbK1gfQdoRW2NBg--.44191S3 X-Coremail-Antispam: 1Uf129KBjvdXoWruw1kCw48Gw15WrykXrW8WFg_yoWDtrbE9r yUuF4xXryDKrWSk392yw4xZFn0yas7ur1xGFZYgF4ava47Kr4rXry8ZrWrXa1DGr43JFWx t34vyF4rua4xJjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7sR_vtCUUUUUU== X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbBDwE3o2gHegppMQAAsd Content-Type: text/plain; charset="utf-8" The PCIE_CLIENT_GENERAL_DEBUG register offset is defined but never used in the driver. Its presence adds noise to the register map and may mislead future developers. Remove this redundant definition to keep the register list minimal and aligned with actual hardware usage. Signed-off-by: Hans Zhang <18255117159@163.com> Reviewed-by: Niklas Cassel --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index 0e0c09bafd63..fd5827bbfae3 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -54,7 +54,6 @@ #define PCIE_CLIENT_GENERAL_CONTROL 0x0 #define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 #define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c -#define PCIE_CLIENT_GENERAL_DEBUG 0x104 #define PCIE_CLIENT_HOT_RESET_CTRL 0x180 #define PCIE_CLIENT_LTSSM_STATUS 0x300 #define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) --=20 2.25.1 From nobody Mon Feb 9 05:19:20 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 36B29253F1F; Tue, 22 Apr 2025 11:29:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745321362; cv=none; b=EwJFax799ghwhS5K9Ha2mngF1KVqnQuZ00lAOUHp6oRHFbNQihhwVRmPZ6C6LSA6G0u8ST7f/sS7JSvCaJtn/8yKxrw5cyMssIAfG5Y0plwJwfG9pwbuPBl/c/kRA6hoeWhxb5Mkwa6uh4jXieVoYMwk6F+9V9VxVcKUpfgTTds= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745321362; c=relaxed/simple; bh=J0oq7i7+aOrHk41A4h85D/OoJCN2A5trbCjlIZf4VXc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=US6nfgxgYYr75H93Mgg94Xx3v8LiD9pXO/9GPBUgpL9VuLtXOKZHhdcxIRg94tHf6gJ7o69H70wKuyK9yzyQyh7z6FednxlA+2gyB2zIdLwkQb/Ec4MqWO6yiV4Q2v0evY6TJv0na7uuPq4i5nI7rrUDkd/fW4D1KZ3sf3schs0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=L8dAlQh2; arc=none smtp.client-ip=220.197.31.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="L8dAlQh2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=2RWjK PWv82UStMG6NIWMhcWrtvVJa7KMbvU2NcwBt1g=; b=L8dAlQh2CfbwxNHys0yEf IyXb8FFHE7WoFP0CX+ElrJ4conoHMiQzEuzceikbUdiO40V85jXcw9JTz7gQKZm8 UsK5HBVt17CF/MUSs0GZrAiYAKsiN+gc3jp5g3GAxsFgYIO1qk2GX0kkf0HQOIBZ N7qC9KSp46kAG1aLsMUskU= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-0 (Coremail) with SMTP id _____wCXbK1gfQdoRW2NBg--.44191S4; Tue, 22 Apr 2025 19:28:37 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, heiko@sntech.de Cc: manivannan.sadhasivam@linaro.org, robh@kernel.org, jingoohan1@gmail.com, shawn.lin@rock-chips.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Hans Zhang <18255117159@163.com> Subject: [PATCH 2/3] PCI: dw-rockchip: Reorganize register and bitfield definitions Date: Tue, 22 Apr 2025 19:28:29 +0800 Message-Id: <20250422112830.204374-3-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250422112830.204374-1-18255117159@163.com> References: <20250422112830.204374-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wCXbK1gfQdoRW2NBg--.44191S4 X-Coremail-Antispam: 1Uf129KBjvJXoWxWFWxWryktw1DKF48uFyfJFb_yoW5Zrykpa 98AFyakrs8tayakwnYgF15AF17tF13KFWjgrsIg3yUu3Z5Aw18Gr18WF1Sgry7tr4kWrW3 uwn8Gw1xWF9xCrUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zEJ3kiUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbBDwU3o2gHegppMgABsb Content-Type: text/plain; charset="utf-8" Register definitions were scattered with ambiguous names (e.g., PCIE_RDLH_LINK_UP_CHGED in PCIE_CLIENT_INTR_STATUS_MISC) and lacked hierarchical grouping. Magic values for bit operations reduced code clarity. Group registers and their associated bitfields logically. This improves maintainability and aligns the code with hardware documentation. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 42 +++++++++++-------- 1 file changed, 24 insertions(+), 18 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index fd5827bbfae3..cdc8afc6cfc1 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -8,6 +8,7 @@ * Author: Simon Xue */ =20 +#include #include #include #include @@ -34,30 +35,35 @@ =20 #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev) =20 -#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40) -#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0) -#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc) -#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8) -#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x04 +#define PCIE_CLIENT_GENERAL_CONTROL 0x0 +#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40) +#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0) +#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc) +#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8) + +#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x4 +#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 + #define PCIE_CLIENT_INTR_STATUS_MISC 0x10 +#define PCIE_RDLH_LINK_UP_CHGED BIT(1) +#define PCIE_LINK_REQ_RST_NOT_INT BIT(2) + +#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c #define PCIE_CLIENT_INTR_MASK_MISC 0x24 + #define PCIE_CLIENT_POWER 0x2c +#define PME_READY_ENTER_L23 BIT(3) + #define PCIE_CLIENT_MSG_GEN 0x34 -#define PME_READY_ENTER_L23 BIT(3) -#define PME_TURN_OFF (BIT(4) | BIT(20)) -#define PME_TO_ACK (BIT(9) | BIT(25)) -#define PCIE_SMLH_LINKUP BIT(16) -#define PCIE_RDLH_LINKUP BIT(17) -#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) -#define PCIE_RDLH_LINK_UP_CHGED BIT(1) -#define PCIE_LINK_REQ_RST_NOT_INT BIT(2) -#define PCIE_CLIENT_GENERAL_CONTROL 0x0 -#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 -#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c +#define PME_TURN_OFF HIWORD_UPDATE_BIT(BIT(4)) +#define PME_TO_ACK HIWORD_UPDATE_BIT(BIT(9)) + #define PCIE_CLIENT_HOT_RESET_CTRL 0x180 +#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) + #define PCIE_CLIENT_LTSSM_STATUS 0x300 -#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) -#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) +#define PCIE_LINKUP_MASK GENMASK(17, 16) +#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0) =20 struct rockchip_pcie { struct dw_pcie pci; --=20 2.25.1 From nobody Mon Feb 9 05:19:20 2026 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C812627BF8E; Tue, 22 Apr 2025 11:29:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745321362; cv=none; b=IZpbkyMont/P7fvWJNDEEcISDqDxZob/uwKjJxW14QcTX+bjXm+Ptlca6AEcuI0WrJG8zGjOLPENx/+IltawxTRG9wCFQDQBCc8Qmux1jdSrGIuEJuEW68JvKuXUx/uSmNpd6uN4AczwJsyDPppfmDtoc7lzdFwUSijFfMBPak4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745321362; c=relaxed/simple; bh=UkHWEuBBr+u8ftNbMm92bUAY3+Nu0EQHSO4PpBia6Vc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=BooccKUcO+mwJdNWrbDd0oNC990snUjTlKBXGt4XD96MvWLww+Fy121a7B7Zc4MYbsn6vVFWcdG8E0eiV3DnAh7pMvrnlg8IpIoLUULnnzdGnv1S3YgZ6cHjwVnmF9zkXvo9i1hsmR4zHwih1zqWPLE/OVs4FJU2JqsOL3ajVZQ= ARC-Authentication-Results: i=1; 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Tue, 22 Apr 2025 19:28:38 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com, heiko@sntech.de Cc: manivannan.sadhasivam@linaro.org, robh@kernel.org, jingoohan1@gmail.com, shawn.lin@rock-chips.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Hans Zhang <18255117159@163.com> Subject: [PATCH 3/3] PCI: dw-rockchip: Unify link status checks with FIELD_GET Date: Tue, 22 Apr 2025 19:28:30 +0800 Message-Id: <20250422112830.204374-4-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250422112830.204374-1-18255117159@163.com> References: <20250422112830.204374-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wCXbK1gfQdoRW2NBg--.44191S5 X-Coremail-Antispam: 1Uf129KBjvJXoWxCF15Gr13CFWxtr1UZr18Zrb_yoW5XFyxpa 98AFWqkF48Gw409F1kCa98XrWFyFnI9ayUCrn7K3WxW3ZIyr1UW3WUWr9xtr4xJrs8CFy3 Cw4rta4xJF43ZrUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zRvdyUUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbBDwo3o2gHegppZgAAsB Content-Type: text/plain; charset="utf-8" Link-up detection manually checked PCIE_LINKUP bits across RC/EP modes, leading to code duplication. Centralize the logic using FIELD_GET. This removes redundancy and abstracts hardware-specific bit masking, ensuring consistent link state handling. Signed-off-by: Hans Zhang <18255117159@163.com> --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index cdc8afc6cfc1..2b26060af5c2 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -196,10 +196,7 @@ static int rockchip_pcie_link_up(struct dw_pcie *pci) struct rockchip_pcie *rockchip =3D to_rockchip_pcie(pci); u32 val =3D rockchip_pcie_get_ltssm(rockchip); =20 - if ((val & PCIE_LINKUP) =3D=3D PCIE_LINKUP) - return 1; - - return 0; + return FIELD_GET(PCIE_LINKUP_MASK, val) =3D=3D 3; } =20 static void rockchip_pcie_enable_l0s(struct dw_pcie *pci) @@ -499,7 +496,7 @@ static irqreturn_t rockchip_pcie_rc_sys_irq_thread(int = irq, void *arg) struct dw_pcie *pci =3D &rockchip->pci; struct dw_pcie_rp *pp =3D &pci->pp; struct device *dev =3D pci->dev; - u32 reg, val; + u32 reg; =20 reg =3D rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC); rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC); @@ -508,8 +505,7 @@ static irqreturn_t rockchip_pcie_rc_sys_irq_thread(int = irq, void *arg) dev_dbg(dev, "LTSSM_STATUS: %#x\n", rockchip_pcie_get_ltssm(rockchip)); =20 if (reg & PCIE_RDLH_LINK_UP_CHGED) { - val =3D rockchip_pcie_get_ltssm(rockchip); - if ((val & PCIE_LINKUP) =3D=3D PCIE_LINKUP) { + if (rockchip_pcie_link_up(pci)) { dev_dbg(dev, "Received Link up event. Starting enumeration!\n"); /* Rescan the bus to enumerate endpoint devices */ pci_lock_rescan_remove(); @@ -526,7 +522,7 @@ static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int = irq, void *arg) struct rockchip_pcie *rockchip =3D arg; struct dw_pcie *pci =3D &rockchip->pci; struct device *dev =3D pci->dev; - u32 reg, val; + u32 reg; =20 reg =3D rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC); rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC); @@ -540,8 +536,7 @@ static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int = irq, void *arg) } =20 if (reg & PCIE_RDLH_LINK_UP_CHGED) { - val =3D rockchip_pcie_get_ltssm(rockchip); - if ((val & PCIE_LINKUP) =3D=3D PCIE_LINKUP) { + if (rockchip_pcie_link_up(pci)) { dev_dbg(dev, "link up\n"); dw_pcie_ep_linkup(&pci->ep); } --=20 2.25.1