From nobody Mon Feb 9 21:40:25 2026 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45CCE25DB11; Tue, 22 Apr 2025 08:46:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745311571; cv=none; b=EXDaiU2K5e/VkeRDx3R+/RrURurL/McpqTd+5osTZK7kYsO2aS8CWzCJfCfpioO/DX7bR5slsvG7vdUaDR0jKF8Zr60HF029oJI8bKjNxkFiYVlInDZkrC4As8ZwYjwM5llsEgGKBgxpa10gt9+BKIsulRKcqommyiLJOUH7ue4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745311571; c=relaxed/simple; bh=Qp3waWXnZNeiib80C7SH4AHEY7KYDUl8d8nTGop8bG4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=aUWJBvMcnYZL5iCYXc+I1r3uFJBpejX4hPi4KTs1hCtUaEyd8GSo6e81R6wMi5kv9RW5fLXlVThHIklPFU8LAyyrMYG5mq3DPeDfxbrG0wLXuxg7gMeWiitIqIw37G3b7ycsKZ0sLQKbJEExqcPOfpeVUB03/zhCx4csAJF1AG0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=0ln5SLdT; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="0ln5SLdT" Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 53M7h5PF030641; Tue, 22 Apr 2025 10:45:55 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= mb7szTxe+O4/YlWD5eNPv4K70cyMKU44+b4hZfrYsbU=; b=0ln5SLdTrrAmb9eE o1tFddmhV6Mj7aTK7ukQQNB75I3L1f/EmJqONt1xFoPB60c8cnnw6CT2ewJ80eSI xiLwP10GsHZNI3ElgPeA0w1Su7q5B4vrV/IPBLKAA+1QNaBmwpDPfbwEYVsGtbLX JVVh9jsxnf5kQjAJD97V0TKZjZALXOHagp6UCC5m6PwWZFON1OKndRmtzeHolh2O g466JJyI9aCD8lMQ+tm4pK5ZizCZlRBzhXuXIHCZ/zhaAz1Xbu9Z2JMxYQ3hkThb mXCWnqrFgsYR+iwWbBfZrkcepTalt+/zzRJKL94EZB3u6vzc2SznTRrcOIL/uuUc WUa3Fw== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 4642qg8xux-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 22 Apr 2025 10:45:54 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 72BCF4002D; Tue, 22 Apr 2025 10:44:53 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 1506A9D8729; Tue, 22 Apr 2025 10:44:04 +0200 (CEST) Received: from localhost (10.48.87.62) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 22 Apr 2025 10:44:03 +0200 From: Patrice Chotard Date: Tue, 22 Apr 2025 10:44:00 +0200 Subject: [PATCH v10 1/3] dt-bindings: memory-controllers: Add STM32 Octo Memory Manager controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250422-upstream_ospi_v6-v10-1-6f4942a04e10@foss.st.com> References: <20250422-upstream_ospi_v6-v10-0-6f4942a04e10@foss.st.com> In-Reply-To: <20250422-upstream_ospi_v6-v10-0-6f4942a04e10@foss.st.com> To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Krzysztof Kozlowski , Catalin Marinas , Will Deacon CC: , , , , , Patrice Chotard X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-22_04,2025-04-21_02,2024-11-22_01 Add bindings for STM32 Octo Memory Manager (OMM) controller. OMM manages: - the muxing between 2 OSPI busses and 2 output ports. There are 4 possible muxing configurations: - direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2 output is on port 2 - OSPI1 and OSPI2 are multiplexed over the same output port 1 - swapped mode (no multiplexing), OSPI1 output is on port 2, OSPI2 output is on port 1 - OSPI1 and OSPI2 are multiplexed over the same output port 2 - the split of the memory area shared between the 2 OSPI instances. - chip select selection override. - the time between 2 transactions in multiplexed mode. Signed-off-by: Patrice Chotard Reviewed-by: Rob Herring (Arm) --- .../memory-controllers/st,stm32mp25-omm.yaml | 226 +++++++++++++++++= ++++ 1 file changed, 226 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32m= p25-omm.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm3= 2mp25-omm.yaml new file mode 100644 index 0000000000000000000000000000000000000000..344878db88188f5df5f9ee42633= 5bed38a8fac5c --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32mp25-omm= .yaml @@ -0,0 +1,226 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/st,stm32mp25-omm.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32 Octo Memory Manager (OMM) + +maintainers: + - Patrice Chotard + +description: | + The STM32 Octo Memory Manager is a low-level interface that enables an + efficient OCTOSPI pin assignment with a full I/O matrix (before alternate + function map) and multiplex of single/dual/quad/octal SPI interfaces over + the same bus. It Supports up to: + - Two single/dual/quad/octal SPI interfaces + - Two ports for pin assignment + +properties: + compatible: + const: st,stm32mp25-omm + + "#address-cells": + const: 2 + + "#size-cells": + const: 1 + + ranges: + description: | + Reflects the memory layout per OSPI instance. + Format: + 0 + minItems: 2 + maxItems: 2 + + reg: + items: + - description: OMM registers + - description: OMM memory map area + + reg-names: + items: + - const: regs + - const: memory_map + + memory-region: + description: + Memory region shared between the 2 OCTOSPI instance. + One or two phandle to a node describing a memory mapped region + depending of child number. + minItems: 1 + maxItems: 2 + + memory-region-names: + description: + Identify to which OSPI instance the memory region belongs to. + items: + enum: [ospi1, ospi2] + minItems: 1 + maxItems: 2 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: omm + - const: ospi1 + - const: ospi2 + + resets: + maxItems: 3 + + reset-names: + items: + - const: omm + - const: ospi1 + - const: ospi2 + + access-controllers: + maxItems: 1 + + power-domains: + maxItems: 1 + + st,syscfg-amcr: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + The Address Mapping Control Register (AMCR) is used to split the 256= MB + memory map area shared between the 2 OSPI instance. The Octo Memory + Manager sets the AMCR depending of the memory-region configuration. + The memory split bitmask description is: + - 000: OCTOSPI1 (256 Mbytes), OCTOSPI2 unmapped + - 001: OCTOSPI1 (192 Mbytes), OCTOSPI2 (64 Mbytes) + - 010: OCTOSPI1 (128 Mbytes), OCTOSPI2 (128 Mbytes) + - 011: OCTOSPI1 (64 Mbytes), OCTOSPI2 (192 Mbytes) + - 1xx: OCTOSPI1 unmapped, OCTOSPI2 (256 Mbytes) + items: + - items: + - description: phandle to syscfg + - description: register offset within syscfg + - description: register bitmask for memory split + + st,omm-req2ack-ns: + description: + In multiplexed mode (MUXEN =3D 1), this field defines the time in + nanoseconds between two transactions. + default: 0 + + st,omm-cssel-ovr: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Configure the chip select selector override for the 2 OCTOSPIs. + - 0: OCTOSPI1 chip select send to NCS1 OCTOSPI2 chip select send to = NCS1 + - 1: OCTOSPI1 chip select send to NCS2 OCTOSPI2 chip select send to = NCS1 + - 2: OCTOSPI1 chip select send to NCS1 OCTOSPI2 chip select send to = NCS2 + - 3: OCTOSPI1 chip select send to NCS2 OCTOSPI2 chip select send to = NCS2 + minimum: 0 + maximum: 3 + default: 0 + + st,omm-mux: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Configure the muxing between the 2 OCTOSPIs busses and the 2 output = ports. + - 0: direct mode + - 1: mux OCTOSPI1 and OCTOSPI2 to port 1 + - 2: swapped mode + - 3: mux OCTOSPI1 and OCTOSPI2 to port 2 + minimum: 0 + maximum: 3 + default: 0 + +patternProperties: + ^spi@[0-9]: + type: object + $ref: /schemas/spi/st,stm32mp25-ospi.yaml# + description: Required spi child node + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - clocks + - clock-names + - resets + - reset-names + - st,syscfg-amcr + - ranges + +additionalProperties: false + +examples: + - | + #include + #include + #include + ommanager@40500000 { + compatible =3D "st,stm32mp25-omm"; + reg =3D <0x40500000 0x400>, <0x60000000 0x10000000>; + reg-names =3D "regs", "memory_map"; + ranges =3D <0 0 0x40430000 0x400>, + <1 0 0x40440000 0x400>; + memory-region =3D <&mm_ospi1>, <&mm_ospi2>; + memory-region-names =3D "ospi1", "ospi2"; + pinctrl-0 =3D <&ospi_port1_clk_pins_a + &ospi_port1_io03_pins_a + &ospi_port1_cs0_pins_a>; + pinctrl-1 =3D <&ospi_port1_clk_sleep_pins_a + &ospi_port1_io03_sleep_pins_a + &ospi_port1_cs0_sleep_pins_a>; + pinctrl-names =3D "default", "sleep"; + clocks =3D <&rcc CK_BUS_OSPIIOM>, + <&scmi_clk CK_SCMI_OSPI1>, + <&scmi_clk CK_SCMI_OSPI2>; + clock-names =3D "omm", "ospi1", "ospi2"; + resets =3D <&rcc OSPIIOM_R>, + <&scmi_reset RST_SCMI_OSPI1>, + <&scmi_reset RST_SCMI_OSPI2>; + reset-names =3D "omm", "ospi1", "ospi2"; + access-controllers =3D <&rifsc 111>; + power-domains =3D <&CLUSTER_PD>; + #address-cells =3D <2>; + #size-cells =3D <1>; + st,syscfg-amcr =3D <&syscfg 0x2c00 0x7>; + st,omm-req2ack-ns =3D <0>; + st,omm-mux =3D <0>; + st,omm-cssel-ovr =3D <0>; + + spi@0 { + compatible =3D "st,stm32mp25-ospi"; + reg =3D <0 0 0x400>; + memory-region =3D <&mm_ospi1>; + interrupts =3D ; + dmas =3D <&hpdma 2 0x62 0x00003121 0x0>, + <&hpdma 2 0x42 0x00003112 0x0>; + dma-names =3D "tx", "rx"; + clocks =3D <&scmi_clk CK_SCMI_OSPI1>; + resets =3D <&scmi_reset RST_SCMI_OSPI1>, <&scmi_reset RST_SCMI_OSP= I1DLL>; + access-controllers =3D <&rifsc 74>; + power-domains =3D <&CLUSTER_PD>; + #address-cells =3D <1>; + #size-cells =3D <0>; + st,syscfg-dlyb =3D <&syscfg 0x1000>; + }; + + spi@1 { + compatible =3D "st,stm32mp25-ospi"; + reg =3D <1 0 0x400>; + memory-region =3D <&mm_ospi1>; + interrupts =3D ; + dmas =3D <&hpdma 3 0x62 0x00003121 0x0>, + <&hpdma 3 0x42 0x00003112 0x0>; + dma-names =3D "tx", "rx"; + clocks =3D <&scmi_clk CK_KER_OSPI2>; + resets =3D <&scmi_reset RST_SCMI_OSPI2>, <&scmi_reset RST_SCMI_OSP= I1DLL>; + access-controllers =3D <&rifsc 75>; + power-domains =3D <&CLUSTER_PD>; + #address-cells =3D <1>; + #size-cells =3D <0>; + st,syscfg-dlyb =3D <&syscfg 0x1000>; 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Tue, 22 Apr 2025 10:45:54 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 8897A40049; Tue, 22 Apr 2025 10:44:53 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id CBF2E9D873B; Tue, 22 Apr 2025 10:44:04 +0200 (CEST) Received: from localhost (10.48.87.62) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 22 Apr 2025 10:44:04 +0200 From: Patrice Chotard Date: Tue, 22 Apr 2025 10:44:01 +0200 Subject: [PATCH v10 2/3] memory: Add STM32 Octo Memory Manager driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250422-upstream_ospi_v6-v10-2-6f4942a04e10@foss.st.com> References: <20250422-upstream_ospi_v6-v10-0-6f4942a04e10@foss.st.com> In-Reply-To: <20250422-upstream_ospi_v6-v10-0-6f4942a04e10@foss.st.com> To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Krzysztof Kozlowski , Catalin Marinas , Will Deacon CC: , , , , , Patrice Chotard X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-22_04,2025-04-21_02,2024-11-22_01 Octo Memory Manager driver (OMM) manages: - the muxing between 2 OSPI busses and 2 output ports. There are 4 possible muxing configurations: - direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2 output is on port 2 - OSPI1 and OSPI2 are multiplexed over the same output port 1 - swapped mode (no multiplexing), OSPI1 output is on port 2, OSPI2 output is on port 1 - OSPI1 and OSPI2 are multiplexed over the same output port 2 - the split of the memory area shared between the 2 OSPI instances. - chip select selection override. - the time between 2 transactions in multiplexed mode. - check firewall access. Signed-off-by: Christophe Kerello Signed-off-by: Patrice Chotard --- drivers/memory/Kconfig | 17 ++ drivers/memory/Makefile | 1 + drivers/memory/stm32_omm.c | 471 +++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 489 insertions(+) diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index c82d8d8a16eaf154c247c0dbb9aff428b7c81402..3a0703fbfee7d1a9467cc748216= 04d3861fb1de0 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -225,6 +225,23 @@ config STM32_FMC2_EBI devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on SOCs containing the FMC2 External Bus Interface. =20 +config STM32_OMM + tristate "STM32 Octo Memory Manager" + depends on SPI_STM32_OSPI || COMPILE_TEST + help + This driver manages the muxing between the 2 OSPI busses and + the 2 output ports. There are 4 possible muxing configurations: + - direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2 + output is on port 2 + - OSPI1 and OSPI2 are multiplexed over the same output port 1 + - swapped mode (no multiplexing), OSPI1 output is on port 2, + OSPI2 output is on port 1 + - OSPI1 and OSPI2 are multiplexed over the same output port 2 + It also manages : + - the split of the memory area shared between the 2 OSPI instances. + - chip select selection override. + - the time between 2 transactions in multiplexed mode. + source "drivers/memory/samsung/Kconfig" source "drivers/memory/tegra/Kconfig" =20 diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile index d2e6ca9abbe0231c14284e3818ce734c618f83d0..c1959661bf63775bdded6dcbe87= b732883c26135 100644 --- a/drivers/memory/Makefile +++ b/drivers/memory/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_DA8XX_DDRCTL) +=3D da8xx-ddrctl.o obj-$(CONFIG_PL353_SMC) +=3D pl353-smc.o obj-$(CONFIG_RENESAS_RPCIF) +=3D renesas-rpc-if.o obj-$(CONFIG_STM32_FMC2_EBI) +=3D stm32-fmc2-ebi.o +obj-$(CONFIG_STM32_OMM) +=3D stm32_omm.o =20 obj-$(CONFIG_SAMSUNG_MC) +=3D samsung/ obj-$(CONFIG_TEGRA_MC) +=3D tegra/ diff --git a/drivers/memory/stm32_omm.c b/drivers/memory/stm32_omm.c new file mode 100644 index 0000000000000000000000000000000000000000..76236c23ef7a1ac8cb19e0cbd9c= 929bdbc0186ca --- /dev/null +++ b/drivers/memory/stm32_omm.c @@ -0,0 +1,471 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author(s): Patrice Chotard for STMicroele= ctronics. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define OMM_CR 0 +#define CR_MUXEN BIT(0) +#define CR_MUXENMODE_MASK GENMASK(1, 0) +#define CR_CSSEL_OVR_EN BIT(4) +#define CR_CSSEL_OVR_MASK GENMASK(6, 5) +#define CR_REQ2ACK_MASK GENMASK(23, 16) + +#define OMM_CHILD_NB 2 +#define OMM_CLK_NB 3 + +struct stm32_omm { + struct resource *mm_res; + struct clk_bulk_data clk_bulk[OMM_CLK_NB]; + struct reset_control *child_reset[OMM_CHILD_NB]; + void __iomem *io_base; + u32 cr; + u8 nb_child; + bool restore_omm; +}; + +static int stm32_omm_set_amcr(struct device *dev, bool set) +{ + struct stm32_omm *omm =3D dev_get_drvdata(dev); + resource_size_t mm_ospi2_size =3D 0; + static const char * const mm_name[] =3D { "ospi1", "ospi2" }; + struct regmap *syscfg_regmap; + struct device_node *node; + struct resource res, res1; + u32 amcr_base, amcr_mask; + int ret, idx; + unsigned int i, amcr, read_amcr; + + for (i =3D 0; i < omm->nb_child; i++) { + idx =3D of_property_match_string(dev->of_node, + "memory-region-names", + mm_name[i]); + if (idx < 0) + continue; + + /* res1 only used on second loop iteration */ + res1.start =3D res.start; + res1.end =3D res.end; + + node =3D of_parse_phandle(dev->of_node, "memory-region", idx); + if (!node) + continue; + + ret =3D of_address_to_resource(node, 0, &res); + if (ret) { + of_node_put(node); + dev_err(dev, "unable to resolve memory region\n"); + return ret; + } + + /* check that memory region fits inside OMM memory map area */ + if (!resource_contains(omm->mm_res, &res)) { + dev_err(dev, "%s doesn't fit inside OMM memory map area\n", + mm_name[i]); + dev_err(dev, "%pR doesn't fit inside %pR\n", &res, omm->mm_res); + of_node_put(node); + + return -EFAULT; + } + + if (i =3D=3D 1) { + mm_ospi2_size =3D resource_size(&res); + + /* check that OMM memory region 1 doesn't overlap memory region 2 */ + if (resource_overlaps(&res, &res1)) { + dev_err(dev, "OMM memory-region %s overlaps memory region %s\n", + mm_name[0], mm_name[1]); + dev_err(dev, "%pR overlaps %pR\n", &res1, &res); + of_node_put(node); + + return -EFAULT; + } + } + of_node_put(node); + } + + syscfg_regmap =3D syscon_regmap_lookup_by_phandle(dev->of_node, "st,syscf= g-amcr"); + if (IS_ERR(syscfg_regmap)) + return dev_err_probe(dev, PTR_ERR(syscfg_regmap), + "Failed to get st,syscfg-amcr property\n"); + + ret =3D of_property_read_u32_index(dev->of_node, "st,syscfg-amcr", 1, + &amcr_base); + if (ret) + return ret; + + ret =3D of_property_read_u32_index(dev->of_node, "st,syscfg-amcr", 2, + &amcr_mask); + if (ret) + return ret; + + amcr =3D mm_ospi2_size / SZ_64M; + + if (set) + regmap_update_bits(syscfg_regmap, amcr_base, amcr_mask, amcr); + + /* read AMCR and check coherency with memory-map areas defined in DT */ + regmap_read(syscfg_regmap, amcr_base, &read_amcr); + read_amcr =3D read_amcr >> (ffs(amcr_mask) - 1); + + if (amcr !=3D read_amcr) { + dev_err(dev, "AMCR value not coherent with DT memory-map areas\n"); + ret =3D -EINVAL; + } + + return ret; +} + +static int stm32_omm_toggle_child_clock(struct device *dev, bool enable) +{ + struct stm32_omm *omm =3D dev_get_drvdata(dev); + int i, ret; + + for (i =3D 0; i < omm->nb_child; i++) { + if (enable) { + ret =3D clk_prepare_enable(omm->clk_bulk[i + 1].clk); + if (ret) { + dev_err(dev, "Can not enable clock\n"); + goto clk_error; + } + } else { + clk_disable_unprepare(omm->clk_bulk[i + 1].clk); + } + } + + return 0; + +clk_error: + while (i--) + clk_disable_unprepare(omm->clk_bulk[i + 1].clk); + + return ret; +} + +static int stm32_omm_disable_child(struct device *dev) +{ + struct stm32_omm *omm =3D dev_get_drvdata(dev); + struct reset_control *reset; + int ret; + u8 i; + + ret =3D stm32_omm_toggle_child_clock(dev, true); + if (!ret) + return ret; + + for (i =3D 0; i < omm->nb_child; i++) { + /* reset OSPI to ensure CR_EN bit is set to 0 */ + reset =3D omm->child_reset[i]; + ret =3D reset_control_acquire(reset); + if (ret) { + dev_err(dev, "Can not acquire resset %d\n", ret); + return ret; + } + + reset_control_assert(reset); + udelay(2); + reset_control_deassert(reset); + + reset_control_release(reset); + } + + return stm32_omm_toggle_child_clock(dev, false); +} + +static int stm32_omm_configure(struct device *dev) +{ + static const char * const clocks_name[] =3D {"omm", "ospi1", "ospi2"}; + struct stm32_omm *omm =3D dev_get_drvdata(dev); + unsigned long clk_rate_max =3D 0; + u32 mux =3D 0; + u32 cssel_ovr =3D 0; + u32 req2ack =3D 0; + struct reset_control *rstc; + unsigned long clk_rate; + int ret; + u8 i; + + for (i =3D 0; i < OMM_CLK_NB; i++) + omm->clk_bulk[i].id =3D clocks_name[i]; + + /* retrieve OMM, OSPI1 and OSPI2 clocks */ + ret =3D devm_clk_bulk_get(dev, OMM_CLK_NB, omm->clk_bulk); + if (ret) + return dev_err_probe(dev, ret, "Failed to get OMM/OSPI's clocks\n"); + + /* Ensure both OSPI instance are disabled before configuring OMM */ + ret =3D stm32_omm_disable_child(dev); + if (ret) + return ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) + return ret; + + /* parse children's clock */ + for (i =3D 1; i <=3D omm->nb_child; i++) { + clk_rate =3D clk_get_rate(omm->clk_bulk[i].clk); + if (!clk_rate) { + dev_err(dev, "Invalid clock rate\n"); + goto error; + } + + if (clk_rate > clk_rate_max) + clk_rate_max =3D clk_rate; + } + + rstc =3D devm_reset_control_get_exclusive(dev, "omm"); + if (IS_ERR(rstc)) + return dev_err_probe(dev, PTR_ERR(rstc), "reset get failed\n"); + + reset_control_assert(rstc); + udelay(2); + reset_control_deassert(rstc); + + omm->cr =3D readl_relaxed(omm->io_base + OMM_CR); + /* optional */ + ret =3D of_property_read_u32(dev->of_node, "st,omm-mux", &mux); + if (!ret) { + if (mux & CR_MUXEN) { + ret =3D of_property_read_u32(dev->of_node, "st,omm-req2ack-ns", + &req2ack); + if (!ret && !req2ack) { + req2ack =3D DIV_ROUND_UP(req2ack, NSEC_PER_SEC / clk_rate_max) - 1; + + if (req2ack > 256) + req2ack =3D 256; + } + + req2ack =3D FIELD_PREP(CR_REQ2ACK_MASK, req2ack); + + omm->cr &=3D ~CR_REQ2ACK_MASK; + omm->cr |=3D FIELD_PREP(CR_REQ2ACK_MASK, req2ack); + + /* + * If the mux is enabled, the 2 OSPI clocks have to be + * always enabled + */ + ret =3D stm32_omm_toggle_child_clock(dev, true); + if (ret) + goto error; + } + + omm->cr &=3D ~CR_MUXENMODE_MASK; + omm->cr |=3D FIELD_PREP(CR_MUXENMODE_MASK, mux); + } + + /* optional */ + ret =3D of_property_read_u32(dev->of_node, "st,omm-cssel-ovr", &cssel_ovr= ); + if (!ret) { + omm->cr &=3D ~CR_CSSEL_OVR_MASK; + omm->cr |=3D FIELD_PREP(CR_CSSEL_OVR_MASK, cssel_ovr); + omm->cr |=3D CR_CSSEL_OVR_EN; + } + + omm->restore_omm =3D true; + writel_relaxed(omm->cr, omm->io_base + OMM_CR); + + ret =3D stm32_omm_set_amcr(dev, true); + +error: + pm_runtime_put_sync_suspend(dev); + + return ret; +} + +static int stm32_omm_check_access(struct device_node *np) +{ + struct stm32_firewall firewall; + int ret; + + ret =3D stm32_firewall_get_firewall(np, &firewall, 1); + if (ret) + return ret; + + return stm32_firewall_grant_access(&firewall); +} + +static int stm32_omm_probe(struct platform_device *pdev) +{ + static const char * const resets_name[] =3D {"ospi1", "ospi2"}; + struct device *dev =3D &pdev->dev; + u8 child_access_granted =3D 0; + struct stm32_omm *omm; + int i, ret; + + omm =3D devm_kzalloc(dev, sizeof(*omm), GFP_KERNEL); + if (!omm) + return -ENOMEM; + + omm->io_base =3D devm_platform_ioremap_resource_byname(pdev, "regs"); + if (IS_ERR(omm->io_base)) + return PTR_ERR(omm->io_base); + + omm->mm_res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "memor= y_map"); + if (IS_ERR(omm->mm_res)) + return PTR_ERR(omm->mm_res); + + /* check child's access */ + for_each_child_of_node_scoped(dev->of_node, child) { + if (omm->nb_child >=3D OMM_CHILD_NB) { + dev_err(dev, "Bad DT, found too much children\n"); + return -E2BIG; + } + + ret =3D stm32_omm_check_access(child); + if (ret < 0 && ret !=3D -EACCES) + return ret; + + if (!ret) + child_access_granted++; + + omm->nb_child++; + } + + if (omm->nb_child !=3D OMM_CHILD_NB) + return -EINVAL; + + platform_set_drvdata(pdev, omm); + + devm_pm_runtime_enable(dev); + + /* check if OMM's resource access is granted */ + ret =3D stm32_omm_check_access(dev->of_node); + if (ret < 0 && ret !=3D -EACCES) + return ret; + + for (i =3D 0; i < omm->nb_child; i++) { + omm->child_reset[i] =3D devm_reset_control_get_exclusive_released(dev, + resets_name[i]); + + if (IS_ERR(omm->child_reset[i])) + return dev_err_probe(dev, PTR_ERR(omm->child_reset[i]), + "Can't get %s reset\n", resets_name[i]); + } + + if (!ret && child_access_granted =3D=3D OMM_CHILD_NB) { + ret =3D stm32_omm_configure(dev); + if (ret) + return ret; + } else { + dev_dbg(dev, "Octo Memory Manager resource's access not granted\n"); + /* + * AMCR can't be set, so check if current value is coherent + * with memory-map areas defined in DT + */ + ret =3D stm32_omm_set_amcr(dev, false); + if (ret) + return ret; + } + + ret =3D devm_of_platform_populate(dev); + if (ret) + dev_err(dev, "Failed to create Octo Memory Manager child\n"); + + return ret; +} + +static void stm32_omm_remove(struct platform_device *pdev) +{ + struct stm32_omm *omm =3D platform_get_drvdata(pdev); + + if (omm->cr & CR_MUXEN) + stm32_omm_toggle_child_clock(&pdev->dev, false); +} + +static const struct of_device_id stm32_omm_of_match[] =3D { + { .compatible =3D "st,stm32mp25-omm", }, + {} +}; +MODULE_DEVICE_TABLE(of, stm32_omm_of_match); + +static int __maybe_unused stm32_omm_runtime_suspend(struct device *dev) +{ + struct stm32_omm *omm =3D dev_get_drvdata(dev); + + clk_disable_unprepare(omm->clk_bulk[0].clk); + + return 0; +} + +static int __maybe_unused stm32_omm_runtime_resume(struct device *dev) +{ + struct stm32_omm *omm =3D dev_get_drvdata(dev); + + return clk_prepare_enable(omm->clk_bulk[0].clk); +} + +static int __maybe_unused stm32_omm_suspend(struct device *dev) +{ + struct stm32_omm *omm =3D dev_get_drvdata(dev); + + if (omm->restore_omm && omm->cr & CR_MUXEN) + stm32_omm_toggle_child_clock(dev, false); + + return pinctrl_pm_select_sleep_state(dev); +} + +static int __maybe_unused stm32_omm_resume(struct device *dev) +{ + struct stm32_omm *omm =3D dev_get_drvdata(dev); + int ret; + + pinctrl_pm_select_default_state(dev); + + if (!omm->restore_omm) + return 0; + + /* Ensure both OSPI instance are disabled before configuring OMM */ + ret =3D stm32_omm_disable_child(dev); + if (ret) + return ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) + return ret; + + writel_relaxed(omm->cr, omm->io_base + OMM_CR); + ret =3D stm32_omm_set_amcr(dev, true); + pm_runtime_put_sync_suspend(dev); + if (ret) + return ret; + + if (omm->cr & CR_MUXEN) + ret =3D stm32_omm_toggle_child_clock(dev, true); + + return ret; +} + +static const struct dev_pm_ops stm32_omm_pm_ops =3D { + SET_RUNTIME_PM_OPS(stm32_omm_runtime_suspend, + stm32_omm_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(stm32_omm_suspend, stm32_omm_resume) +}; + +static struct platform_driver stm32_omm_driver =3D { + .probe =3D stm32_omm_probe, + .remove =3D stm32_omm_remove, + .driver =3D { + .name =3D "stm32-omm", + .of_match_table =3D stm32_omm_of_match, + .pm =3D &stm32_omm_pm_ops, + }, +}; +module_platform_driver(stm32_omm_driver); + +MODULE_DESCRIPTION("STMicroelectronics Octo Memory Manager driver"); +MODULE_LICENSE("GPL"); --=20 2.25.1 From nobody Mon Feb 9 21:40:25 2026 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A77725D8F2; Tue, 22 Apr 2025 08:46:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745311570; cv=none; b=Wr0jiaHlqB+WXWyoOV7upnfQA5BjWnxXly1HRxvhT0752AxKyjwfoW/GNQ4UHOEwv64kS8BhC8tdwbH06zt92SXykLlD1E496t1yi9x9vb+5OvIq+WVaNpuQIvq3LSMGydtGtOKCnQWVjqcglKlgfOEZMgZm8UPfF9hl69En+ak= ARC-Message-Signature: i=1; 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Tue, 22 Apr 2025 10:44:54 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 7F7AA9D8CD5; Tue, 22 Apr 2025 10:44:05 +0200 (CEST) Received: from localhost (10.48.87.62) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 22 Apr 2025 10:44:05 +0200 From: Patrice Chotard Date: Tue, 22 Apr 2025 10:44:02 +0200 Subject: [PATCH v10 3/3] MAINTAINERS: add entry for STM32 OCTO MEMORY MANAGER driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250422-upstream_ospi_v6-v10-3-6f4942a04e10@foss.st.com> References: <20250422-upstream_ospi_v6-v10-0-6f4942a04e10@foss.st.com> In-Reply-To: <20250422-upstream_ospi_v6-v10-0-6f4942a04e10@foss.st.com> To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Philipp Zabel , Krzysztof Kozlowski , Catalin Marinas , Will Deacon CC: , , , , , Patrice Chotard X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-22_04,2025-04-21_02,2024-11-22_01 Add myself as STM32 OCTO MEMORY MANAGER maintainer. Signed-off-by: Patrice Chotard --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 96b82704950184bd71623ff41fc4df31e4c7fe87..32abd09c0e4309709998f91882c= 7983d1b53a80c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22881,6 +22881,12 @@ L: linux-i2c@vger.kernel.org S: Maintained F: drivers/i2c/busses/i2c-stm32* =20 +ST STM32 OCTO MEMORY MANAGER +M: Patrice Chotard +S: Maintained +F: Documentation/devicetree/bindings/memory-controllers/st,stm32mp25-omm.y= aml +F: drivers/memory/stm32_omm.c + ST STM32 SPI DRIVER M: Alain Volmat L: linux-spi@vger.kernel.org --=20 2.25.1