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[2a02:3100:a503:5900::e63]) by smtp.googlemail.com with ESMTPSA id 4fb4d7f45d1cf-5f62557a547sm4955447a12.22.2025.04.21.13.13.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Apr 2025 13:13:15 -0700 (PDT) From: Martin Blumenstingl To: dri-devel@lists.freedesktop.org, linux-amlogic@lists.infradead.org Cc: neil.armstrong@linaro.org, christianshewitt@gmail.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Martin Blumenstingl Subject: [PATCH RFC v2 1/2] Revert "drm/meson: vclk: fix calculation of 59.94 fractional rates" Date: Mon, 21 Apr 2025 22:12:59 +0200 Message-ID: <20250421201300.778955-2-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250421201300.778955-1-martin.blumenstingl@googlemail.com> References: <20250421201300.778955-1-martin.blumenstingl@googlemail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Christian Hewitt This reverts commit bfbc68e. The patch does permit the offending YUV420 @ 59.94 phy_freq and vclk_freq mode to match in calculations. It also results in all fractional rates being unavailable for use. This was unintended and requires the patch to be reverted. Fixes: bfbc68e4d869 ("drm/meson: vclk: fix calculation of 59.94 fractional = rates") Cc: Signed-off-by: Christian Hewitt Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong --- drivers/gpu/drm/meson/meson_vclk.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/mes= on_vclk.c index 2a942dc6a6dc..2a82119eb58e 100644 --- a/drivers/gpu/drm/meson/meson_vclk.c +++ b/drivers/gpu/drm/meson/meson_vclk.c @@ -790,13 +790,13 @@ meson_vclk_vic_supported_freq(struct meson_drm *priv,= unsigned int phy_freq, FREQ_1000_1001(params[i].pixel_freq)); DRM_DEBUG_DRIVER("i =3D %d phy_freq =3D %d alt =3D %d\n", i, params[i].phy_freq, - FREQ_1000_1001(params[i].phy_freq/1000)*1000); + FREQ_1000_1001(params[i].phy_freq/10)*10); /* Match strict frequency */ if (phy_freq =3D=3D params[i].phy_freq && vclk_freq =3D=3D params[i].vclk_freq) return MODE_OK; /* Match 1000/1001 variant */ - if (phy_freq =3D=3D (FREQ_1000_1001(params[i].phy_freq/1000)*1000) && + if (phy_freq =3D=3D (FREQ_1000_1001(params[i].phy_freq/10)*10) && vclk_freq =3D=3D FREQ_1000_1001(params[i].vclk_freq)) return MODE_OK; } @@ -1070,7 +1070,7 @@ void meson_vclk_setup(struct meson_drm *priv, unsigne= d int target, =20 for (freq =3D 0 ; params[freq].pixel_freq ; ++freq) { if ((phy_freq =3D=3D params[freq].phy_freq || - phy_freq =3D=3D FREQ_1000_1001(params[freq].phy_freq/1000)*1000) && + phy_freq =3D=3D FREQ_1000_1001(params[freq].phy_freq/10)*10) && (vclk_freq =3D=3D params[freq].vclk_freq || vclk_freq =3D=3D FREQ_1000_1001(params[freq].vclk_freq))) { if (vclk_freq !=3D params[freq].vclk_freq) --=20 2.49.0 From nobody Sun Feb 8 21:11:27 2026 Received: from mail-ed1-f47.google.com (mail-ed1-f47.google.com [209.85.208.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 086C91F09B0 for ; Mon, 21 Apr 2025 20:13:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745266404; cv=none; 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[2a02:3100:a503:5900::e63]) by smtp.googlemail.com with ESMTPSA id 4fb4d7f45d1cf-5f62557a547sm4955447a12.22.2025.04.21.13.13.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Apr 2025 13:13:18 -0700 (PDT) From: Martin Blumenstingl To: dri-devel@lists.freedesktop.org, linux-amlogic@lists.infradead.org Cc: neil.armstrong@linaro.org, christianshewitt@gmail.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Martin Blumenstingl Subject: [PATCH RFC v2 2/2] drm/meson: use unsigned long long / Hz for frequency types Date: Mon, 21 Apr 2025 22:13:00 +0200 Message-ID: <20250421201300.778955-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250421201300.778955-1-martin.blumenstingl@googlemail.com> References: <20250421201300.778955-1-martin.blumenstingl@googlemail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Christian reports that 4K output using YUV420 encoding fails with the following error: Fatal Error, invalid HDMI vclk freq 593406 Modetest shows the following: 3840x2160 59.94 3840 4016 4104 4400 2160 2168 2178 2250 593407 flags: xxx= x, xxxx, drm calculated value -------------------------------------^ This indicates that there's a (1kHz) mismatch between the clock calculated by the drm framework and the meson driver. Relevant function call stack: (drm framework) -> meson_encoder_hdmi_atomic_enable() -> meson_encoder_hdmi_set_vclk() -> meson_vclk_setup() The video clock requested by the drm framework is 593407kHz. This is passed by meson_encoder_hdmi_atomic_enable() to meson_encoder_hdmi_set_vclk() and the following formula is applied: - the frequency is halved (which would be 296703.5kHz) and rounded down to the next full integer, which is 296703kHz - TMDS clock is calculated (296703kHz * 10) - video encoder clock is calculated - this needs to match a table from meson_vclk.c and so it doubles the previously halved value again (resulting in 593406kHz) - meson_vclk_setup() can't find (either directly, or by deriving it from 594000kHz * 1000 / 1001 and rounding to the closest integer value - which is 593407kHz as originally requested by the drm framework) a matching clock in it's internal table and errors out with "invalid HDMI vclk freq" Fix the division precision by switching the whole meson driver to use unsigned long long (64-bit) Hz values for clock frequencies instead of unsigned int (32-bit) kHz to fix the rouding error. Fixes: e5fab2ec9ca4 ("drm/meson: vclk: add support for YUV420 setup") Reported-by: Christian Hewitt Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong --- Changes since v1 from Christian: - fix compilation targeting 32-bit ARM - change all clock frequencies from kHz to Hz (throughout the whole driver) drivers/gpu/drm/meson/meson_drv.c | 2 +- drivers/gpu/drm/meson/meson_drv.h | 2 +- drivers/gpu/drm/meson/meson_encoder_hdmi.c | 29 +-- drivers/gpu/drm/meson/meson_vclk.c | 195 +++++++++++---------- drivers/gpu/drm/meson/meson_vclk.h | 13 +- 5 files changed, 126 insertions(+), 115 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meso= n_drv.c index 81d2ee37e773..49ff9f1f16d3 100644 --- a/drivers/gpu/drm/meson/meson_drv.c +++ b/drivers/gpu/drm/meson/meson_drv.c @@ -169,7 +169,7 @@ static const struct meson_drm_soc_attr meson_drm_soc_at= trs[] =3D { /* S805X/S805Y HDMI PLL won't lock for HDMI PHY freq > 1,65GHz */ { .limits =3D { - .max_hdmi_phy_freq =3D 1650000, + .max_hdmi_phy_freq =3D 1650000000, }, .attrs =3D (const struct soc_device_attribute []) { { .soc_id =3D "GXL (S805*)", }, diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meso= n_drv.h index 3f9345c14f31..be4b0e4df6e1 100644 --- a/drivers/gpu/drm/meson/meson_drv.h +++ b/drivers/gpu/drm/meson/meson_drv.h @@ -37,7 +37,7 @@ struct meson_drm_match_data { }; =20 struct meson_drm_soc_limits { - unsigned int max_hdmi_phy_freq; + unsigned long long max_hdmi_phy_freq; }; =20 struct meson_drm { diff --git a/drivers/gpu/drm/meson/meson_encoder_hdmi.c b/drivers/gpu/drm/m= eson/meson_encoder_hdmi.c index 6d1c9262a2cf..7752d8ac85f0 100644 --- a/drivers/gpu/drm/meson/meson_encoder_hdmi.c +++ b/drivers/gpu/drm/meson/meson_encoder_hdmi.c @@ -70,12 +70,12 @@ static void meson_encoder_hdmi_set_vclk(struct meson_en= coder_hdmi *encoder_hdmi, { struct meson_drm *priv =3D encoder_hdmi->priv; int vic =3D drm_match_cea_mode(mode); - unsigned int phy_freq; - unsigned int vclk_freq; - unsigned int venc_freq; - unsigned int hdmi_freq; + unsigned long long phy_freq; + unsigned long long vclk_freq; + unsigned long long venc_freq; + unsigned long long hdmi_freq; =20 - vclk_freq =3D mode->clock; + vclk_freq =3D mode->clock * 1000; =20 /* For 420, pixel clock is half unlike venc clock */ if (encoder_hdmi->output_bus_fmt =3D=3D MEDIA_BUS_FMT_UYYVYY8_0_5X24) @@ -107,7 +107,8 @@ static void meson_encoder_hdmi_set_vclk(struct meson_en= coder_hdmi *encoder_hdmi, if (mode->flags & DRM_MODE_FLAG_DBLCLK) venc_freq /=3D 2; =20 - dev_dbg(priv->dev, "vclk:%d phy=3D%d venc=3D%d hdmi=3D%d enci=3D%d\n", + dev_dbg(priv->dev, + "vclk:%lluHz phy=3D%lluHz venc=3D%lluHz hdmi=3D%lluHz enci=3D%d\n", phy_freq, vclk_freq, venc_freq, hdmi_freq, priv->venc.hdmi_use_enci); =20 @@ -122,10 +123,11 @@ static enum drm_mode_status meson_encoder_hdmi_mode_v= alid(struct drm_bridge *bri struct meson_encoder_hdmi *encoder_hdmi =3D bridge_to_meson_encoder_hdmi(= bridge); struct meson_drm *priv =3D encoder_hdmi->priv; bool is_hdmi2_sink =3D display_info->hdmi.scdc.supported; - unsigned int phy_freq; - unsigned int vclk_freq; - unsigned int venc_freq; - unsigned int hdmi_freq; + unsigned long long clock =3D mode->clock * 1000; + unsigned long long phy_freq; + unsigned long long vclk_freq; + unsigned long long venc_freq; + unsigned long long hdmi_freq; int vic =3D drm_match_cea_mode(mode); enum drm_mode_status status; =20 @@ -144,12 +146,12 @@ static enum drm_mode_status meson_encoder_hdmi_mode_v= alid(struct drm_bridge *bri if (status !=3D MODE_OK) return status; =20 - return meson_vclk_dmt_supported_freq(priv, mode->clock); + return meson_vclk_dmt_supported_freq(priv, clock); /* Check against supported VIC modes */ } else if (!meson_venc_hdmi_supported_vic(vic)) return MODE_BAD; =20 - vclk_freq =3D mode->clock; + vclk_freq =3D clock; =20 /* For 420, pixel clock is half unlike venc clock */ if (drm_mode_is_420_only(display_info, mode) || @@ -179,7 +181,8 @@ static enum drm_mode_status meson_encoder_hdmi_mode_val= id(struct drm_bridge *bri if (mode->flags & DRM_MODE_FLAG_DBLCLK) venc_freq /=3D 2; =20 - dev_dbg(priv->dev, "%s: vclk:%d phy=3D%d venc=3D%d hdmi=3D%d\n", + dev_dbg(priv->dev, + "%s: vclk:%lluHz phy=3D%lluHz venc=3D%lluHz hdmi=3D%lluHz\n", __func__, phy_freq, vclk_freq, venc_freq, hdmi_freq); =20 return meson_vclk_vic_supported_freq(priv, phy_freq, vclk_freq); diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/mes= on_vclk.c index 2a82119eb58e..3325580d885d 100644 --- a/drivers/gpu/drm/meson/meson_vclk.c +++ b/drivers/gpu/drm/meson/meson_vclk.c @@ -110,7 +110,10 @@ #define HDMI_PLL_LOCK BIT(31) #define HDMI_PLL_LOCK_G12A (3 << 30) =20 -#define FREQ_1000_1001(_freq) DIV_ROUND_CLOSEST(_freq * 1000, 1001) +#define PIXEL_FREQ_1000_1001(_freq) \ + DIV_ROUND_CLOSEST_ULL((_freq) * 1000ULL, 1001ULL) +#define PHY_FREQ_1000_1001(_freq) \ + (PIXEL_FREQ_1000_1001(DIV_ROUND_DOWN_ULL(_freq, 10ULL)) * 10) =20 /* VID PLL Dividers */ enum { @@ -360,11 +363,11 @@ enum { }; =20 struct meson_vclk_params { - unsigned int pll_freq; - unsigned int phy_freq; - unsigned int vclk_freq; - unsigned int venc_freq; - unsigned int pixel_freq; + unsigned long long pll_freq; + unsigned long long phy_freq; + unsigned long long vclk_freq; + unsigned long long venc_freq; + unsigned long long pixel_freq; unsigned int pll_od1; unsigned int pll_od2; unsigned int pll_od3; @@ -372,11 +375,11 @@ struct meson_vclk_params { unsigned int vclk_div; } params[] =3D { [MESON_VCLK_HDMI_ENCI_54000] =3D { - .pll_freq =3D 4320000, - .phy_freq =3D 270000, - .vclk_freq =3D 54000, - .venc_freq =3D 54000, - .pixel_freq =3D 54000, + .pll_freq =3D 4320000000, + .phy_freq =3D 270000000, + .vclk_freq =3D 54000000, + .venc_freq =3D 54000000, + .pixel_freq =3D 54000000, .pll_od1 =3D 4, .pll_od2 =3D 4, .pll_od3 =3D 1, @@ -384,11 +387,11 @@ struct meson_vclk_params { .vclk_div =3D 1, }, [MESON_VCLK_HDMI_DDR_54000] =3D { - .pll_freq =3D 4320000, - .phy_freq =3D 270000, - .vclk_freq =3D 54000, - .venc_freq =3D 54000, - .pixel_freq =3D 27000, + .pll_freq =3D 4320000000, + .phy_freq =3D 270000000, + .vclk_freq =3D 54000000, + .venc_freq =3D 54000000, + .pixel_freq =3D 27000000, .pll_od1 =3D 4, .pll_od2 =3D 4, .pll_od3 =3D 1, @@ -396,11 +399,11 @@ struct meson_vclk_params { .vclk_div =3D 1, }, [MESON_VCLK_HDMI_DDR_148500] =3D { - .pll_freq =3D 2970000, - .phy_freq =3D 742500, - .vclk_freq =3D 148500, - .venc_freq =3D 148500, - .pixel_freq =3D 74250, + .pll_freq =3D 2970000000, + .phy_freq =3D 742500000, + .vclk_freq =3D 148500000, + .venc_freq =3D 148500000, + .pixel_freq =3D 74250000, .pll_od1 =3D 4, .pll_od2 =3D 1, .pll_od3 =3D 1, @@ -408,11 +411,11 @@ struct meson_vclk_params { .vclk_div =3D 1, }, [MESON_VCLK_HDMI_74250] =3D { - .pll_freq =3D 2970000, - .phy_freq =3D 742500, - .vclk_freq =3D 74250, - .venc_freq =3D 74250, - .pixel_freq =3D 74250, + .pll_freq =3D 2970000000, + .phy_freq =3D 742500000, + .vclk_freq =3D 74250000, + .venc_freq =3D 74250000, + .pixel_freq =3D 74250000, .pll_od1 =3D 2, .pll_od2 =3D 2, .pll_od3 =3D 2, @@ -420,11 +423,11 @@ struct meson_vclk_params { .vclk_div =3D 1, }, [MESON_VCLK_HDMI_148500] =3D { - .pll_freq =3D 2970000, - .phy_freq =3D 1485000, - .vclk_freq =3D 148500, - .venc_freq =3D 148500, - .pixel_freq =3D 148500, + .pll_freq =3D 2970000000, + .phy_freq =3D 1485000000, + .vclk_freq =3D 148500000, + .venc_freq =3D 148500000, + .pixel_freq =3D 148500000, .pll_od1 =3D 1, .pll_od2 =3D 2, .pll_od3 =3D 2, @@ -432,11 +435,11 @@ struct meson_vclk_params { .vclk_div =3D 1, }, [MESON_VCLK_HDMI_297000] =3D { - .pll_freq =3D 5940000, - .phy_freq =3D 2970000, - .venc_freq =3D 297000, - .vclk_freq =3D 297000, - .pixel_freq =3D 297000, + .pll_freq =3D 5940000000, + .phy_freq =3D 2970000000, + .venc_freq =3D 297000000, + .vclk_freq =3D 297000000, + .pixel_freq =3D 297000000, .pll_od1 =3D 2, .pll_od2 =3D 1, .pll_od3 =3D 1, @@ -444,11 +447,11 @@ struct meson_vclk_params { .vclk_div =3D 2, }, [MESON_VCLK_HDMI_594000] =3D { - .pll_freq =3D 5940000, - .phy_freq =3D 5940000, - .venc_freq =3D 594000, - .vclk_freq =3D 594000, - .pixel_freq =3D 594000, + .pll_freq =3D 5940000000, + .phy_freq =3D 5940000000, + .venc_freq =3D 594000000, + .vclk_freq =3D 594000000, + .pixel_freq =3D 594000000, .pll_od1 =3D 1, .pll_od2 =3D 1, .pll_od3 =3D 2, @@ -456,11 +459,11 @@ struct meson_vclk_params { .vclk_div =3D 1, }, [MESON_VCLK_HDMI_594000_YUV420] =3D { - .pll_freq =3D 5940000, - .phy_freq =3D 2970000, - .venc_freq =3D 594000, - .vclk_freq =3D 594000, - .pixel_freq =3D 297000, + .pll_freq =3D 5940000000, + .phy_freq =3D 2970000000, + .venc_freq =3D 594000000, + .vclk_freq =3D 594000000, + .pixel_freq =3D 297000000, .pll_od1 =3D 2, .pll_od2 =3D 1, .pll_od3 =3D 1, @@ -617,16 +620,16 @@ static void meson_hdmi_pll_set_params(struct meson_dr= m *priv, unsigned int m, 3 << 20, pll_od_to_reg(od3) << 20); } =20 -#define XTAL_FREQ 24000 +#define XTAL_FREQ (24 * 1000 * 1000) =20 static unsigned int meson_hdmi_pll_get_m(struct meson_drm *priv, - unsigned int pll_freq) + unsigned long long pll_freq) { /* The GXBB PLL has a /2 pre-multiplier */ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) - pll_freq /=3D 2; + pll_freq =3D DIV_ROUND_DOWN_ULL(pll_freq, 2); =20 - return pll_freq / XTAL_FREQ; + return DIV_ROUND_DOWN_ULL(pll_freq, XTAL_FREQ); } =20 #define HDMI_FRAC_MAX_GXBB 4096 @@ -635,12 +638,13 @@ static unsigned int meson_hdmi_pll_get_m(struct meson= _drm *priv, =20 static unsigned int meson_hdmi_pll_get_frac(struct meson_drm *priv, unsigned int m, - unsigned int pll_freq) + unsigned long long pll_freq) { - unsigned int parent_freq =3D XTAL_FREQ; + unsigned long long parent_freq =3D XTAL_FREQ; unsigned int frac_max =3D HDMI_FRAC_MAX_GXL; unsigned int frac_m; unsigned int frac; + u32 remainder; =20 /* The GXBB PLL has a /2 pre-multiplier and a larger FRAC width */ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) { @@ -652,11 +656,11 @@ static unsigned int meson_hdmi_pll_get_frac(struct me= son_drm *priv, frac_max =3D HDMI_FRAC_MAX_G12A; =20 /* We can have a perfect match !*/ - if (pll_freq / m =3D=3D parent_freq && - pll_freq % m =3D=3D 0) + if (div_u64_rem(pll_freq, m, &remainder) =3D=3D parent_freq && + remainder =3D=3D 0) return 0; =20 - frac =3D div_u64((u64)pll_freq * (u64)frac_max, parent_freq); + frac =3D mul_u64_u64_div_u64(pll_freq, frac_max, parent_freq); frac_m =3D m * frac_max; if (frac_m > frac) return frac_max; @@ -666,7 +670,7 @@ static unsigned int meson_hdmi_pll_get_frac(struct meso= n_drm *priv, } =20 static bool meson_hdmi_pll_validate_params(struct meson_drm *priv, - unsigned int m, + unsigned long long m, unsigned int frac) { if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) { @@ -694,7 +698,7 @@ static bool meson_hdmi_pll_validate_params(struct meson= _drm *priv, } =20 static bool meson_hdmi_pll_find_params(struct meson_drm *priv, - unsigned int freq, + unsigned long long freq, unsigned int *m, unsigned int *frac, unsigned int *od) @@ -706,7 +710,7 @@ static bool meson_hdmi_pll_find_params(struct meson_drm= *priv, continue; *frac =3D meson_hdmi_pll_get_frac(priv, *m, freq * *od); =20 - DRM_DEBUG_DRIVER("PLL params for %dkHz: m=3D%x frac=3D%x od=3D%d\n", + DRM_DEBUG_DRIVER("PLL params for %lluHz: m=3D%x frac=3D%x od=3D%d\n", freq, *m, *frac, *od); =20 if (meson_hdmi_pll_validate_params(priv, *m, *frac)) @@ -718,7 +722,7 @@ static bool meson_hdmi_pll_find_params(struct meson_drm= *priv, =20 /* pll_freq is the frequency after the OD dividers */ enum drm_mode_status -meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned int freq) +meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned long long f= req) { unsigned int od, m, frac; =20 @@ -741,7 +745,7 @@ EXPORT_SYMBOL_GPL(meson_vclk_dmt_supported_freq); =20 /* pll_freq is the frequency after the OD dividers */ static void meson_hdmi_pll_generic_set(struct meson_drm *priv, - unsigned int pll_freq) + unsigned long long pll_freq) { unsigned int od, m, frac, od1, od2, od3; =20 @@ -756,7 +760,7 @@ static void meson_hdmi_pll_generic_set(struct meson_drm= *priv, od1 =3D od / od2; } =20 - DRM_DEBUG_DRIVER("PLL params for %dkHz: m=3D%x frac=3D%x od=3D%d/%d/%d\n= ", + DRM_DEBUG_DRIVER("PLL params for %lluHz: m=3D%x frac=3D%x od=3D%d/%d/%d\= n", pll_freq, m, frac, od1, od2, od3); =20 meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3); @@ -764,17 +768,18 @@ static void meson_hdmi_pll_generic_set(struct meson_d= rm *priv, return; } =20 - DRM_ERROR("Fatal, unable to find parameters for PLL freq %d\n", + DRM_ERROR("Fatal, unable to find parameters for PLL freq %lluHz\n", pll_freq); } =20 enum drm_mode_status -meson_vclk_vic_supported_freq(struct meson_drm *priv, unsigned int phy_fre= q, - unsigned int vclk_freq) +meson_vclk_vic_supported_freq(struct meson_drm *priv, + unsigned long long phy_freq, + unsigned long long vclk_freq) { int i; =20 - DRM_DEBUG_DRIVER("phy_freq =3D %d vclk_freq =3D %d\n", + DRM_DEBUG_DRIVER("phy_freq =3D %lluHz vclk_freq =3D %lluHz\n", phy_freq, vclk_freq); =20 /* Check against soc revision/package limits */ @@ -785,19 +790,19 @@ meson_vclk_vic_supported_freq(struct meson_drm *priv,= unsigned int phy_freq, } =20 for (i =3D 0 ; params[i].pixel_freq ; ++i) { - DRM_DEBUG_DRIVER("i =3D %d pixel_freq =3D %d alt =3D %d\n", + DRM_DEBUG_DRIVER("i =3D %d pixel_freq =3D %lluHz alt =3D %lluHz\n", i, params[i].pixel_freq, - FREQ_1000_1001(params[i].pixel_freq)); - DRM_DEBUG_DRIVER("i =3D %d phy_freq =3D %d alt =3D %d\n", + PIXEL_FREQ_1000_1001(params[i].pixel_freq)); + DRM_DEBUG_DRIVER("i =3D %d phy_freq =3D %lluHz alt =3D %lluHz\n", i, params[i].phy_freq, - FREQ_1000_1001(params[i].phy_freq/10)*10); + PHY_FREQ_1000_1001(params[i].phy_freq)); /* Match strict frequency */ if (phy_freq =3D=3D params[i].phy_freq && vclk_freq =3D=3D params[i].vclk_freq) return MODE_OK; /* Match 1000/1001 variant */ - if (phy_freq =3D=3D (FREQ_1000_1001(params[i].phy_freq/10)*10) && - vclk_freq =3D=3D FREQ_1000_1001(params[i].vclk_freq)) + if (phy_freq =3D=3D PHY_FREQ_1000_1001(params[i].phy_freq) && + vclk_freq =3D=3D PIXEL_FREQ_1000_1001(params[i].vclk_freq)) return MODE_OK; } =20 @@ -805,8 +810,9 @@ meson_vclk_vic_supported_freq(struct meson_drm *priv, u= nsigned int phy_freq, } EXPORT_SYMBOL_GPL(meson_vclk_vic_supported_freq); =20 -static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_f= req, - unsigned int od1, unsigned int od2, unsigned int od3, +static void meson_vclk_set(struct meson_drm *priv, + unsigned long long pll_base_freq, unsigned int od1, + unsigned int od2, unsigned int od3, unsigned int vid_pll_div, unsigned int vclk_div, unsigned int hdmi_tx_div, unsigned int venc_div, bool hdmi_use_enci, bool vic_alternate_clock) @@ -826,15 +832,15 @@ static void meson_vclk_set(struct meson_drm *priv, un= signed int pll_base_freq, meson_hdmi_pll_generic_set(priv, pll_base_freq); } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) { switch (pll_base_freq) { - case 2970000: + case 2970000000: m =3D 0x3d; frac =3D vic_alternate_clock ? 0xd02 : 0xe00; break; - case 4320000: + case 4320000000: m =3D vic_alternate_clock ? 0x59 : 0x5a; frac =3D vic_alternate_clock ? 0xe8f : 0; break; - case 5940000: + case 5940000000: m =3D 0x7b; frac =3D vic_alternate_clock ? 0xa05 : 0xc00; break; @@ -844,15 +850,15 @@ static void meson_vclk_set(struct meson_drm *priv, un= signed int pll_base_freq, } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) { switch (pll_base_freq) { - case 2970000: + case 2970000000: m =3D 0x7b; frac =3D vic_alternate_clock ? 0x281 : 0x300; break; - case 4320000: + case 4320000000: m =3D vic_alternate_clock ? 0xb3 : 0xb4; frac =3D vic_alternate_clock ? 0x347 : 0; break; - case 5940000: + case 5940000000: m =3D 0xf7; frac =3D vic_alternate_clock ? 0x102 : 0x200; break; @@ -861,15 +867,15 @@ static void meson_vclk_set(struct meson_drm *priv, un= signed int pll_base_freq, meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3); } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { switch (pll_base_freq) { - case 2970000: + case 2970000000: m =3D 0x7b; frac =3D vic_alternate_clock ? 0x140b4 : 0x18000; break; - case 4320000: + case 4320000000: m =3D vic_alternate_clock ? 0xb3 : 0xb4; frac =3D vic_alternate_clock ? 0x1a3ee : 0; break; - case 5940000: + case 5940000000: m =3D 0xf7; frac =3D vic_alternate_clock ? 0x8148 : 0x10000; break; @@ -1025,14 +1031,14 @@ static void meson_vclk_set(struct meson_drm *priv, = unsigned int pll_base_freq, } =20 void meson_vclk_setup(struct meson_drm *priv, unsigned int target, - unsigned int phy_freq, unsigned int vclk_freq, - unsigned int venc_freq, unsigned int dac_freq, + unsigned long long phy_freq, unsigned long long vclk_freq, + unsigned long long venc_freq, unsigned long long dac_freq, bool hdmi_use_enci) { bool vic_alternate_clock =3D false; - unsigned int freq; - unsigned int hdmi_tx_div; - unsigned int venc_div; + unsigned long long freq; + unsigned long long hdmi_tx_div; + unsigned long long venc_div; =20 if (target =3D=3D MESON_VCLK_TARGET_CVBS) { meson_venci_cvbs_clock_config(priv); @@ -1052,27 +1058,27 @@ void meson_vclk_setup(struct meson_drm *priv, unsig= ned int target, return; } =20 - hdmi_tx_div =3D vclk_freq / dac_freq; + hdmi_tx_div =3D DIV_ROUND_DOWN_ULL(vclk_freq, dac_freq); =20 if (hdmi_tx_div =3D=3D 0) { - pr_err("Fatal Error, invalid HDMI-TX freq %d\n", + pr_err("Fatal Error, invalid HDMI-TX freq %lluHz\n", dac_freq); return; } =20 - venc_div =3D vclk_freq / venc_freq; + venc_div =3D DIV_ROUND_DOWN_ULL(vclk_freq, venc_freq); =20 if (venc_div =3D=3D 0) { - pr_err("Fatal Error, invalid HDMI venc freq %d\n", + pr_err("Fatal Error, invalid HDMI venc freq %lluHz\n", venc_freq); return; } =20 for (freq =3D 0 ; params[freq].pixel_freq ; ++freq) { if ((phy_freq =3D=3D params[freq].phy_freq || - phy_freq =3D=3D FREQ_1000_1001(params[freq].phy_freq/10)*10) && + phy_freq =3D=3D PHY_FREQ_1000_1001(params[freq].phy_freq)) && (vclk_freq =3D=3D params[freq].vclk_freq || - vclk_freq =3D=3D FREQ_1000_1001(params[freq].vclk_freq))) { + vclk_freq =3D=3D PIXEL_FREQ_1000_1001(params[freq].vclk_freq))) { if (vclk_freq !=3D params[freq].vclk_freq) vic_alternate_clock =3D true; else @@ -1098,7 +1104,8 @@ void meson_vclk_setup(struct meson_drm *priv, unsigne= d int target, } =20 if (!params[freq].pixel_freq) { - pr_err("Fatal Error, invalid HDMI vclk freq %d\n", vclk_freq); + pr_err("Fatal Error, invalid HDMI vclk freq %lluHz\n", + vclk_freq); return; } =20 diff --git a/drivers/gpu/drm/meson/meson_vclk.h b/drivers/gpu/drm/meson/mes= on_vclk.h index 60617aaf18dd..7ac55744e574 100644 --- a/drivers/gpu/drm/meson/meson_vclk.h +++ b/drivers/gpu/drm/meson/meson_vclk.h @@ -20,17 +20,18 @@ enum { }; =20 /* 27MHz is the CVBS Pixel Clock */ -#define MESON_VCLK_CVBS 27000 +#define MESON_VCLK_CVBS (27 * 1000 * 1000) =20 enum drm_mode_status -meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned int freq); +meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned long long f= req); enum drm_mode_status -meson_vclk_vic_supported_freq(struct meson_drm *priv, unsigned int phy_fre= q, - unsigned int vclk_freq); +meson_vclk_vic_supported_freq(struct meson_drm *priv, + unsigned long long phy_freq, + unsigned long long vclk_freq); =20 void meson_vclk_setup(struct meson_drm *priv, unsigned int target, - unsigned int phy_freq, unsigned int vclk_freq, - unsigned int venc_freq, unsigned int dac_freq, + unsigned long long phy_freq, unsigned long long vclk_freq, + unsigned long long venc_freq, unsigned long long dac_freq, bool hdmi_use_enci); =20 #endif /* __MESON_VCLK_H */ --=20 2.49.0