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Lin" , Nancy Lin , Singo Chang , "Paul Chen --cc=devicetree @ vger . kernel . org" , , , , , , Sunny Shen Subject: [PATCH v2 4/5] drm/mediatek: Add MDP-RSZ component support for MT8196 Date: Mon, 21 Apr 2025 21:38:31 +0800 Message-ID: <20250421133835.508863-5-sunny.shen@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250421133835.508863-1-sunny.shen@mediatek.com> References: <20250421133835.508863-1-sunny.shen@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add MDP-RSZ component support for MT8196. Signed-off-by: Sunny Shen Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 24 ++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++ 3 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.c index 6628f5cd732a..04f13ca3601b 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -46,6 +46,9 @@ #define DSC_BYPASS BIT(4) #define DSC_UFOE_SEL BIT(16) =20 +#define DISP_REG_MDP_RSZ_INPUT_SIZE 0x0010 +#define DISP_REG_MDP_RSZ_OUTPUT_SIZE 0x0014 + #define DISP_REG_OD_EN 0x0000 #define DISP_REG_OD_CFG 0x0020 #define OD_RELAYMODE BIT(0) @@ -235,6 +238,19 @@ static void mtk_od_start(struct device *dev) writel(1, priv->regs + DISP_REG_OD_EN); } =20 +static void mtk_mdp_rsz_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_ddp_comp_dev *priv =3D dev_get_drvdata(dev); + + /* Set size =3D 0 for bypass mode */ + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, + DISP_REG_MDP_RSZ_INPUT_SIZE); + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, + DISP_REG_MDP_RSZ_OUTPUT_SIZE); +} + static void mtk_postmask_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -393,6 +409,12 @@ static const struct mtk_ddp_comp_funcs ddp_ovlsys_adap= tor =3D { .get_num_formats =3D mtk_ovlsys_adaptor_get_num_formats, }; =20 +static const struct mtk_ddp_comp_funcs ddp_mdp_rsz =3D { + .clk_enable =3D mtk_ddp_clk_enable, + .clk_disable =3D mtk_ddp_clk_disable, + .config =3D mtk_mdp_rsz_config, +}; + static const struct mtk_ddp_comp_funcs ddp_postmask =3D { .clk_enable =3D mtk_ddp_clk_enable, .clk_disable =3D mtk_ddp_clk_disable, @@ -456,6 +478,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COM= P_TYPE_MAX] =3D { [MTK_DISP_DITHER] =3D "dither", [MTK_DISP_DSC] =3D "dsc", [MTK_DISP_GAMMA] =3D "gamma", + [MTK_DISP_MDP_RSZ] =3D "mdp-rsz", [MTK_DISP_MERGE] =3D "merge", [MTK_DISP_MUTEX] =3D "mutex", [MTK_DISP_OD] =3D "od", @@ -515,6 +538,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[= DDP_COMPONENT_DRM_ID_MAX] [DDP_COMPONENT_DSI2] =3D { MTK_DSI, 2, &ddp_dsi }, [DDP_COMPONENT_DSI3] =3D { MTK_DSI, 3, &ddp_dsi }, [DDP_COMPONENT_GAMMA] =3D { MTK_DISP_GAMMA, 0, &ddp_gamma }, + [DDP_COMPONENT_MDP_RSZ0] =3D { MTK_DISP_MDP_RSZ, 0, &ddp_mdp_rsz}, [DDP_COMPONENT_MERGE0] =3D { MTK_DISP_MERGE, 0, &ddp_merge }, [DDP_COMPONENT_MERGE1] =3D { MTK_DISP_MERGE, 1, &ddp_merge }, [DDP_COMPONENT_MERGE2] =3D { MTK_DISP_MERGE, 2, &ddp_merge }, diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.h index badb42bd4f7c..87f573fcc903 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h @@ -36,6 +36,7 @@ enum mtk_ddp_comp_type { MTK_DISP_OVLSYS_ADAPTOR, MTK_DISP_OVL_2L, MTK_DISP_OVL_ADAPTOR, + MTK_DISP_MDP_RSZ, MTK_DISP_POSTMASK, MTK_DISP_PWM, MTK_DISP_RDMA, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index 70a7e6d06d4f..aa7eec1fc7e6 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -975,6 +975,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = =3D { .data =3D (void *)MTK_DSI }, { .compatible =3D "mediatek,mt8188-dsi", .data =3D (void *)MTK_DSI }, + { .compatible =3D "mediatek,mt8196-mdp-rsz", + .data =3D (void *)MTK_DISP_MDP_RSZ }, { } }; =20 --=20 2.45.2