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Lin" , Nancy Lin , Singo Chang , "Paul Chen --cc=devicetree @ vger . kernel . org" , , , , , , Sunny Shen Subject: [PATCH v2 1/5] dt-bindings: display: mediatek: mdp-rsz: Add rules for MT8196 Date: Mon, 21 Apr 2025 21:38:28 +0800 Message-ID: <20250421133835.508863-2-sunny.shen@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250421133835.508863-1-sunny.shen@mediatek.com> References: <20250421133835.508863-1-sunny.shen@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add MDP-RSZ hardware description for MediaTek MT8196 SoC Signed-off-by: Sunny Shen --- .../display/mediatek/mediatek,mdp-rsz.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/medi= atek,mdp-rsz.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,md= p-rsz.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,md= p-rsz.yaml new file mode 100644 index 000000000000..fb7be0d1df6f --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rsz.y= aml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rsz.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek display multimedia data path resizer + +maintainers: + - Chun-Kuang Hu + - Philipp Zabel + +description: | + MediaTek display multimedia data path resizer, namely MDP-RSZ, + can do scaling up/down to the picture. + +properties: + compatible: + const: mediatek,mt8196-mdp-rsz + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + soc { + #address-cells =3D <2>; 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Lin" , "Nancy Lin" , Singo Chang , "Paul Chen --cc=devicetree @ vger . kernel . org" , , , , , , Sunny Shen Subject: [PATCH v2 2/5] dt-bindings: display: mediatek: postmask: Add compatible string for MT8196 Date: Mon, 21 Apr 2025 21:38:29 +0800 Message-ID: <20250421133835.508863-3-sunny.shen@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250421133835.508863-1-sunny.shen@mediatek.com> References: <20250421133835.508863-1-sunny.shen@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a compatible string for MediaTek MT8196 SoC Signed-off-by: Sunny Shen --- .../devicetree/bindings/display/mediatek/mediatek,postmask.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,po= stmask.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,p= ostmask.yaml index fb6fe4742624..29624ac191e1 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.= yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.= yaml @@ -27,6 +27,7 @@ properties: - enum: - mediatek,mt8186-disp-postmask - mediatek,mt8188-disp-postmask + - mediatek,mt8196-disp-postmask - const: mediatek,mt8192-disp-postmask =20 reg: --=20 2.45.2 From nobody Thu Dec 18 01:54:39 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08BA226659B for ; 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Lin" , Nancy Lin , Singo Chang , "Paul Chen --cc=devicetree @ vger . kernel . org" , , , , , , Sunny Shen Subject: [PATCH v2 3/5] soc: mediatek: Add components to support PQ in display path for MT8196 Date: Mon, 21 Apr 2025 21:38:30 +0800 Message-ID: <20250421133835.508863-4-sunny.shen@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250421133835.508863-1-sunny.shen@mediatek.com> References: <20250421133835.508863-1-sunny.shen@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Due to the path mux design of the MT8196, the following components need to be configured into mutex and mmsys to support Picture Quality (PQ) in the display path:CCORR0, CCORR1, DITHER0, GAMMA0, MDP_RSZ0, POSTMASK0, TDSHP0. Signed-off-by: Sunny Shen --- drivers/soc/mediatek/mt8196-mmsys.h | 70 +++++++++++++++++++++++++- drivers/soc/mediatek/mtk-mutex.c | 17 +++++++ include/linux/soc/mediatek/mtk-mmsys.h | 5 ++ 3 files changed, 90 insertions(+), 2 deletions(-) diff --git a/drivers/soc/mediatek/mt8196-mmsys.h b/drivers/soc/mediatek/mt8= 196-mmsys.h index ff841ae9939a..bc2dbdf18d24 100644 --- a/drivers/soc/mediatek/mt8196-mmsys.h +++ b/drivers/soc/mediatek/mt8196-mmsys.h @@ -68,6 +68,22 @@ #define MT8196_DISP_OVL_OUT_PROC_CB_TO_OVL_DLO_RELAY7 BIT(2) =20 /* DISPSYS0 */ +#define MT8196_DISP_CCORR0_SEL 0xd28 +#define MT8196_DISP_CCORR0_FROM_TDSHP0 BIT(1) +#define MT8196_DISP_CCORR0_SOUT 0xd2c +#define MT8196_DISP_CCORR0_TO_CCORR1 BIT(0) +#define MT8196_DISP_CCORR1_SEL 0xd30 +#define MT8196_DISP_CCORR1_FROM_CCORR0 BIT(0) +#define MT8196_DISP_CCORR1_SOUT 0xd34 +#define MT8196_DISP_CCORR1_TO_GAMMA0 BIT(0) +#define MT8196_DISP_GAMMA0_SEL 0xd58 +#define MT8196_DISP_GAMMA0_FROM_CCORR1 BIT(0) +#define MT8196_DISP_POSTMASK0_SOUT 0xd68 +#define MT8196_DISP_POSTMASK0_TO_DITHER0 0x0 +#define MT8196_DISP_TDSHP0_SOUT 0xd70 +#define MT8196_DISP_TDSHP0_TO_CCORR0 BIT(1) +#define MT8196_MDP_RSZ0_MOUT_EN 0xd78 +#define MT8196_MDP_RSZ0_TO_TDSHP0 BIT(0) #define MT8196_PANEL_COMP_OUT_CB1_MOUT_EN 0xd84 #define MT8196_DISP_TO_DLO_RELAY1 BIT(1) #define MT8196_PANEL_COMP_OUT_CB2_MOUT_EN 0xd88 @@ -75,12 +91,14 @@ #define MT8196_PANEL_COMP_OUT_CB3_MOUT_EN 0xd8c #define MT8196_DISP_TO_DLO_RELAY3 BIT(3) #define MT8196_PQ_IN_CB0_MOUT_EN 0xdd0 +#define MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_0 BIT(0) #define MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_6 BIT(2) - #define MT8196_PQ_IN_CB1_MOUT_EN 0xdd4 #define MT8196_PQ_IN_CB1_TO_PQ_OUT_CB_7 BIT(3) #define MT8196_PQ_IN_CB8_MOUT_EN 0xdf0 #define MT8196_PQ_IN_CB8_TO_PQ_OUT_CB_8 BIT(4) +#define MT8196_PQ_OUT_CB0_MOUT_EN 0xe3c +#define MT8196_PQ_OUT_CB0_TO_PANEL0_COMP_OUT_CB1 BIT(1) #define MT8196_PQ_OUT_CB6_MOUT_EN 0xe54 #define MT8196_PQ_OUT_CB6_TO_PANEL0_COMP_OUT_CB1 BIT(1) #define MT8196_PQ_OUT_CB7_MOUT_EN 0xe58 @@ -318,11 +336,13 @@ static const struct mtk_mmsys_routes mmsys_mt8196_ovl= 1_routing_table[] =3D { }; =20 /* - * main: DLI_ASYNC0-> PQ_IN_CB0 -> PQ_OUT_CB6 -> PANEL_COMP_OUT_CB1 -> DLO= _ASYNC1 + * main: DLI_ASYNC0-> PQ_IN_CB0 -> PQ (MDP_RSZ0/TDSHP0/CCORR0/CCORR1/GAMMA= 0/POSTMASK0/DITHER0) + * -> PQ_OUT_CB0 -> PANEL_COMP_OUT_CB1 -> DLO_ASYNC1 * ext: DLI_ASYNC1-> PQ_IN_CB1 -> PQ_OUT_CB7 -> PANEL_COMP_OUT_CB2 -> DLO= _ASYNC2 */ static const struct mtk_mmsys_routes mmsys_mt8196_disp0_routing_table[] = =3D { { + /* main: PQ bypass */ DDP_COMPONENT_DLI_ASYNC0, DDP_COMPONENT_DLO_ASYNC1, MT8196_PQ_IN_CB0_MOUT_EN, MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_6, MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_6 @@ -335,6 +355,52 @@ static const struct mtk_mmsys_routes mmsys_mt8196_disp= 0_routing_table[] =3D { MT8196_PANEL_COMP_OUT_CB1_MOUT_EN, MT8196_DISP_TO_DLO_RELAY1, MT8196_DISP_TO_DLO_RELAY1 }, { + /* main: PQ path */ + DDP_COMPONENT_DLI_ASYNC0, DDP_COMPONENT_MDP_RSZ0, + MT8196_PQ_IN_CB0_MOUT_EN, MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_0, + MT8196_PQ_IN_CB0_TO_PQ_OUT_CB_0 + }, { + DDP_COMPONENT_MDP_RSZ0, DDP_COMPONENT_TDSHP0, + MT8196_MDP_RSZ0_MOUT_EN, MT8196_MDP_RSZ0_TO_TDSHP0, + MT8196_MDP_RSZ0_TO_TDSHP0 + }, { + DDP_COMPONENT_TDSHP0, DDP_COMPONENT_CCORR0, + MT8196_DISP_TDSHP0_SOUT, MT8196_DISP_TDSHP0_TO_CCORR0, + MT8196_DISP_TDSHP0_TO_CCORR0 + }, { + DDP_COMPONENT_TDSHP0, DDP_COMPONENT_CCORR0, + MT8196_DISP_CCORR0_SEL, MT8196_DISP_CCORR0_FROM_TDSHP0, + MT8196_DISP_CCORR0_FROM_TDSHP0 + }, { + DDP_COMPONENT_CCORR0, DDP_COMPONENT_CCORR1, + MT8196_DISP_CCORR0_SOUT, MT8196_DISP_CCORR0_TO_CCORR1, + MT8196_DISP_CCORR0_TO_CCORR1 + }, { + DDP_COMPONENT_CCORR0, DDP_COMPONENT_CCORR1, + MT8196_DISP_CCORR1_SEL, MT8196_DISP_CCORR1_FROM_CCORR0, + MT8196_DISP_CCORR1_FROM_CCORR0 + }, { + DDP_COMPONENT_CCORR1, DDP_COMPONENT_GAMMA0, + MT8196_DISP_CCORR1_SOUT, MT8196_DISP_CCORR1_TO_GAMMA0, + MT8196_DISP_CCORR1_TO_GAMMA0 + }, { + DDP_COMPONENT_CCORR1, DDP_COMPONENT_GAMMA0, + MT8196_DISP_GAMMA0_SEL, MT8196_DISP_GAMMA0_FROM_CCORR1, + MT8196_DISP_GAMMA0_FROM_CCORR1 + }, { + DDP_COMPONENT_POSTMASK0, DDP_COMPONENT_DITHER0, + MT8196_DISP_POSTMASK0_SOUT, MT8196_DISP_POSTMASK0_TO_DITHER0, + MT8196_DISP_POSTMASK0_TO_DITHER0 + }, { + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DLO_ASYNC1, + MT8196_PQ_OUT_CB0_MOUT_EN, MT8196_PQ_OUT_CB0_TO_PANEL0_COMP_OUT_CB1, + MT8196_PQ_OUT_CB0_TO_PANEL0_COMP_OUT_CB1 + }, { + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DLO_ASYNC1, + MT8196_PANEL_COMP_OUT_CB1_MOUT_EN, MT8196_DISP_TO_DLO_RELAY1, + MT8196_DISP_TO_DLO_RELAY1 + }, { + /* ext */ DDP_COMPONENT_DLI_ASYNC1, DDP_COMPONENT_DLO_ASYNC2, MT8196_PQ_IN_CB1_MOUT_EN, MT8196_PQ_IN_CB1_TO_PQ_OUT_CB_7, MT8196_PQ_IN_CB1_TO_PQ_OUT_CB_7 diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mu= tex.c index f51d1cb5ad1e..ea2e5ce5ee53 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -263,6 +263,11 @@ #define MT8196_MUTEX_MOD1_OVL_DLO_ASYNC6 (32 + 17) =20 /* DISP0 */ + +#define MT8196_MUTEX_MOD0_DISP_CCORR0 6 +#define MT8196_MUTEX_MOD0_DISP_CCORR1 7 +#define MT8196_MUTEX_MOD0_DISP_DITHER0 14 + #define MT8196_MUTEX_MOD0_DISP_DLI_ASYNC0 16 #define MT8196_MUTEX_MOD0_DISP_DLI_ASYNC1 17 #define MT8196_MUTEX_MOD0_DISP_DLI_ASYNC8 24 @@ -270,6 +275,11 @@ #define MT8196_MUTEX_MOD1_DISP_DLO_ASYNC2 (32 + 2) #define MT8196_MUTEX_MOD1_DISP_DLO_ASYNC3 (32 + 3) =20 +#define MT8196_MUTEX_MOD1_DISP_GAMMA0 (32 + 9) +#define MT8196_MUTEX_MOD1_DISP_POSTMASK0 (32 + 14) +#define MT8196_MUTEX_MOD1_DISP_MDP_RSZ0 (32 + 18) +#define MT8196_MUTEX_MOD1_DISP_TDSHP0 (32 + 21) + /* DISP1 */ #define MT8196_MUTEX_MOD0_DISP1_DLI_ASYNC21 1 #define MT8196_MUTEX_MOD0_DISP1_DLI_ASYNC22 2 @@ -682,6 +692,13 @@ static const u8 mt8195_mutex_table_mod[MUTEX_MOD_IDX_M= AX] =3D { }; =20 static const u8 mt8196_mutex_mod[DDP_COMPONENT_ID_MAX] =3D { + [DDP_COMPONENT_CCORR0] =3D MT8196_MUTEX_MOD0_DISP_CCORR0, + [DDP_COMPONENT_CCORR1] =3D MT8196_MUTEX_MOD0_DISP_CCORR1, + [DDP_COMPONENT_DITHER0] =3D MT8196_MUTEX_MOD0_DISP_DITHER0, + [DDP_COMPONENT_GAMMA0] =3D MT8196_MUTEX_MOD1_DISP_GAMMA0, + [DDP_COMPONENT_MDP_RSZ0] =3D MT8196_MUTEX_MOD1_DISP_MDP_RSZ0, + [DDP_COMPONENT_POSTMASK0] =3D MT8196_MUTEX_MOD1_DISP_POSTMASK0, + [DDP_COMPONENT_TDSHP0] =3D MT8196_MUTEX_MOD1_DISP_TDSHP0, [DDP_COMPONENT_OVL0_EXDMA2] =3D MT8196_MUTEX_MOD0_OVL_EXDMA2, [DDP_COMPONENT_OVL0_EXDMA3] =3D MT8196_MUTEX_MOD0_OVL_EXDMA3, [DDP_COMPONENT_OVL0_EXDMA4] =3D MT8196_MUTEX_MOD0_OVL_EXDMA4, diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/med= iatek/mtk-mmsys.h index 4a0b10567581..250054ca5523 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -25,6 +25,8 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_AAL1, DDP_COMPONENT_BLS, DDP_COMPONENT_CCORR, + DDP_COMPONENT_CCORR0 =3D DDP_COMPONENT_CCORR, + DDP_COMPONENT_CCORR1, DDP_COMPONENT_COLOR0, DDP_COMPONENT_COLOR1, DDP_COMPONENT_DITHER0, @@ -51,6 +53,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_DVO0, DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_GAMMA, + DDP_COMPONENT_GAMMA0 =3D DDP_COMPONENT_GAMMA, DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MDP_RDMA2, @@ -59,6 +62,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_MDP_RDMA5, DDP_COMPONENT_MDP_RDMA6, DDP_COMPONENT_MDP_RDMA7, + DDP_COMPONENT_MDP_RSZ0, DDP_COMPONENT_MERGE0, DDP_COMPONENT_MERGE1, DDP_COMPONENT_MERGE2, @@ -130,6 +134,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_RDMA1, DDP_COMPONENT_RDMA2, DDP_COMPONENT_RDMA4, + DDP_COMPONENT_TDSHP0, DDP_COMPONENT_UFOE, DDP_COMPONENT_WDMA0, DDP_COMPONENT_WDMA1, --=20 2.45.2 From nobody Thu Dec 18 01:54:39 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A576A26658C for ; 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Lin" , Nancy Lin , Singo Chang , "Paul Chen --cc=devicetree @ vger . kernel . org" , , , , , , Sunny Shen Subject: [PATCH v2 4/5] drm/mediatek: Add MDP-RSZ component support for MT8196 Date: Mon, 21 Apr 2025 21:38:31 +0800 Message-ID: <20250421133835.508863-5-sunny.shen@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250421133835.508863-1-sunny.shen@mediatek.com> References: <20250421133835.508863-1-sunny.shen@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add MDP-RSZ component support for MT8196. Signed-off-by: Sunny Shen Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 24 ++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++ 3 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.c index 6628f5cd732a..04f13ca3601b 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -46,6 +46,9 @@ #define DSC_BYPASS BIT(4) #define DSC_UFOE_SEL BIT(16) =20 +#define DISP_REG_MDP_RSZ_INPUT_SIZE 0x0010 +#define DISP_REG_MDP_RSZ_OUTPUT_SIZE 0x0014 + #define DISP_REG_OD_EN 0x0000 #define DISP_REG_OD_CFG 0x0020 #define OD_RELAYMODE BIT(0) @@ -235,6 +238,19 @@ static void mtk_od_start(struct device *dev) writel(1, priv->regs + DISP_REG_OD_EN); } =20 +static void mtk_mdp_rsz_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_ddp_comp_dev *priv =3D dev_get_drvdata(dev); + + /* Set size =3D 0 for bypass mode */ + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, + DISP_REG_MDP_RSZ_INPUT_SIZE); + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, + DISP_REG_MDP_RSZ_OUTPUT_SIZE); +} + static void mtk_postmask_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -393,6 +409,12 @@ static const struct mtk_ddp_comp_funcs ddp_ovlsys_adap= tor =3D { .get_num_formats =3D mtk_ovlsys_adaptor_get_num_formats, }; =20 +static const struct mtk_ddp_comp_funcs ddp_mdp_rsz =3D { + .clk_enable =3D mtk_ddp_clk_enable, + .clk_disable =3D mtk_ddp_clk_disable, + .config =3D mtk_mdp_rsz_config, +}; + static const struct mtk_ddp_comp_funcs ddp_postmask =3D { .clk_enable =3D mtk_ddp_clk_enable, .clk_disable =3D mtk_ddp_clk_disable, @@ -456,6 +478,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COM= P_TYPE_MAX] =3D { [MTK_DISP_DITHER] =3D "dither", [MTK_DISP_DSC] =3D "dsc", [MTK_DISP_GAMMA] =3D "gamma", + [MTK_DISP_MDP_RSZ] =3D "mdp-rsz", [MTK_DISP_MERGE] =3D "merge", [MTK_DISP_MUTEX] =3D "mutex", [MTK_DISP_OD] =3D "od", @@ -515,6 +538,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[= DDP_COMPONENT_DRM_ID_MAX] [DDP_COMPONENT_DSI2] =3D { MTK_DSI, 2, &ddp_dsi }, [DDP_COMPONENT_DSI3] =3D { MTK_DSI, 3, &ddp_dsi }, [DDP_COMPONENT_GAMMA] =3D { MTK_DISP_GAMMA, 0, &ddp_gamma }, + [DDP_COMPONENT_MDP_RSZ0] =3D { MTK_DISP_MDP_RSZ, 0, &ddp_mdp_rsz}, [DDP_COMPONENT_MERGE0] =3D { MTK_DISP_MERGE, 0, &ddp_merge }, [DDP_COMPONENT_MERGE1] =3D { MTK_DISP_MERGE, 1, &ddp_merge }, [DDP_COMPONENT_MERGE2] =3D { MTK_DISP_MERGE, 2, &ddp_merge }, diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.h index badb42bd4f7c..87f573fcc903 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h @@ -36,6 +36,7 @@ enum mtk_ddp_comp_type { MTK_DISP_OVLSYS_ADAPTOR, MTK_DISP_OVL_2L, MTK_DISP_OVL_ADAPTOR, + MTK_DISP_MDP_RSZ, MTK_DISP_POSTMASK, MTK_DISP_PWM, MTK_DISP_RDMA, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index 70a7e6d06d4f..aa7eec1fc7e6 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -975,6 +975,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = =3D { .data =3D (void *)MTK_DSI }, { .compatible =3D "mediatek,mt8188-dsi", .data =3D (void *)MTK_DSI }, + { .compatible =3D "mediatek,mt8196-mdp-rsz", + .data =3D (void *)MTK_DISP_MDP_RSZ }, { } }; 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Mon, 21 Apr 2025 21:38:53 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 21 Apr 2025 21:38:53 +0800 From: Sunny Shen To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chun-Kuang Hu , AngeloGioacchino Del Regno CC: Matthias Brugger , Philipp Zabel , Fei Shao , Pin-yen Lin , "Jason-JH . Lin" , Nancy Lin , Singo Chang , "Paul Chen --cc=devicetree @ vger . kernel . org" , , , , , , Sunny Shen , CK Hu Subject: [PATCH v2 5/5] drm/mediatek: Change main display path to support PQ for MT8196 Date: Mon, 21 Apr 2025 21:38:32 +0800 Message-ID: <20250421133835.508863-6-sunny.shen@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250421133835.508863-1-sunny.shen@mediatek.com> References: <20250421133835.508863-1-sunny.shen@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Due to the path mux design of the MT8196, the following components need to be added to support Picture Quality (PQ) in the main display path: CCORR0, CCORR1, DITHER0, GAMMA0, MDP_RSZ0, POSTMASK0, TDSHP0. Signed-off-by: Sunny Shen Reviewed-by: CK Hu --- The method of using OF graph for display path is still under investigation. --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index aa7eec1fc7e6..5ca2b9badbe0 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -242,6 +242,13 @@ static const unsigned int mt8196_mtk_ddp_ovl0_main[] = =3D { =20 static const unsigned int mt8196_mtk_ddp_disp0_main[] =3D { DDP_COMPONENT_DLI_ASYNC0, + DDP_COMPONENT_MDP_RSZ0, + DDP_COMPONENT_TDSHP0, + DDP_COMPONENT_CCORR0, + DDP_COMPONENT_CCORR1, + DDP_COMPONENT_GAMMA0, + DDP_COMPONENT_POSTMASK0, + DDP_COMPONENT_DITHER0, DDP_COMPONENT_DLO_ASYNC1, }; =20 --=20 2.45.2